JP2002358783A - Data input/output method, and dram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data input/output method which can minimize losses of data interruption at the time of switching between reading and writing in a DRAM using a common input/output section for reading and writing data, and to provide a DRAM. SOLUTION: This data input/output method comprises a step for holding predetermined data from a memory array 12 by a read command of m-th (m is integer), a step for outputting the data to a common input/output section 30 and holding new data from the memory array 12 upon (m+1)-th read command, a step for holding the data from the common input/output section 30 upon n-th (n is integer) write command, and a step for storing the data in the memory array 12 and holding new data from the common input/output section 30 upon (n+1)-th write command.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor using a common input / output unit (Common I / O) for reading and writing data.
Data input / output method and DRA in a RAM (Dynamic Random Access Memory) that minimizes loss of data interruption when switching between reading and writing
About M. By applying it to a DRAM capable of seamless row-to-row seamless access, it is possible to have a true Random Row Access function without any banks. The present invention also relates to a data input / output method and a DRAM that can always maintain the peak data rate of a memory system even in applications where reading and writing are frequently switched.

[0002]

2. Description of the Related Art The speed of a DRAM is MPU (Micro Proces).
sor Unit) is a bottleneck in computer performance. Therefore, SDRAM
(Synchronous Dynamic RAM) and various high-speed schemes represented by a burst mode of RAMBUS are used.
These are all based on a page mode for extracting data latched (held) by a conventional sense amplifier.
Also, so that the data to be accessed is at the address latched by the activated sense amplifier as much as possible,
A large number of sense amplifiers are activated. Furthermore, by providing a large number of banks to increase the amount of data latched by the sense amplifier, or by accessing another bank in the case where an address that is not present in the latched sense amplifier in one bank is accessed. Speeding up.

However, under actual use conditions, access to the memory is basically random row access for accessing an arbitrary row address (word line). In these conventional memories, although the actual use is random row access, it is avoided as much as possible to increase the speed according to the page mode or bank. Therefore, when an access comes within the same bank, data is interrupted between bursts. In particular, when reading and writing are switched one after another, the effect becomes extremely large.

FIG. 5 shows the SDRAM DDR (Double D).
ata Rate). CAS (Column Address St
robe) Latency (Latency) is 2, burst length (Bur)
stLength) is 8, and reading and writing alternately come to addresses in the same bank. Data input / output (Da
There is a large sky between bursts at ta I / O). There are 18 clocks in one cycle of read and write operations, during which read and write of 8 bursts are performed at both edges of the clock. Thus, of the 36 clock edges, only 16 clock edges are actually processing data. The data rate in this case indicates that it is only 16/36 = 44% as compared with the peak when all edges are filled.
This means that even when operating with a 200 MHz clock, the actual data rate is only the data rate obtained with a 88 MHz clock. In such an actual random row access environment in which reading and writing are frequently switched, there is a disadvantage that the data rate cannot be increased.

[0005] As a countermeasure for the above-mentioned random row access, seamless row-to-row access will be described. A memory array of a memory is basically a matrix in which word lines and bit lines are orthogonal to each other, and cannot access another next address while either of them is operating. A period from the rise of the word line to the completion of the equalization of the bit line is called an array time constant. In other words, the cycle time of the memory can in principle be reduced to this array time constant. Prefetch (Prefect
h) Pre-loading (Preload) greatly reduces the array time constant, making it shorter than the time required for bursting, enabling seamless row-to-row access.

FIG. 6 shows an operation under the same read and write conditions as in FIG. Since the page mode is abolished and all accesses are precharged immediately after prefetching data or simultaneous writing of preloaded data, the command is issued by RAS (Raw Address Strobe) like SDRAM. ) And CAS, and a single command that distinguishes between read and write is given together with the row and column addresses.

In FIG. 6, as compared with FIG. 5, the empty time of data input / output (the time when there is no data) is greatly reduced due to the shortened array time constant. 1 between bursts
There is empty for clock. This space is necessary to prevent data collision on the bus between the memory and the driver of the controller chip. If both chips use an open-drain driver that is pulled up externally (Pull-up), this one-clock empty is unnecessary and all bursts are connected without interruption. Therefore, it can be said that this can be accessed at the peak data rate.

However, the actual reading and writing are not simply repeated as described above, but the reading and writing are performed in an arbitrary pattern. For example, as shown in FIG. 7, in the case where reading is performed twice and writing is performed once, data is processed at 24 clock edges during 42 clock edges, and the data rate is 24/42 = 57 ( %). The data rate is better than 44% of the data rate shown in FIG. 5, but still low at 57%. In the above method, reading and writing are on different buses, so writing can be done at the same timing for reading and busing, and the array time constant for writing can be brought immediately after the array time constant for the second reading. it can. However, it is difficult to increase the data rate when a common input / output unit is used.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to provide a DRA using a common input / output unit for reading and writing data.
M, at the time of switching between reading and writing,
An object of the present invention is to provide a data input / output method and a DRAM capable of minimizing a loss of data interruption.

[0010]

SUMMARY OF THE INVENTION The gist of the data input / output method of the present invention is to provide a data input / output method in a DRAM using a common input / output unit for reading and writing data. Holding the predetermined data from the memory array with the read instruction
Outputting the data to the common input / output unit by an (m + 1) th read instruction and holding new data from the memory array; and outputting the data from the common input / output unit by an nth (n is an integer) write instruction. And storing the new data from the common input / output unit by storing the data in the memory array by the (n + 1) th write command.

The gist of the DRAM of the present invention is as follows.
In a DRAM including a prefetch / latch circuit for holding data from a memory array and a preload / latch circuit for holding data from a common input / output unit, the prefetch / latch circuit is an m-th (m is an integer) Means for holding predetermined data from the memory array by a read instruction; means for outputting the predetermined data to the common input / output unit by a (m + 1) th read instruction; and means for storing the predetermined data from the memory array by a (m + 1) th read instruction. Means for holding predetermined data from the common input / output unit in response to an n-th (n is an integer) write instruction, and means for holding predetermined data from the common input / output unit. n + 1)
And a means for storing the new data from the common input / output unit with the (n + 1) th write command.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Data input / output method and D of the present invention
An embodiment of a RAM will be described with reference to the drawings.

As shown in FIG. 1, a DRAM 10 of the present invention
Includes a prefetch latch circuit 24 and a preload latch circuit 26. The prefetch latch circuit 24
Means for holding predetermined data from the memory array 12 by an m-th (m is an integer) read instruction; means for outputting data to the common input / output unit 30 by an (m + 1) -th read instruction;
Further, the memory array 12 is read by the (m + 1) th read command.
Including means for retaining new data from The preload / latch circuit 26 holds a predetermined data from the common input / output unit 30 by an n-th (n is an integer) write command, and stores data in the memory array 12 by a (n + 1) -th write command. And means for holding new data from the common input / output unit 30 by the (n + 1) th write command.

In addition, like a general DRAM, the DRAM 10 of the present invention includes a memory array 12 for storing data, a row selector 18 for selecting a word line 14 of the memory array 12, and a bit line 16 for the memory array 12. It includes a column selector 20 to be selected, a sense amplifier 22 from which data of the word line 14 selected by the row selector 18 is read, and an output buffer 28 connected to a prefetch latch circuit 24. Further, a data input line 32 and a data output line 34 connected to the preload / latch circuit 26 and the output buffer 28 are connected to a common input / output unit 30.

In the DRAM 10 of the present invention, the data latched by the prefetch latch circuit 24 and the preload latch circuit 26 is 8 bits, but 2 bits, 4 bits.
It may be multiple bits such as 16 bits. The memory array 12 includes a word line 14 and a bit line 16 arranged in a matrix, and the word line 14 and the bit line 1.
There are cells at the positions of the six grids, and data is stored in these cells. The memory array 12 is divided into a plurality of blocks, and data input / output is performed for each block.

Next, a data input / output method in the DRAM 10 of the present invention will be described. As shown in FIG.
The reason that a large empty space is generated between bursts is that the command, the array time constant, and the temporal relative positions of the three elements of the burst are significantly different between read and write. This can be said from the fact that there is no interruption between bursts when only reading is performed or when only writing is performed. Conversely, the relative time positions of these three factors are
If the same is used for reading and writing, it indicates that any arbitrary combination of reading and writing can be accessed without interruption.

Therefore, the present invention is to match the writing to the three elements of reading, and this procedure is shown in FIG. Note that the m-th (m is an integer) read instruction is Rm, and the n-th read instruction is
(N is an integer) a write instruction is Wn. Further, the square frame in the middle of the figure indicates the array time constant. In the figure, data to be read by the command Rm is r
m, and data to be written by the command Wn is wn.

The read command (instruction) R01 is two clocks before the array time constant, and the burst of data r1 has the same timing as the array time constant after the next read command R02. On the other hand, W01 of the write command (instruction) is four clocks before the array time constant, because it is the head of the write data w1. Since the start of the operation of the word line 14 is the head of the array time constant, this is changed to the position of W01N, which is the same two clocks as for reading.

Next, at the burst position of the write data w1, since the burst cannot be started before the command, the clock is delayed by 4 clocks, and the write latency is set to 2 clocks so as to have the same timing as the array time constant of W01. That is, the data w1 is changed to the position of the data w1n. However, at this timing, data cannot be written to the array time constant of W01, and the data burst by the W01N command and latched by the preload / latch circuit 24 at the location corresponding to the original array time constant of W02 is stored in the memory array 12. Write to cell. The relative time between the command and the array time constant in writing and reading becomes the same in reading and writing. As described above, in FIG. 2, the write data is shown at the upper to lower positions of the data input / output.

In this state, the command and the array time constant of the burst position are both temporally aligned (aligned), but the read time is the same as the array time constant that the burst comes next, and the write time is the previous burst. There is a difference that it is aligned with the array time constant. That is, from the viewpoint of the array time constant, the burst position is shifted in the opposite direction by one array time constant between read and write. Therefore, when reading and writing are successively performed, the array time constants are adjacent to each other well, but the burst positions of reading and writing are exactly the same, so that it must be shifted by one or more bursts after all. A big sky is created. To eliminate the gap between bursts in a mixed read and write condition, you need the flexibility to relatively change the array time constant and burst position while keeping the command and array time constant positions constant. It is.

Such a mechanism is performed as the next step by setting the processing contents of the command. In writing, W01N
The data w1n burst by the command of
The data stored in the latch circuit is written to the cell at the position of the second array time constant after the completion of the burst. W01
In the command of N, the address (word line and bit line) is ignored and the start of the burst is indicated by latency 2 (after 2 clocks). Second command W02N
Is a command to start the second burst similar to the first, and it is assumed that data w1n burst-input by the command of W01N is written into the cell at the address entered here. As described above, the present invention is a two-stage command system in which a command is used in two stages to complete a series of burst write operations.

Although the timing of reading is not changed, the command is of a two-stage system as in the case of writing. Although the address is also given by the command of R01 and the data r1 proceeds until the data r1 is latched by the prefetch latch circuit 24, the start of the burst is kicked by the next read command R02. R02 is also a command that receives the second address at the same time and starts activation of the next block.

To summarize the above, predetermined data is held from the memory array 12 by the m-th read command, and the (m +
The data is output to the common input / output unit by the read command of 1),
New data is held from the memory array 12. The predetermined data from the common input / output unit is held by the n-th write command, the data is stored in the memory array 12 by the (n + 1) th write command, and new data is held from the common input / output unit.

In the two-step command system, it is convenient to be able to distinguish the last command (instruction) in the case of reading and the first command (instruction) in the case of writing for each certain continuous access chunk. Therefore, there is a method of giving each of them an identification signal (End Point Signal). For example, if the identification signal is high (High) and a write operation is performed, the identification signal is recognized as the first command in a continuous access block, the address is ignored, and the block is not activated. Used only as the beginning of a burst of write data.

If the identification signal is high at the time of a read command, this identification signal is recognized as the last command of a continuous access block, and this command starts a burst of read data previously latched by the prefetch latch circuit. The following blocks are not activated.

As another method, without providing a signal line for the identification signal, an end point (End Poin
t) or not. The command is enabled if it is low at the rising edge of the clock.
If this becomes low from the falling edge of the clock before that clock and the next rising is also low, this is the last command. That is, if a row is detected at the falling edge of such a command that is wide by 1/2 clock and this command is read or written, this command ignores the address, does not activate the block, and kicks the burst. Treated as a signal.

As described above, FIG. 2 shows that bursts are connected without interruption when only read and write are successively performed. In such a two-step command system, even when reading and writing come in an arbitrary combination, the array time constant and the burst position can be flexibly moved while aligning these two timings according to the order of reading and writing. Processing can be performed without interruption between bursts of data input / output. An example will be described below.

FIG. 3 shows a simple pattern in which a read command and a write command alternate. Since the read address is given by R01, the data r1 burst by 8 bits is stored in the prefetch latch circuit 2
4, but there is no next read command to kick the burst, so the prefetch latch circuit 24
Is held. The next command is a write command of W01, and a write burst starts at T1 which is two latencies behind, but the address here is ignored and there is no second write command, so the input data w1 is preloaded. -It is held by the latch circuit 26.

Next, when a read command of R02 comes,
At T2, the first burst of read data r1 held in the prefetch latch circuit 24 is kicked at T2, and at the same time, the next read address is fetched to activate this block. Next, when a write command of W02 comes, the next burst input is kicked at T3, and at the same time, the burst input is input to the given address at T1 and the data w1 held by the preload latch circuit 26 is stored in the memory array. 12 is written.

FIG. 4 shows a case where the read operation is repeated twice and the write operation is performed once thereafter. However, the continuous read operation is completely empty because there is no bus collision between bursts. All are connected except for one clock empty to prevent bus collision necessary only at the time of switching between write and write.

As described above, the two-step command method for adjusting the relative time between the read and write commands and the array time constant and providing flexibility in the array time constant and the burst position requires a data rate in actual use. Always at peak data rate. Although this is shown in the above pattern, any combination of reading and writing is also effective. In order to prevent a collision on the data input / output bus, an empty one clock is provided at the time of switching between read and write. However, if the read is continued as shown in FIG. 4, there is no empty space between bursts. Also, in the case of continued writing, the bursts are completely connected. Therefore, the worst data rate in actual use is the pattern of FIG. 3 in which reading and writing alternate, which is 8/10 of the peak data rate.
= 80%. This means that data input / output is performed at the edge of four clocks out of the edge of five clocks.
The worst value of 80% has not been obtained by any other method. If bus collision is prevented, there is no empty space for one clock at the time of switching. Of 10
True random row access with 0% always maintained.

The access time varies depending on the next command. However, in any system, particularly when a large amount of data is to be processed at a high speed, reading or writing is not performed in one shot, but is performed continuously. Is accessed. Therefore, the slow access time does not become a hindrance at all, but rather it is most important how the data rate in actual use approaches the peak data rate possible for the memory system. Therefore, the present invention which can be completely seamless by random row access has a great merit.

In the two-step command, the first write command only kicks the burst, and the address has to wait until the next. Therefore, the address can be considered as a dummy command, and the read requires a dummy read command at the end. , These become overhead. However, in an actual system, the access comes continuously for a long time, so that the overhead of the two-step command can be completely ignored.

Further, a flexible access method can be used by a combination of reading and writing. For example, if reading and writing are switched frequently, the second command to complete a series of cycles comes earlier as shown in FIGS. The identification signal may be used once for the last reading.

When one of the read command and the write command is large and the other comes only occasionally, the smaller second command is difficult to come,
Since it takes time to complete the operation, the operation can be immediately completed using the identification signal. For example, when a write command comes only once during several tens of read commands, the first write command sets the identification signal high for each of the few write commands, and then after an array time constant immediately thereafter. Then, the write command and the identification signal are set to low again to input an address, thereby completing the write to the cell.

As described above, the data input / output method and DR of the present invention
Although the embodiment has been described for AM, the present invention is not limited to the above embodiment. For example, data reading and writing were performed, but only data writing,
Alternatively, only data reading may be performed.

In addition, the present invention can be implemented in various modified, modified, and modified forms based on the knowledge of those skilled in the art without departing from the spirit of the present invention.

[0038]

The data input / output method and DRAM of the present invention
According to this, even when switching between reading and writing in the common input / output unit, data can be accessed without interruption other than empty to prevent data collision. This method can be applied to memories using all common input / output units.However, by using the memory for seamless row-to-row access, it is possible to switch between any address and any read / write. On the other hand, true random row access performance that can always maintain the peak data rate can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a DRAM of the present invention.

FIG. 2 is a diagram showing data input / output when data reading is performed twice and writing is continued twice.

FIG. 3 is a diagram showing data input / output when data reading and writing are performed alternately.

FIG. 4 is a diagram showing data input / output in a case where data writing is performed while data reading is continued twice, and between the two readings and the next two readings are performed.

FIG. 5 is a diagram showing conventional data input / output.

6 is a diagram showing a conventional data input / output in which the data input / output of FIG. 5 is improved.

7 is a diagram showing data input / output when data reading and writing become complicated in the data input / output of FIG. 6;

[Explanation of symbols]

 10: DRAM 12: Memory array 14: Word line 16: Bit line 18: Row selector 20: Column selector 22: Sense amplifier 24: Prefetch latch circuit 26: Preload latch circuit 28: Output buffer 30: Common input / output Part 32: Data input line 34: Data output line r1, r2, r3: Read data w1, w2, w3, w1n, w2n: Write data

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor: Toshio Sunaga, 800 Miyake, Yasu-machi, Yasu-cho, Yasu-gun, Shiga Prefecture IBM Japan, Ltd. 1623 No. 14 IBM Japan, Ltd. Yamato Plant F-term (reference) 5M024 AA49 BB03 BB04 BB33 BB34 DD39 DD59 DD83 JJ02 JJ32 LL01 PP01 PP07

Claims (12)

[Claims] 1. A data input / output method in a DRAM using a common input / output unit for reading and writing data, wherein a predetermined data from a memory array is held by an m-th (m is an integer) read command; The (m +
Outputting the predetermined data to the common input / output unit in response to the read command of 1), and holding new data from the memory array. 2. A data input / output method in a DRAM using a common input / output unit for reading and writing data, wherein predetermined data from the common input / output unit is held by an n-th (n is an integer) write command. Step and (n
+1) storing the predetermined data in a memory array in response to a write command, and holding new data from the common input / output unit. 3. A data input / output method in a DRAM using a common input / output unit for reading and writing data, wherein a predetermined data from the memory array is held by an m-th (m is an integer) read command; The (m +
(1) outputting the predetermined data to the common input / output unit by the read command and holding new data from the memory array; and outputting the predetermined data from the common input / output unit by the n-th (n is an integer) write command. And a step of storing the predetermined data in a memory array by an (n + 1) th write command and holding new data from the common input / output unit. Method. 4. A method according to claim 1, wherein, among the plurality of read instructions, a step of identifying a last read instruction, and a step of outputting data held when the last read instruction is identified to the common input / output unit. The data input / output method according to claim 1 or 3, further comprising: 5. The method according to claim 1, further comprising the step of: identifying a last write instruction in the plurality of write instructions; and storing data held when the last write instruction is identified in a memory array. 2 or 3
Data input / output method described in 1. 6. The data input / output method according to claim 1, wherein the step of outputting the held data to a common input / output unit is performed by a multi-bit burst. 7. The data input / output method according to claim 2, wherein the step of storing the held data in a memory array is performed by a multi-bit burst. 8. A DRAM including a prefetch / latch circuit for holding data from a memory array and a preload / latch circuit for holding data from a common input / output unit.
In the above, the prefetch latch circuit is connected to the m-th (m
Means for holding predetermined data from the memory array by a (m) integer readout instruction, means for outputting the predetermined data to the common input / output unit by a (m + 1) th readout instruction, and (m + 1) th readout instruction Means for holding new data from the memory array with instructions. 9. A DRAM including a prefetch / latch circuit holding data from a memory array and a preload / latch circuit holding data from a common input / output unit.
Wherein the preload / latch circuit stores predetermined data from the common input / output unit by an n-th (n is an integer) write instruction, and stores the predetermined data by a (n + 1) -th write instruction in a memory. Means for storing in the array;
Means for holding new data from the common input / output unit in response to an (n + 1) th write command. 10. A DRA comprising: a prefetch / latch circuit for holding data from a memory array; and a preload / latch circuit for holding data from a common input / output unit.
M, the prefetch latch circuit is connected to the m-th
Means for holding predetermined data from the memory array by a (m is an integer) read instruction, means for outputting the predetermined data to the common input / output unit by a (m + 1) th read instruction, Means for holding new data from the memory array by a read command, and wherein the preload / latch circuit holds predetermined data from the common input / output unit by an n-th (n is an integer) write command. Means for storing the predetermined data in the memory array by a (n + 1) th write command, and means for holding new data from the common input / output unit by a (n + 1) th write command. Including DRAM. 11. The data input / output method according to claim 8, wherein, among the plurality of read commands, an identification signal indicating that the command is the last is added to the last read command. 12. The data input / output method according to claim 9, wherein, among the plurality of write commands, an identification signal indicating that the command is the first is added to a first write command.