JPH04356789A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To convert a defective product into a nondefective product and to increase the yield by setting a switching circuit so as to generate a control signal of an active level when a reading error is found at a function test. CONSTITUTION:When a control signal DS from a switching circuit 5 is set at a low level in an open state of a pad PD, a sense amplifier activation signal SE goes forward through the paths of a delay element D1, a NAND gate G2 and an inverter circuit IV3 and a selection signal YSW is obtained. When it is decided as a nondefective product through the function test in this state, a fuse F2 of the circuit 5 is melted and cut and the signal DS is made eternally to a low level. On the other hand, when a reading error is detected, a pad PD is made to a ground potential and when the signal DS is made at a high level, the signal SE goes forward through the paths of elements D1, D2, a circuit IV2, gates G1, G2 and a circuit IV3. The function test in this state is again conducted and if it is a nondefective product, a fuse F1 is melt and cut.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that allows a device conventionally considered to be defective to be used as a non-defective device without relying on redundant circuits.

0002

2. Description of the Related Art In general, a semiconductor memory device includes a memory cell array consisting of a plurality of memory cells arranged in an array and a plurality of bit lines and word lines respectively connected to the memory cells, and a memory cell array for selecting a predetermined memory cell. A row decoder and a column decoder are respectively arranged adjacent to this memory cell array so as to be able to do so. The plurality of bit lines constituting this memory cell array consist of a plurality of bit line pairs whose levels are complementary to each other, and one sense amplifier is provided for each of these bit line pairs. These sense amplifiers are activated in response to a sense amplifier activation signal, and amplify the potential difference between the two bit lines forming the bit line pair.

A selection switch selects one bit line pair in response to a selection signal from a column decoder, and electrically connects the bit line pair to an I/O line for reading and writing data to memory cells. do.

In such a conventional semiconductor memory device, the connection between a predetermined bit line pair and an I/O line when reading data is such that the potential difference between the bit line pair is sufficiently amplified by the sense amplifier. As will be done later, the column decoder is controlled by a signal obtained by delaying the sense amplifier activation signal. That is, after a period (approximately 6 nS to 10 nS) necessary for the sense amplifier to operate in response to the sense amplifier activation signal and sufficiently amplify the potential difference between the bit line pair,
The sense amplifier activation signal is delayed for a predetermined period of time (6 to 10
nS), and when this delayed signal is applied to the column decoder, a selection signal is generated.

[0005]

[Problems to be Solved by the Invention] Generally speaking, functional tests of semiconductor memory devices are performed in the wafer state, and if a defective part is found, the defective part is corrected with redundant bit lines or redundant word lines and the product is returned as a good product. There is. There are various factors that can cause a defective point to occur, but during the period from the activation of the sense amplifier described above to the operation of the selection switch, the sense amplifier cannot sufficiently amplify the potential difference between the bit line pair and the bit line pair and the I/O. One of these is read errors due to electrical connections being made to lines. In other words, there may be cases where the potential difference between the bit line pair is small due to variations in the characteristics of the transistors or capacitive elements that make up the selected memory cell, or cases where the performance of the sense amplifier is degraded due to variations in the characteristics of the elements that make up the sense amplifier. be. In such a case, it is not possible to amplify the potential difference between the bit line pair by the sense amplifier to a sufficient level within a predetermined time. If a connection is formed between the bit line pair and the I/O line in this state, not only will the read time become longer, but in some cases, the potential levels of the bit line pair may be reversed, resulting in a read error. be.

Conventionally, read errors due to the above-mentioned causes have been resolved by replacing the relevant bit line pair with a redundant bit line. However, when there are many bit line pairs with such read errors, it is not possible to replace all the bit line pairs that cause read errors with redundant bit lines, which has the disadvantage of decreasing yield and increasing cost. .

Therefore, an object of the present invention is to provide a semiconductor memory device that can use a semiconductor memory wafer that takes a long time to rise for amplifying the potential difference between a pair of bit lines as a non-defective product without using a redundant circuit. be.

[0008]

A semiconductor memory device of the present invention includes a plurality of memory cells arranged in an array, and a plurality of bit lines and word lines respectively connected to the memory cells. a memory cell array arranged as a pair of two lines, a sense amplifier provided for each of the bit line pairs and amplifying the potential difference between the bit line pairs in accordance with an activation signal, and a switching circuit. a delay circuit that applies a delay that varies according to a control signal from the activation signal to the activation signal to generate a selection signal; and a selection switch that connects a predetermined bit line pair and an I/O line according to the selection signal. means.

Preferably, this switching circuit includes a first output means for arbitrarily changing the level of the control signal, and a fuse provided between a power terminal and an output terminal for outputting the control signal at a fixed level. and second output means.

0010

Embodiment An embodiment of the present invention will be described with reference to FIG. In FIG. 1, a memory cell array 1 is composed of a plurality of memory cells each consisting of one N-channel transistor and one capacitive element, arranged in an array (so-called 1-transistor-1-capacitor type cells MC are arranged in an array). ). Bit lines BLa and B
Lb is connected to each sense amplifier SA as a pair. Sense amplifier SA receives sense amplifier activation signal SE.
, and amplifies the potential difference between bit line pair BLa and BLb.

The row decoder 2 is connected to one of the plurality of word lines WL.
A book is selected according to the input row address (RA) and its potential is set to high level. Column decoder 3 receives selection signal Y
When SW is supplied, one of the selection signals Y1, Y2, Y3, . The selection switch 4 receives selection signals Y1, Y2, Y3,...Yn from the column decoder 3 at its gate, and selects the source and
The drain path is constituted by a group of transistors provided between the input/output terminal of the sense amplifier SA and the wirings La and Lb forming the I/O line.

The bit line pair BLa and BLb selected by the selection switch 4 are connected to wirings La and Lb, respectively. These wirings La and Lb supply read data and write data in a complementary manner, and one end is connected to data amplifier 7 and write amplifier 8. A selection signal YSW is also input to these data amplifier 7 and write amplifier 8, and their activation is controlled.

Delay circuit 6 receives sense amplifier activation signal SE.
A selection signal YSW is generated which is delayed by a predetermined time depending on the level of the control signal DS from the switching circuit 5. That is, when the control signal DS is at an inactive level, the selection signal YSW is generated delayed by a predetermined time (6 to 10 nS) from the sense amplifier activation signal SE. When the control signal DS is at the active level, the control signal DS is kept for a predetermined period of time (2 to 4 nS) longer than the selection signal YSW when the selection signal DS is at the inactive level.
) Generates a delayed selection signal YSW.

The level setting of the control signal DS generated by the switching circuit 5 is performed in accordance with the results of a functional test in the wafer state.

Next, the operation of this embodiment, particularly the read operation, will be explained with reference to FIG. First, when a row active RAS signal is input from the outside (see FIG. 2(a)), a row address (RA) is supplied from the outside to the row decoder 2 (FIG. 1) via an address buffer (not shown). (See Figure 2(c)). The row decoder 2 selects one word line WL according to the supplied RA and sets its potential to a high level (see FIG. 2(d)). B forming a bit line pair according to the information of 0 or 1 stored in the memory cell MC under the word line WL that has become high level.
The potential of one of La and BLb decreases (see Figure 2(f)).
, the voltage levels of these two bit lines have a complementary relationship.

Next, the sense amplifier activation signal SE is activated at time t.
When it is 0, it becomes an active level (see FIG. 2(e)), and all sense amplifiers SA are activated. The activated sense amplifier SA immediately increases the potential difference between the bit line pair, that is, BL.
The potential difference between a and BLb begins to be amplified, and one potential is close to the power supply potential (Vcc) and the other potential is the ground potential (GND).
(See the dotted line in FIG. 2(f)).

Next, when a row active CAS signal is input from the outside (see FIG. 2(b)), a column address (CA) is supplied from the outside to the column decoder 3 via the address buffer (see FIG. 2(b)). (see (c)). Delay circuit 6
When the level of the control signal DS is at the inactive level, the selection signal YSW is set to the active level at time t10 by delaying the sense amplifier activation signal SE by DT0 (see the dotted line in FIG. 2(g)).

Here, if the sense amplifier SA operates as designed, the selection signal YS
At time t10 when W becomes active level, the potential difference between BLa and BLb forming the bit line pair is equal to the power supply potential Vcc.
Get closer. When the selection signal YSW becomes active level, the column decoder 3 sets any one of the selection signals Y1, Y2, ...Yn to active level (high level) according to the input CA, so that a set of corresponding signals is activated. The bit line pair is selected by the selection switch 4 (see FIG. 1).
.

The bit line BLa selected by the selection switch 4 is electrically connected to the wiring La, and the bit line BLb
is connected to the wiring Lb, one of the wirings La and Lb maintains the Vcc level, and the potential of the other wiring is lowered to the low level by the sense amplifier SA of the selected bit line pair.

The potential difference between the wirings La and Lb is determined by the selection signal Y.
The data amplifier 7 activated by the SW further amplifies the amplified data and outputs it as read data to an input/output terminal (not shown) via a common data bus, thereby completing one data read operation.

The read operation described above is performed by the sense amplifier S.
A is a case where the potential difference between the bit line pair is amplified within a predetermined time. However, the potential difference between the bit line pair may be small due to variations in the characteristics of the transistors or capacitors that make up the selected memory cell, or the performance of the sense amplifier may deteriorate due to variations in the characteristics of the elements that make up the sense amplifier. In such a case, the potential difference between the bit line pair is not sufficiently amplified at time t10 indicated by the solid line in FIG. 2(f). In this state, when the selection signal YSW becomes active level and the column decoder 3 sets one selection signal to the selection switch 4 at active level, the bit line pair whose potential difference is not sufficiently amplified and the I/O line are connected. That will happen. As a result, not only does reading take longer, but in some cases the levels of the bit line pair may be reversed, resulting in a reading error.

Such a read error is detected by a functional test when the semiconductor memory device is in a wafer state. Previously, when a read error occurred, a redundant circuit was used to replace the defective part and the product was returned to good condition.
If a product has so many defective parts that it cannot be replaced with redundant circuits, it is treated as a defective product. However, the inventor of the present invention has discovered that read errors caused by a long rise time required for amplifying the differential potential between a pair of bit lines can be relieved by giving a predetermined delay to the selection signal YSW. By taking this measure, a product that conventionally had to be treated as a defective product can be made into a non-defective product without relying on redundant circuits.

That is, when a read error is detected by the functional test, the switching circuit 5 is set to generate the active level control signal DS. When the control signal DS becomes active level, the delay circuit 6 outputs the selection signal Y after the sense amplifier activation signal SE becomes active level.
Delay time DT0 until SW reaches active level
(see FIG. 2) is further delayed by DT1, and the selection signal YSW becomes active level at time t20 (see FIG. 2(g)).
)) Change the delay time as shown in the solid line).

At time t20, bit line pair BLa, BL
While the potential difference between bit lines BLa and BLb is sufficiently amplified (see the solid line in Figure (f)), the selection signal YSW becomes active level at that point, and the connection between the bit line pair BLa and BLb and the I/O line is formed. Then reading is performed normally.

[0025] In a product containing a read error detected by a functional test, the active level control signal DS
By setting the switching circuit 5 to generate , read errors can be eliminated. In that case, by permanently setting the switching circuit 5 so that the control signal DS is at the active level, it becomes possible to treat products that were conventionally treated as defective as good products, improving yields and reducing costs. can contribute to The read time delay DT1 due to this method is about 2 to 4 nS. This degree of delay in read time is more than compensated for by a dramatic improvement in yield.

Although the embodiments of the present invention have been described in detail for read operations, the present invention can also be applied to write operations, so a brief explanation will be given below.

Also in the write operation, the row address RA
The operation in which one bit line pair is selected by column address CA (time t20 in FIG. 2) is the same as the read operation. After that, in the write operation, complementary data amplified by the write amplifier 8 (see FIG. 1) activated in response to the selection signal YSW is supplied to the wirings La and Lb forming the I/O line, and this complementary data is The signal is supplied to one bit line pair by the switch circuit 4. This write data is forcibly written into a predetermined memory cell MC, and the write operation is completed.

Next, referring to FIG. 3, a specific example of the switching circuit 5 and delay circuit 6 in the embodiment of FIG. 1 will be described. The switching circuit 5 includes a pad PD connected to the node N1, a resistor R1 having one end connected to the contact N1 and the other end connected to the fuse F1, a fuse F1 connected between the resistor R1 and the power supply terminal Vcc, and one end. is connected to contact N1 and the other end is connected to fuse F2, fuse F2 is connected between resistor R2 and the ground terminal, and inverter circuit INV
1.

On the other hand, the delay circuit 6 includes a delay element D1 that receives the sense amplifier activation signal SE, a delay element D2 that further delays the output signal of the delay element D1, and a switching circuit 5.
A NAND gate G1 receives as inputs the output signal DS of the delay element D2 and a signal passed through the inverter circuit INV2, and a NAND gate G2 receives as inputs the output of the delay element D1 and the output of the NAND gate G1. The inverter circuit INV3 receives the output of the gate G2 as an input.

Next, the operation of the switching circuit 5 and the delay circuit 6 will be explained. First, during a functional test of this semiconductor memory device in a wafer state, the pad PD is initially in an open state and the output of the inverter circuit INV1, that is, the control signal DS is set to a low level. Since the control signal DS is at low level, the sense amplifier activation signal SE is activated by the delay element D.
1, NAND gate G2, and inverter circuit INV, and becomes the selection signal YSW delayed by DT0 (see FIG. 2).

In this state, a function test is performed, and if the result is that the product is good, the fuse F2 of the switching circuit 5 is
is melted, thereby permanently setting the control signal DS to a low level. After the sense amplifier activation signal SE reaches the active level and time DT has elapsed, the selection signal YSW is activated.
In this way, a semiconductor memory device with a normal read speed in which the active level is obtained is obtained.

On the other hand, if a read error is detected as a result of the functional test, by setting the pad PD to the ground potential, the output of the inverter circuit INV1, that is, the control signal D
Let S be a high level. Since the control signal DS is at high level, the sense amplifier activation signal SE is activated by the delay element D1.
, delay element D2, inverter circuit INV2, NAND gate G1, NAND gate G2, inverter circuit INV
3, and the selection signal YSW is delayed by the time DT0+DT1 (see FIG. 2). If the function test is performed again in this state and the product is found to be of good quality,
Fuse F1 of switching circuit 5 is blown. This causes the control signal DS to remain at a high level permanently. Time DT0 after the sense amplifier activation signal SE reaches the active level
In this way, a semiconductor memory device is obtained which has a read speed slower by DT1 than the normal read speed in which the selection signal YSW is set to active level after +DT1 has elapsed.

If a test result indicating a read error is obtained even when the pad PD is set to the ground potential, the method of the present invention will not be effective. In that case, the prior art method of replacing the defective part with a redundant circuit has to be used.

Next, another example of the switching circuit 5 will be explained with reference to FIG. This switching circuit consists of a resistor R11 which has one end connected to contact N11 and the other end connected to fuse F11.
, a fuse F11 connected between the resistor R11 and the power supply terminal Vcc, and an N-channel MOS transistor 40 whose source/drain path is connected between the contact N11 and the ground terminal.
, an inverter circuit INV10 whose input terminal is the node 11 and whose output is connected to the gate of the transistor 24, a NOR gate G11 whose inputs are the output of the inverter circuit INV10 and the test signal TEST, and whose input is the output of the NOR gate G11. and an inverter circuit INV11.

In this switching circuit 5, first, the TEST signal is set to a low level to perform a function test with the control signal DS at a low level, and if a read error is found, the TEST signal is set to a high level to perform a control signal. The function test is performed again with the signal DS at high level. When the control signal DS is set to high level and no read error occurs, fuse F11 is blown and the control signal D is set to high level.
Set S permanently to high level. In this way, this switching circuit 5 does not require a pad for switching. In this case, an internal signal such as a row active WE (write enable) signal may be used as the TEST signal. Next, another example of the delay circuit 6 will be described with reference to FIG. This delay circuit includes a delay element D20 and a control signal DS.
transfer gates 51 and 52, each consisting of a P-channel transistor and an N-channel transistor, whose conduction is controlled by a signal T1 via an inverter circuit INV20, and a signal T2 via an inverter circuit INV21, which outputs the output of the inverter circuit INV21; and a delay element 53 formed by connecting four CMOS inverters in series.

Also in this embodiment, when the control signal DS is at low level, the sense amplifier activation signal SE is activated by the delay element D20.
and proceed along the path of transfer gate 51, at time D
The selection signal YSW is delayed by T0 (see FIG. 2). On the other hand, when the control signal DS is at a high level, the sense amplifier activation signal SE travels through the delay element D20, the delay element 53, and the transfer gate 52, and the time DT0+D
The selection signal YSW is delayed by T1 (see FIG. 2).

Next, another example of the switching circuit 15 and the delay circuit 16 will be described with reference to FIG. In these circuit examples, two switching circuits 15a and 15b having the same configuration as the switching circuit 5 shown in FIG. 3 are provided, and whether the control signals DS1 and DS2 are both low level or
Or one of them is configured to be at a high level.

Delay circuit 16 has three paths through which sense amplifier activation signal SE passes. That is, the control signal DS
1 and DS2 are both at low level, the sense amplifier activation signal SE is activated by delay element D1, NAND gate G3,
This becomes the path of the inverter circuit INV3. Control signal DS1
When is at a high level, the sense amplifier activation signal SE is
Delay elements D1, D2, inverter circuit INV2, NAN
D gate G1, NAND gate G3, inverter circuit I
Via the route of NV3. On the other hand, when the control signal DS2 is at high level, the sense amplifier activation signal SE is connected to the delay elements D1, D3, D4, inverter circuit INV4, NAND
Gate G2, NAND gate G3, inverter circuit IN
Via route V3.

As described above, by providing two types of control signals, DS1 and DS2, the sense amplifier activation signal SE
It is possible to give three stages of delay to the selection signal YSW, which is generated by selectively delaying . Delaying the selection signal YSW means that the access time will be delayed accordingly, so it is desirable that this delay time be small. In this example,
This amount of delay can be minimized.

In this embodiment, two types of control signals are used, but in the present invention, the same effect can be obtained even if three or more types of control signals are used. In this case, three or more switching circuits having the same configuration as switching circuit 5 shown in FIG. 3 may be provided, and the delay circuit may have four or more paths through which the sense amplifier activation signal SE passes.

[0041]

As described above, in the semiconductor memory device of the present invention, the switching circuit is set to generate an active level control signal when a read error is discovered through a functional test. If the read error is resolved by this, the switching circuit is set so that the control signal remains at the active level permanently, making it possible to make a product that would previously have been considered defective to a good product. It can contribute to improving yield.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a semiconductor memory device in an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the semiconductor memory device shown in FIG. 1;

FIG. 3 is a circuit diagram showing an example of a specific configuration of a switching circuit and a delay circuit shown in FIG. 1;

FIG. 4 is a circuit diagram showing another specific configuration of the switching circuit shown in FIG. 1;

FIG. 5 is a circuit diagram showing another specific configuration of the delay circuit shown in FIG. 1;

FIG. 6 is a circuit diagram showing still another specific configuration of the switching circuit and delay circuit shown in FIG. 1;

[Explanation of symbols]

1 Memory cell array 2 Row decoder 3 Column decoder 4 Selection switch 5 Switching circuit 6 Delay circuit 7 Data amplifier 8 Light amplifier YSW Selection signal SE Sense amplifier activation signal DS selection signal

Claims (7)

[Claims] 1. A memory cell array including a plurality of memory cells provided in an array and a plurality of bit lines and word lines respectively connected to the memory cells, and the memory cell array is arranged such that two bit lines form a pair; a sense amplifier that is provided for each bit line pair and amplifies the potential difference between the bit line pairs according to an activation signal; and a sense amplifier that uses the activation signal as an input signal and changes it according to a control signal from a switching circuit. It is characterized by comprising a delay circuit that applies a delay time to the activation signal to generate a selection signal, and selection switch means that connects a predetermined bit line pair and an I/O line in response to the selection signal. semiconductor memory device. 2. The switching circuit is characterized in that it includes a first output means that arbitrarily changes the level of the control signal, and a second output means that fixes the level of the control signal and outputs it. The semiconductor memory device according to claim 1. 3. The semiconductor memory device according to claim 2, wherein said second output means includes a fuse provided between a power supply terminal and an output terminal. 4. The semiconductor memory device according to claim 1, wherein the delay circuit includes a plurality of delay paths and selection means for selecting one of the delay paths depending on the level of the control signal. 5. The semiconductor memory device according to claim 4, wherein said selection means is constituted by a logic gate. 6. The semiconductor memory device according to claim 4, wherein said selection means is constituted by a plurality of transfer gates receiving said control signal at a control terminal. 7. The switching circuit generates a plurality of control signals, and the delay circuit changes the delay time according to the levels of the plurality of control signals.
The semiconductor memory device described above.