JPH0291900A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To easily adjust delaying time to optimize the delaying time by additionally providing a circuit which adjusts the delaying time of an internal circuit by changing the level of an external input terminal in a memory circuit. CONSTITUTION:A delaying time adjustment circuit 19 can change the timing of a row address input enable signal 11, row decoder enable signal 12, sense amplifier activating signal 13, and sense amplifier amplification completing signal 14 outputted from a row address strobe system controlling signal generation circuit 17 by controlling the circuit 17 by changing the level of an external input terminal 18. Therefore, adjustment of delaying time is simplified and the optimum delaying time can be give in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit equipped with a test circuit for checking internal operation timing.

[Conventional technology] Semiconductor memory circuits generally use address buffers.

It consists of circuit blocks such as decoders, sense amplifiers, and output buffers, but these circuit blocks must be operated sequentially at regular time intervals. That is, a row decoder is operated after the address buffer, a sense amplifier is operated after the row decoder, a column decoder is operated after the sense amplifier, and so on. This is because unless the output of the preceding circuit block is stabilized before activating the subsequent circuit block, operational problems such as hazards may occur.

In current semiconductor memory circuits, the operation of each circuit block is not a so-called synchronous operation, in which the operation of each circuit block is directly synchronized with one external word, and the operation time cannot be directly controlled by an external signal. In this sense, it is an asynchronous operation. In other words, since the activation signal of each circuit block is a signal that is generated internally in series in response to an external signal, the delay time setting between these internal control signals is
This is an important design issue. This is because these delay times have an optimal value because if they are too short, they will cause an error as described above, and if they are too long, they will lead to a decrease in access time.

An example of the operation of a semiconductor memory device will be described below to facilitate understanding of the present invention.

FIG. 5 is a block diagram of a multi-address manual dynamic random access memory circuit. In FIG. 5, one address word input manually to the address input terminal 1 is stored in the row address buffer 2 when the row address input enable signal 11 becomes enabled. Address buffer output 3 of row address buffer 2 is given to row decoder 4 and decoded when row decoder enable shield 12 is enabled. The decode output 5 is a word line of the memory cell array 6.

After one of the word lines 5 goes high and the data in the memory cell goes to the digit line D (8,9), the sense amplifier activation 1 word 13 is enabled and the sense amplifier 10 will amplify the data. The data amplification completion signal 14 of the sense amplifier is given to the CAS system control 1 word generation circuit, and the signals 48 to 48 generated thereby are
51 is applied to the I10 switch 46 and the I/○ buffer 15, and data reading and writing are performed. RA determines the timing of signals 11, 12, 13, and 14.
This is an S-system control signal generation circuit 17. 1 word 11. 12
．． 17 must be designed so that the timing of 13 and 14 is optimal, but it is generally difficult to create a design that accurately reflects the effects of parasitic elements, so it is difficult to make a design that accurately reflects the effects of parasitic elements. , a method is used to find the optimal value of timing.

Conventionally, this type of delay time adjustment has been carried out by fabricating a plurality of chips with different delay times by changing the layout pattern of the aluminum wiring process, and then obtaining the optimum delay time from the actual measurement results.

An example is shown in FIGS. 6(a) and (b) and FIGS. 7(a) and (b). FIG. 6(b) is a circuit diagram when the delay time is adjusted by two stages of inverters compared to FIG. 6(a), and FIG.
a) and (b) are layout diagrams corresponding to these. In the figure, 600 indicates an adjustment signal path composed of two inverters.

[Problems to be Solved by the Invention] As mentioned above, in the asynchronous operation of a semiconductor memory, a certain signal is delayed and used as an internal signal, and if the delay time is short, malfunctions may occur. It becomes the original.

Here, with reference to FIGS. 8 and 9, the hazard of a row decoder will be explained as an example. Assume that a new address (corresponding to address a) is applied to the address input terminal of the semiconductor memory shown in FIG. 5, and then the X ball becomes enabled.

Then, after a certain delay (time t1), the address manual enable signal is enabled and a new address is stored in the address buffer, and the address buffer output is given to the row decoder at time t2. On the other hand, the row decoder enable signal, which is a signal obtained by delaying the address manual enable signal, is enabled at time t3, decodes the address, and sets one word line to a high level.

At this time, if t3-tl is larger than t2-tl, the word line at address a becomes high level, but if t3-tl is smaller than t2-tl, the state of the external address terminal before the address at address a is given ( (corresponding to address a') is decoded and a hazard occurs on the word line at address a'. In particular, an irregular address a is selected as shown in Figure 9.
If a hazard occurs on the word line at row address a', the cell data at row address a' or the digit line will not be refreshed, and the word line at address a' will be at a low level. The cell data of a' will be destroyed. Furthermore, this also destroys the balance level of daisies) &l and D, so if the cell data at address a' and the cell data at address a are reversed, there is a possibility that the cell data at address a cannot be read correctly.

As described above, setting the delay time incorrectly is a fatal mistake in semiconductor memory circuits.

-In all-conductor memory circuits, access time is an important factor that determines product performance, so access time must be shortened as much as possible. Therefore, in a semiconductor memory, this type of delay time must be set so that the memory device does not malfunction and is as short as possible.

For the above reasons, adjusting the delay time in order to find the optimal delay time is an essential issue in the design of semiconductor memory devices. However, as mentioned above, in the past, in order to adjust the timing of the delay signal, it was necessary to wait for a prototype product with a different aluminum wiring process to be completed, so it was difficult to determine the optimal delay time. It took a very long time.

[Differences between the invention and the prior art] Compared to the delay time adjustment circuit and method in the conventional control signal generation circuit described above, the present invention allows the delay time to be easily changed by simply changing the level of the external input terminal (test bin). The difference is that it is possible to

[Means for Solving the Problems] A semiconductor memory circuit of the present invention includes a plurality of circuit blocks that are sequentially activated by each of a plurality of control signals obtained by delaying a first external signal. , the delay time between the delay signals between the plurality of control signals is controlled by the second external signal.

Embodiment FIG. 1 is a block diagram of a dynamic semiconductor random access memory according to a first embodiment of the present invention. The same numbers are used for the same configurations as in the conventional example. Since the operation is the same as that of the conventional example, a description thereof will be omitted here. RAS system control signal 11 generated from RAS system control signal generation circuit 17.
12. 13. The circuit that adjusts the timing of 14 is
This is a delay time adjustment circuit 19. The delay time adjustment circuit 19 adjusts the RAS by changing the level of the external input terminal 18.
Acts on the system control signal generation circuit 17 and generates signals 11, 12.1
3.14 timing can be changed.

FIG. 2 is an example of the delay time adjustment circuit shown in FIG. 1. Path a is a normally used signal path (a part of the RAS delay circuit), path S, c, and d are signal paths used when adjusting the delay time.

One of the words created by decoding two signals is input as the opening/closing word of transfer gates TGI to TG4, so that one of the transfer gates is always turned on. There is. In this example 2
By changing the combination of levels of the two external input terminals, the memory device can be tested with three types of delay timing.

FIG. 3 is a block diagram of a semiconductor memory (static RAM) according to a second embodiment of the present invention.

The following will explain the read operation as an example. In some types of static RAM, when a row address changes, a signal (8TD) 20 is generated to notify that the address has changed, and a plurality of delay numbers from that signal are used as enable signals for other circuits.

This will be explained below with reference to FIG. When ATD occurs, the digit line D precharge signal 21 is disabled, and when the row decoder 28 has finished decoding the address, the one-shot signal 22 for setting the selected word line to high level is generated. occurs. When cell data arrives on the data bus 3S, the sense amplifier activation signal 23 is enabled to activate the sense amplifier 37. The data is read here, but after that the sense amplifier 3
Since the signal 7 is inactivated, a signal 24 for latching the data is generated before that, and the read data is latched. Thereafter, a select signal 25 is generated to take out the data output not from the sense amplifier but from the latch circuit to switch the output. Signals 21, 22, 23, 24
．． 25 is determined by the ATD system control signal generation circuit. AT of signals 21, 22, 23, 24.25
In order to find a timing at which the delay time for D is minimized and the memory device does not malfunction, the delay time adjustment circuit 30 is used to adjust the delay time of the ATD system control signal generation circuit. In FIG. 3, simply changing the level of the external input terminal 40 acts on the delay time adjustment circuit 30 or the ATD delay circuit 35, and the signals 21.22, 23, 24.25
The delay time of any signal can be easily changed.

is a block diagram of the conventional example, Figures 6(a) and (b) are circuit diagrams showing the conventional delay time adjustment method, and Figures 7(a) and (b) are layouts of Figures 6(a) and (b). The layout diagrams, FIGS. 8 and 9, respectively, are timing charts for explaining the operation of the conventional example.

[Effects of the Invention] As explained above, the present invention adds a circuit to the memory circuit that adjusts the delay time of the internal circuit by changing the level of the external input terminal, making it easy to adjust the delay time and achieve optimal results. This has the advantage that it does not take much time to find a suitable delay time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the invention, FIG. 2 is a circuit diagram showing a delay time adjustment circuit included in the first embodiment, and FIG. 3 is a block diagram of a second embodiment of the invention. , FIG. 4 is a timing chart showing the operation of the semiconductor memory device shown in FIG. 3, and FIG. 5 is a timing chart showing the operation of the semiconductor memory device shown in FIG. 3. ...Address input terminal, ...Address buffer, ...Address buffer output, ...Row decoder, ...Row decoder output = word Lines, ・Dynamic memory cell array, ・Column address buffer, ・Digit line D, ・Digit line r, ・Sense amplifier, 13.14. ...RAS system delay signal, ...I10 control circuit, ...peripheral circuit, ...RAS system delay circuit, ...external input terminal, ...delay time adjustment circuit , address change detection signal (ATD), 21, 22. 23゜24.25...ATD delay signal, 26, 27, 28, 29, 30, 31, 32, 33, 34, ;35, 36, address buffer, address buffer output,... Row decoder, ・Row decoder output, ・Column decoder, ・Column decoder output, ・Static memory cell array, ・Address input terminal, ・Address change detection circuit, ・ATD delay circuit, ・Data bus, 37... ...Sense amplifier, 38...Input/output data control circuit, 39
... Delay time adjustment circuit, 40 ... External input terminal, 41 ... Aluminum wiring, 42 ... Polycide, 43 ... P diffusion layer, 44...N diffusion layer, 45...contact, 46...■/○ switch, 47. . . . . . . ■/○ bus, 48.49
．． ! 50.51...Control signal, TGI to TG4
...Transfer gate, A, B, C, D...
...Signal, DECI φ...Decoder. Patent applicant: NEC Corporation

Claims (1)

[Claims] A plurality of circuit blocks are sequentially activated by each of a plurality of control signals obtained by delaying a first external signal.
A semiconductor memory circuit characterized in that it is controlled by an external signal.