JP2849550B2 - Column decode enable signal generation circuit for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device DRAM.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a column decode enable signal generating circuit of a (Dynamic Random Access Memory) element, and more particularly to a column decode enable signal generating circuit of a semiconductor device capable of transferring data on a bit line to a data bus line at an optimum time. .

[0002]

2. Description of the Related Art Generally, in order to read data stored in a cell array of a DRAM device, first, one word line is enabled in a cell array block selected by an input row address. The data stored in the cell enabled by the word line is sensed and amplified by a bit line sense amplifier or the like. In addition, only one of the bit line data sensed and amplified by the column address is transmitted to the next data bus line. The data transmitted to the bit line in the above process is sufficiently sensed by the bit line sense amplifier.
The column decode enable signal should be enabled at the optimal time to be passed on the data bus line after being amplified.

In order to secure a period during which data on the bit line can be sensed and amplified by the sense amplifier, the conventional column decode enable method is modeled on a resistive element, a capacitive element, an inverter chain, and the like. The column decode enable time was determined using a circuit. In this case, the delay time of the modeled circuit is changed due to a change in the manufacturing process, the power supply voltage, the temperature, and the like. There is a problem that it is difficult to enable the enable signal. For reference, a process of reading data stored in a cell array block by a conventional column decode enable signal generating circuit will be described with reference to FIGS. 1 and 2A to 2F.

FIG. 1 is a circuit diagram of a memory device for explaining a process in which data stored in a cell array block is read by a conventional column decode enable signal generating circuit, and FIGS. 2A to 2F are shown in FIG. FIG. 6 is a timing chart for each part of the circuit shown.

[0005] A spare row enable bar signal generating circuit 12 shown in FIG. 1 has a row address strobe bar (row adder bar) as shown in FIG. 2A.
ssStrobe Bar; / RSA) is input through the row address strobe buffer 11, and a row address decoding signal is input via a decoding signal input terminal (not shown). Further, the spare row enable bar signal generating circuit 12 logically combines the row address decoding and the row address strobe bar signal to generate a spare row enable bar signal (/ SRE) of low logic as shown in FIG. 2B. Occur.

The scan row enable signal (/ SR)
E) is delayed for a certain time by an enable bar signal sensing / generating circuit (Sensing Generating Enableable Bar) 13 including a word line simulator 14 in order to secure a timing margin. The enable bar signal sensing generation circuit 13
Generates a low logic sensing / generating enable bar signal (/ SG) as shown in FIG. 2C, in which the spare row enable (/ SRE) is delayed for a predetermined period. The sensing generating enable bar signal (/
If SG) transitions to low logic, the bit line sense amplifier array 18 is precharged with Vcc / 2 (Vcc: power supply voltage) and the sensing enable signal (Sensing Enable Signal: / S) as shown in FIG. 2D is restored. Enable signal (Restore Enable Signal; RTO)
Supplies the ground potential (GND) and the voltage of Vcc to the bit line sense amplifier array 18 to drive the bit line sense amplifier array 18. The bit line sense amplifier array 18 includes true / false and complement bit lines (B
L, / BL) and the like, and senses / amplifies the true / false and complement data. Further, after a lapse of sufficient time for the true / false and complement data on the true / false / complement bit lines (BL, / BL) to be sensed / amplified, the sensing / complementing is performed.
The amplified true / false and complement bit lines (BL, //
BL) on the true / false and complement data lines (D
B, / DB) MOS transistor M for transferring to
11, M12 is turned on.

Here, the MOS transistors (M11, M11,
In order to optimize the turn-on time of M12), a chip selector bar signal (/ CS) generating circuit 15 including an inverter and a capacitor and an inverter chain are used. The chip selector bar signal generation circuit 15 delays the output signal (/ SG) of the spare row enable bar signal generation circuit 13 for a predetermined time, and generates a chip selector bar (/ CS) signal as shown in FIG. 2E. The inverter chain inverts and delays the chip selector enable signal (/ CS) from the generation circuit 15 and generates a high logic global column enable signal (global column enable signal) as shown in FIG. 2F.
YGo), and further applies the global column enable signal (YGo) to the column decode array 19. In this case, the column decode array 19 outputs the high logic global column enable signal (YG
During the period when o) is applied, the column address decoding signal (AYi) is transferred to the gates of the MOS transistors M11 and M12.

[0008]

However, the semiconductor device including the conventional column decode enable signal generating circuit as described above has the following problems. First, in order to adjust the sensing time (Sensing Time) for transmitting the data of the bit line to the data bus line, the sensing generating enable bar signal (/ SG) is used.
Since the delay time is estimated by simulation of the chip cell bar signal (/ CS) and the chip cell bar signal (/ CS), the semiconductor device has a problem that the data access time increases.

Second, the semiconductor device uses an inverter and a capacitive element to delay the sensing / generating enable bar signal (/ SG) and the chip selector enable bar signal (/ CS) for a certain period of time. In addition, there is a problem that the delay time continuously changes according to the voltage and the temperature.

Third, the semiconductor device has a problem that the circuit must be corrected using a mask when an appropriate delay time is to be obtained by expressing a signal delay using the inverter and the capacitor. Have.

Accordingly, an object of the present invention is to provide a column decoding enable signal generating circuit for a semiconductor device capable of transferring data on a bit line to a data bus at an optimum time even when a manufacturing process, a power supply voltage and a temperature change. Is to provide.

[0012]

In order to achieve the above object, an object of the present invention is to provide a true / false and complement dummy bit line including a dummy cell arranged at one end of a normal cell array; A column decode enable signal (d) is connected to the false and complement dummy bit lines and uses data from the true and false and complement dummy bit lines.
V), and a column decode enable signal (YGo; amplifying the column decode enable signal from the first sense amplifier and amplifying the column decode enable signal from the first sense amplifier).
.Phi.YGi) in a high-speed page mode, and a dummy bit line sense amplifier comprising a second sense amplifier for maintaining the enable state continuously. To provide a circuit. It is another object of the present invention that a dummy cell connected to the true / false dummy bit line has a high logical value and a dummy cell connected to the complement dummy bit line has a low logical value. It is another object of the present invention to provide a column decode enable signal generating circuit for a semiconductor device. Still another object of the present invention is to provide a semiconductor device according to the present invention, further comprising a separate cell plate for charge coupling the dummy cell to record data in the dummy cell connected to the dummy bit line. A column decode enable signal generating circuit is provided. It is still another object of the present invention to provide a second normal cell array block having the true / false and complement dummy bit lines, and the true / false and complement dummy bit lines of the second normal cell array block. And a second dummy bit line sense amplifier for generating a column decode enable signal (.PHI.YGj) using the data from the first and second dummy bit line sense amplifiers (.PHI.YGi, .PHI.YGj) and performing a logical operation on the global decode enable signal (.PHI.YGj). 2. A logical operation means for generating (.PHI.YG).
It is another object of the present invention to provide a column decode enable signal generating circuit of the semiconductor device described above.

[0013]

According to the above construction, the column decode enable signal generating circuit of the present invention adds a dummy cell to the normal array, generates a column decode enable signal based on data output from the dummy cell, and changes the power supply voltage and temperature in the manufacturing process. Regardless, the data on the bit line can be transferred to the data bus at the optimal time.

[0014]

FIG. 3 is a circuit diagram of a semiconductor device for explaining an operation in which data read by a cell array block by a column decode enable signal generating circuit according to one embodiment of the present invention is transferred to a data bus side. is there. 4A to 4G are timing diagrams of each part of the circuit shown in FIG. FIG. 3 will be described in detail with reference to FIGS. 4A to 4G.

First, when a row address strobe signal (/ RAS) as shown in FIG. 4A is enabled to low logic, a spare row enable bar signal (/ SRE) is generated.
Will have a low logic as shown in FIG. 4B. As the spare row enable bar signal (/ SRE) has a low logic state, a sensing block selection signal (Sensing Block Selection: SB) is provided.
S) is enabled to high logic, and the sensing / generating enable bar signal (/ SG) is also enabled to low logic as shown in FIG. 4D. Also, a sensing block selection bar signal (Sensing Block Selection Bar Singn) having a logical value opposite to the sensing block selection signal (SBS).
al; / SBS) is enabled to low logic.

If the sensing block selection signal (SBS) and the sensing block selection bar signal (/ SBS) are enabled, the true / false Separate Cell Plate (SCP) is shifted to a high logic state. On the other hand, a complement separate cell plate (SCP) transitions to a low logic state.
At this time, a dummy cell connected between the true / false dummy bit line (DBL) and the true / false separate cell plate (SCP) is precharged to have a high logic voltage, and a complement dummy bit line (SCP) is provided. / DB
L) and the complement's separate cell plate (SCP)
Are precharged to have a low logic voltage. Further, when the word line (WD) connected to the cell array block 31 including the dummy cells together with the row decoder 32 is enabled to a high logic, the true / false and complement dummy bit lines (D / D) are enabled.
BL) generates a voltage of only dV determined as follows.

(Equation 1)

Here, Ccell is a capacitance value of a capacitor included in the dummy cell, Vcc / 2 is a voltage precharged to the true / false dummy bit line (DBL), and CDBL is a dummy bit line. (DBL)
Is the capacitance value. The voltage level of dV is the voltage level sensed and amplified by the first sense amplifier 34, and
Has substantially the same value as the voltage sensed / amplified by the normal bit line sense amplifier included in. At this time, as shown in FIG. 4E, a sensing enable bar signal (/ S) of a low logic and a restore enable signal (RTO) of a high logic are supplied to the sense amplifier array 33 including the first sense amplifier 34. Is done. Further, the voltage of dV is amplified by the second sense amplifier 35 to the level of the power supply voltage (Vcc). The second sense amplifier 35 operates while the true / false block selection signal (SBS) maintains high logic.

The amplified dV voltage has a waveform as shown in FIG. 4G, and further passes as a column decoding enable signal (YGo) through an inverter chain 37 composed of two inverters. Supplied to In this case, the column decode array 36 converts the column address decoding signal (AYi) into M by the high logic column decoding enable signal (YGo) from the inverter chain 37.
The data is transferred to the gates of the OS transistors M11 and M12. In this case, when the column address decoding signal (AYi) is applied from the column decode array 36, the MOS transistors M11 and M12 are turned on by the true / false normal bit line (BL) and the complement normal bit line. The data on (/ BL) is transferred to the true / false and complement data lines (DB, / DB).

The dummy cell is arranged at one end of the normal cell array so as to input the word line boot strebing voltage even later than the normal cell which inputs the word line boot strebing voltage latest. This allows the sense amplifier connected to the dummy bit line to sense and amplify data later than the sense amplifier connected to the normal bit line, and the data on the normal bit line is transferred to the data bus at the optimal time. That will be guaranteed. The column decoding enable signal (YGo) indicates whether the true / false and complement data on the true / false and complement normal bit lines (BL, / BL) output from the slowest operating normal cell among the normal cells are normal. Is enabled at a point slightly later than the point at which it is sensed and amplified by the sense amplifier. This is ensured by the sensing / amplifying operation by the second sense amplifier 35.

The second sense amplifier 35 includes a latch circuit. The latch circuit operates in a fast page mode (Fast P mode).
age Mode), the row address is selected, and the column decode enable signal (YGo) is maintained at a high logic state while the column address is toggled (Toggle). Further, the true / false dummy bit line (DBL) and the complement dummy bit line (/ DBL)
The true / false separate cell plate (SPC) is used to precharge data to the dummy cell connected to the dummy cell.
The complementary cell plate (/ SPC) has a function of charge-coupling the dummy cell.

As described above, the semiconductor device shown in FIG. 3 generates the column decode enable signal by sensing and amplifying the data output from the dummy cell by the first and second sense amplifiers. In addition, the data on the normal bit line can be transferred to the data bus at the optimum time regardless of the change in temperature.
Due to the above advantages, the semiconductor device can minimize data access time.

FIG. 5 is a block diagram of a semiconductor device of another embodiment including a column decode enable signal generating circuit according to an embodiment of the present invention. In the semiconductor device shown in FIG. 5, when a column decode enable signal (YGo) is not generated due to a defect of a dummy cell included in the semiconductor device of FIG. 3, a cell array block including a defective dummy cell is treated as defective. To prevent that. For this reason, the semiconductor device has a global column enable signal (.PHI.YGi, .PHI.YGj) generated in each cell array block.
Is ORed by OR gate 58 (OR Gate),
The OR-operated signal is applied to the column decode array 57 as a column decode enable signal (ΦYG). Due to the decode enable signal (ΦYG) generated by the OR operation, the semiconductor device normally performs the reading operation even if some defects occur in the cells included in the cell array blocks 51 and 53.

In FIG. 5, a pair of dummy bit lines
The first and second sense amplifiers 54 and 55 include a pair of bit lines (DBL and / DBL) shown in FIG.
It has the same configuration as the sense amplifiers 34 and 35. However, the second sense amplifier 55 applies the global column decode enable signals (.PHI.YGi, .PHI.YGj), which are output signals, to the OR gate 58 without directly applying them to the column decode enable. The OR gate 58 applies an OR operation of the global column decode enable signals (ΦYGi, ΦYGj) to the column decode array 57 as a column decode enable signal (ΦYG). As a result, the semiconductor device can perform a normal reading operation even if some dummy cells do not operate due to a manufacturing process or a soft error.

[0024]

As described above, the column decode enable signal generating circuit of the present invention adds a dummy cell to a normal cell array, generates a column decode enable signal based on data output from the dummy cell, and manufactures the power supply voltage and temperature. Data on the bit line can be transferred to the data bus side at the optimum time regardless of the change of the data line.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor device including a conventional column decode enable signal generation circuit.

FIG. 2 (A), (B), (C), (D),
(E), (F) is a timing chart for each part of the circuit shown in FIG.

FIG. 3 is a circuit diagram of a semiconductor device including a column decode enable signal generation circuit according to one embodiment of the present invention.

FIG. 4 (A), (B), (C), (D),
(E), (F), (G) are timing diagrams for each part of the circuit shown in FIG.

FIG. 5 is a circuit diagram of a semiconductor device including a column decode enable signal generation circuit according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 11 row address strobe buffer 12 spare row enable bar signal generation circuit 13 enable bar signal detection generation circuit 14 word line simulator 15 chip selector bar signal generation circuit 16, 31 cell array 17, 32 row decoder 18, 33, 52 bit line sense amplifier Array 34,54 First sense amplifier 19,36,57 Column decode array 35,55 Second sense amplifier 37 Inverter chain 51 First cell array block 53 Second cell array block 56 Dummy bit line pair 58 OR gate 59 Inverter

Claims (4)

(57) [Claims] 1. A true / false / complement dummy bit line including dummy cells disposed at one end of a normal cell array and connected to the true / false / complement dummy bit lines. A first sense amplifier for generating a column decode enable signal (dV) using data from the first sense amplifier, and a column decode enable signal (YGo; ΦYGi) which amplifies and amplifies the column decode enable signal from the first sense amplifier. A dummy bit line sense amplifier comprising a second sense amplifier for latching and maintaining the enable state in the high-speed page mode and continuously maintaining the enable state. 2. The dummy cell connected to the true / false dummy bit line has a high logical value, and the dummy cell connected to the complement dummy bit line has a low logical value. 20. A column decode enable signal generation circuit of the semiconductor device according to the above. 3. The column decoder according to claim 1, further comprising: a separate cell plate for charge-coupling the dummy cell for recording data to the dummy cell connected to the dummy bit line. Enable signal generation circuit. 4. A second normal cell array block having the true / false and complement dummy bit lines, and a column using data from the true / false and complement dummy bit lines of the second normal cell array block. a second dummy bit line sense amplifier for generating a decode enable signal (ΦYGj), the outputs of both the dummy bit line sense amplifier (FaiYGi
, ΦYGj), and a logic operation means for generating a global decode enable signal (ΦYG) by logically operating the column decode enable signal generation circuit of the semiconductor device according to claim 1.