JP3814033B2 - Column selection signal control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a column selection signal control circuit related to column selection for addressing.
[0002]
[Prior art]
A semiconductor memory device includes a memory cell array as an aggregate of memory cells that store a large number of data, and a peripheral circuit for controlling storage data input / output of the memory cell array. Each memory cell of the memory cell array is arranged in a matrix form between a number of rows and a number of column pairs. A predetermined address is set for each row and column pair. The row address is used to specify one of the rows, and the column address is used to specify one of the column pairs. Currently, the row address and the column address are generally provided by an address multiplexing method.
[0003]
FIG. 1 is a circuit diagram showing a core configuration of a semiconductor memory device having a dynamic cell. The access process of the illustrated memory will be briefly described. First, a pair of bit lines forming a column pair is precharged to a predetermined equal voltage level by precharging prior to operation. The precharge of the bit line pair is performed by the precharge and equalization circuit 12, and the precharge level of the bit line pair is generally VCC / 2 (VCC is an operating power supply voltage in the chip).
[0004]
Next, when the read operation is activated, the precharge and equalization circuit 12 is stopped, and a row address signal is output from the row address buffer and decoded by the row decoder, and a word forming a row corresponding to the row address. Line WLi is activated. When the selected word line WLi is activated, charge sharing (charge distribution) occurs between the memory cell connected to the selected word line WLi and the corresponding bit line BLi, thereby causing the bit line pair BLi and bar BLi to be paired. A voltage difference of several tens to several hundreds mV is generated according to the stored charge of the memory cell. The difference between the bit line pair BLi and bar BLi is sensed by the sense amplifier 14 and further developed to the VCC level and the VSS (ground) level.
[0005]
Subsequently, a column address signal output from the column address buffer is decoded by a column decoder, and a column selection signal CSL thereby connects the bit line pair BLi, bar BLi to the input / output line pair IO, bar IO. By being provided to 16 and 18, column selection is performed. That is, when the column selection gates 16 and 18 are turned on in response to the column selection signal CSL, the data read to the bit line pair BL and bar BL is transmitted to the input / output line pair IO and bar IO. The data placed on the input / output line pair IO and bar IO is sensed and amplified again by the output sense amplifier provided on the input / output line pair IO and bar IO, and then output to the outside of the chip via the output system circuit. This completes the read operation for outputting 1-bit data.
[0006]
In the case of the write operation, data is stored in the designated memory cell by performing the reverse process of the read operation. In general, the output sense amplifier is not operated in the write operation.
[0007]
FIG. 2 shows a circuit diagram of a column selection signal control circuit provided for controlling the application timing of the column selection signal CSL in the above process. That is, it is the role of the column selection control signal φCP output from the column selection signal control circuit that determines the activation timing of the column selection signal CSL provided to the gate electrodes of the column selection gates 16 and 18 shown in FIG. is there.
[0008]
Enable signal φCPE is input to inverter 22, and the output of inverter 22 is input to inverter 24. The output of the inverter 24 is input to the pulse generation circuit 26, and the output of the pulse generation circuit 26 is input to the inverter 38. The output of the inverter 38 is input to the inverter 40, and the column selection control signal φCP is output from the inverter 40. For the pulse generation circuit 26, a short pulse generator using a delay path by an inverter and a NAND gate is used. FIG. 3 shows the operation timing of this circuit.
[0009]
As shown in the figure, when the clock-like enable signal φCPE having a predetermined period is activated by the combination of the external clock signal CLK and the column predecoding information, the pulse-like signal whose pulse width is determined by the delay path of the enable signal φCPE is obtained. A column selection control signal φCP is output and input to the column predecoder. Thereby, the decoding time of the column address signal of a predetermined bit is controlled, and a predecoded column address signal having a predetermined width is output from the column predecoder accordingly. At this time, the predetermined bits for which the decoding time is determined are usually 2-3 most significant bits (MSB). The column address signal predecoded in this way is the column selection that designates the column selection gates 16 and 18 after the remaining column address signal except the most significant bit is finally decoded by the column decoder. Output as signal CSL. Such a circuit configuration of the column predecoder and the column decoder is a well-known technique. Through such control, the column selection signal CSL is activated for the same time in the read and write operations.
[0010]
[Problems to be solved by the invention]
In the above prior art, the enable time of the column selection signal in the read / write operation is determined in consideration of the precharge of the input / output line pair and the enable time of the output sense amplifier. That is, the output sense amplifier is activated within the enable time of the column selection signal, and the input / output line pair is precharged outside the enable time of the column selection signal, so that the enable time of the column selection signal is sufficient for these. It is determined. However, in recent semiconductor memory devices that operate with a high-frequency system clock, the access cycle time is shortened. In particular, the enable time of the column selection signal in the write operation tends to be insufficient, and the high-frequency access is restricted. It is a factor. That is, the enable time of the column selection signal necessary for writing in further high-frequency operation is insufficient, causing a situation in which valid data of the input / output line pair is not sufficiently transmitted to the bit line, and the frequency of occurrence of write errors is increased. Get higher.
[0011]
Focusing on these problems, the object of the present invention is to provide a column selection signal control circuit suitable for high-frequency operation without increasing the access time while ensuring the column selection signal enable time sufficient for writing. It is to provide.
[0012]
[Means for Solving the Problems]
In the write operation, since the write drive circuit is used without operating the output sense amplifier of the input / output line pair as described above, the precharge of the input / output line pair is not so important. Accordingly, in the write operation, if the precharge time can be shortened and the column select signal enable time can be controlled to be long, a high frequency clock can be used.
[0013]
To this end, according to the present invention, a column selection control of a semiconductor memory device that generates a pulsed column selection control signal based on an enable signal provided in the form of a clock having a predetermined period and determines an enable time of the column selection signal. In the circuit, the pulse width of the column selection control signal is changed between reading and writing by changing the delay path of the enable signal according to the logic of the writing control signal.
[0014]
Such a column selection control circuit includes a first delay circuit that delays an enable signal, a first delay selection circuit that forms a detour of the first delay circuit according to a write control signal, and an output of the first delay circuit And a first combination circuit that logically combines the outputs of the first delay selection circuit, a second delay circuit that delays the output of the first combination circuit, and a bypass circuit of the second delay circuit according to the write control signal A second combinational circuit for logically combining the output of the second delay circuit and the output of the second delay selection circuit, the output of the first combination circuit and the output of the second combination circuit And an output combination circuit that generates a column selection control signal by logical combination. The first delay selection circuit is a first logic circuit that performs a logical operation on the enable signal and the write control signal and outputs a signal according to the enable signal when the write control signal is inactive. The output of the first combination circuit and the write control signal may be logically operated to output a signal according to the output of the first combination circuit when the write control signal is activated.
[0015]
In this case, the pulse width of the column selection control signal that determines the enable time of the column selection signal is set longer during writing.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a semiconductor memory device according to the present invention will be described below with reference to the accompanying drawings.
[0017]
FIG. 4 shows an implementation circuit diagram of the column selection signal control circuit. In this circuit, the enable signal φCPE is input to the inverter 42 of the first delay circuit and the AND gate 46 of the first logic circuit, and the write control signal φWR is inverted and input to the AND gate 46. That is, the enable signal φCPE is delayed by the first delay circuit including a large number of inverters 42 and 44 connected in series. On the other hand, the first logic circuit composed of the AND gate 46 has a shorter delay time and a higher response speed than the first delay circuit. When the write control signal φWR is logic “low”, the enable signal φCPE is output. This is a delay selection circuit that performs a logical operation and generates an output corresponding to the logical operation. In some cases, the first delay selection circuit may be formed of a MOS transistor according to the write control signal φWR. The output of the inverter 44 of the first delay circuit and the output of the AND gate 46 of the first logic circuit are logically operated in the NOR gate 50 of the first combination circuit and output from the inverter 52, and the NAND gate 66 of the output combination circuit Input to the inverter 54 of the second delay circuit and the AND gate 58 of the second logic circuit.
[0018]
The output of the inverter 52 is delayed by a number of inverters 54 and 56 connected in series in the second delay circuit. The output of the inverter 52 is input to the AND gate 58 of the second logic circuit and logically operated with the write control signal φWR. The second logic circuit composed of the AND gate 58 has a shorter delay time and a faster response speed than the second delay circuit, and outputs the output of the inverter 52 when the write control signal φWR is logic “high”. This is a delay selection circuit that performs a logical operation and generates an output corresponding to the logical operation. In some cases, this second delay selection circuit may be formed of a MOS transistor in accordance with write control signal φWR. The output of the inverter 56 of the second delay circuit and the output of the AND gate 58 of the second logic circuit are logically operated by the NOR gate 62 of the second combination circuit and output from the two inverters 64 and 65. Input to the NAND gate 66. As a result of the logical operation of the output of the inverter 52 and the output of the inverter 65 in the NAND gate 66 constituting the output combination circuit, the column selection control signal φCP is output via the inverters 68 and 70.
[0019]
FIG. 5 shows the operation timing of the circuit of FIG. When enable signal φCPE is activated by a combination of external clock signal CLK (not shown) and column predecoding information, column selection control signal φCP is generated as a pulse signal having a pulse width corresponding to the state of write control signal φWR. Is output. That is, since the write control signal φWR is provided with a logic “low” at the time of reading and a logic “high” at the time of writing, the column selection control signal φCP having different pulse widths for reading and writing is combined by combining these logics. Can be generated. As a result, even when the access cycle time is shortened, the enable time of the column selection signal CSL at the time of writing can be secured. This will be described below.
[0020]
First, in the read operation (READ), the write control signal φWR maintains the logic “low”. Therefore, as a result of the AND gate 46 of the first logic circuit performing the operation of the enable signal φCPE and outputting it, a detour of the first delay circuit is formed. On the other hand, since the AND gate 58 of the second logic circuit is inhibited, the output of the inverter 52 of the first combination circuit is output through the second delay circuit. As a result, the column selection control signal φCP immediately transitions to the logic “low” in response to the logic “high” transition of the enable signal φCPE, and then the “low” pulse corresponding to the delay time D1 by the second delay circuit and the second combination circuit. After maintaining the width, it returns to the logic “high”. That is, in this case, the first delay circuit is not involved in the logic “low” transition of the column selection control signal φCP, while the second delay circuit is involved in the logic “high” transition of the column selection control signal φCP. The column selection control signal φCP is generated with a cycle that substantially matches the cycle of the enable signal φCPE.
[0021]
As can be seen from the column predecoder and decoder circuit shown in FIGS. 6 and 7, the output operation of the column predecoder is allowed during the logic “high” time of the column selection control signal φCP. The selection signal CSL is output with a logic “high”.
[0022]
In the case of the write operation (WRITE), the write control signal φWR maintains the logic “high”. Therefore, the AND gate 46 of the first logic circuit is inhibited, and the enable signal φCPE is delayed through the first delay circuit and output. On the other hand, the AND gate 58 of the second logic circuit calculates the output of the inverter 52 of the first combination circuit, so that a bypass circuit of the second delay circuit is formed. As a result, the column selection control signal φCP is delayed by the delay time D2 by the first delay circuit from the logic “high” transition of the enable signal φCPE, and then delayed by the second logic circuit and the second combination circuit. After maintaining the "low" pulse width for D3, the logic returns to "high". That is, in this case, the first delay circuit is involved in the logic “low” transition of the column selection control signal φCP, while the second delay circuit is not involved in the logic “high” transition of the column selection control signal φCP. Thus, as shown in FIG. 5, the column selection control signal φCP has a long logic “high” time and a short logic “low” time.
[0023]
As described above, according to the column selection signal control circuit of this example, the enable time of the column selection signal CSL can be changed by reading and writing. That is, as shown in FIG. 5, the column selection signal CSL has a shorter “low” period B during writing than a “low” period A during reading, that is, a longer logical “high” period during writing operation. It is variably controlled to take. Accordingly, even when the access cycle time is shortened, it is possible to sufficiently ensure the enable time of the column selection signal CSL during the write operation, the error frequency during the write can be greatly reduced, and the high frequency reliability is higher. A semiconductor memory device can be realized. The “low” period B may be left to some extent without being completely eliminated because there is a possibility of multi-bit column selection by a column selection signal according to address transition.
[Brief description of the drawings]
FIG. 1 is a schematic circuit diagram showing a core configuration of a semiconductor memory.
FIG. 2 is a circuit diagram showing a conventional column selection signal control circuit.
FIG. 3 is a signal waveform diagram showing operation timing of the circuit of FIG. 2;
FIG. 4 is a circuit diagram showing a column selection signal control circuit according to the present invention.
FIG. 5 is a signal waveform diagram showing operation timing of the circuit of FIG. 4;
FIG. 6 is a circuit diagram of a column predecoder.
FIG. 7 is a circuit diagram of a column decoder.
[Explanation of symbols]
42, 44 First delay circuit 46 First logic circuit (first delay selection circuit)
50, 52 First combination circuit 54, 56 Second delay circuit 58 Second logic circuit (second delay selection circuit)
62, 64, 65 Second combination circuit 66, 68, 70 Output combination circuit φCPE Enable signal φWR Write control signal φCP Column selection control signal

Claims (3)

A pulsed column selection control signal for controlling the output operation of the column predecoder is generated based on an enable signal provided in the form of a clock having a predetermined cycle, and the enable time of the column selection signal is determined by the pulse width of the column selection control signal. In the column selection control circuit of the semiconductor memory device to be determined,
By changing the delay path of the enable signal according to the logic of the write control signal, the pulse width of the column selection control signal for determining the enable time of the column selection signal is changed at the time of reading and writing, and the above-mentioned at the time of writing. A column selection signal control circuit comprising means for making the pulse width of the column selection control signal longer than that during reading . A first delay circuit for delaying the enable signal;
A first delay selection circuit that forms a bypass of the first delay circuit according to a write control signal;
A first combination circuit that logically combines the output of the first delay circuit and the output of the first delay selection circuit;
A second delay circuit for delaying the output of the first combination circuit;
A second delay selection circuit that forms a bypass of the second delay circuit according to the write control signal;
A second combination circuit that logically combines the output of the second delay circuit and the output of the second delay selection circuit;
2. The column selection signal control circuit according to claim 1, further comprising: an output combination circuit that generates a column selection control signal by logically combining the output of the first combination circuit and the output of the second combination circuit. The first delay selection circuit is a first logic circuit that performs a logical operation on the enable signal and the write control signal and outputs a signal according to the enable signal when the write control signal is inactive.
A second delay selection circuit that performs a logical operation on the output of the first combination circuit and the write control signal and outputs a signal according to the output of the first combination circuit when the write control signal is activated; The column selection signal control circuit according to claim 2, wherein

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