JP2000182374A - Dynamic semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption at the time of standby by reducing a pattern area of a bit line pre-charge equalizing circuit of a DRAM and reducing a leak current made to flow toward a word line of a short-circuited defective part between a word line and a bit line from a pre-charge power source line. SOLUTION: This memory is provided with plural cell array selecting switches 14 selecting plural memory cell arrays, a bit line sense amplifier 16 provided corresponding to pairs of bit line (BLL, bBLL), (BLR, bBLR) of plural memory cell arrays and connected to the pairs of bit line through the cell array selecting switch, a pre-charge equalizing circuit 15 connected to a pre-charge power source line 40 and the bit line sense amplifier 16 and pre-charging/ equalizing the selected pairs of bit line, and a current limiting element Q20 inserted between the pre-charge equalizing circuit 15 and the pre-charge power source line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory (DRAM), and more particularly to a circuit for precharging and equalizing the potential of a bit line pair in a sense amplifier shared DRAM.

[0002]

2. Description of the Related Art A large-capacity DRAM often employs a sense amplifier sharing system in which a plurality of memory cell arrays share a bit line sense amplifier.

FIG. 9 shows a conventional sense amplifier shared type D.
FIG. 2 is an equivalent circuit diagram showing a part of a core circuit of a RAM (for one column of a memory cell array) and a part of a peripheral circuit (such as a sense amplifier) connected thereto;

In a DRAM memory cell array, a plurality of dynamic memory cells are arranged in a matrix, and a plurality of pairs of word lines for selecting memory cells and a plurality of pairs for transferring data between the memory cells. The bit lines are provided in directions that cross each other.

FIG. 9 shows one bit line sense amplifier 16 among bit line sense amplifiers arranged between memory cell arrays and a memory arranged on the left side of the sense amplifier 16 for simplification of display. A pair of cell array selection switches 13 corresponding to each column of the cell array, a pair of bit lines (BLL, bBLL), one memory cell 11, one word line WLL, and a right side of the sense amplifier 16 are arranged. A pair of cell array selection switches 14 corresponding to each column of the memory cell array, a pair of bit lines (BLR, bBLR),
One memory cell 12 and one word line WLR, one column selection gate 17 shared by each pair of bit lines of the left and right memory cell arrays of the sense amplifier 16, and a pair of data lines connected thereto DQ and bDQ are shown as representatives.

The bit line sense amplifier 16 comprises an NMOS sense amplifier controlled by a sense amplifier control signal SEN and a PMOS sense amplifier controlled by a sense amplifier control signal bSEP. This is to detect and amplify a potential difference generated in a corresponding bit line pair when a cell is selectively driven.

The cell array selection switches 13 and 14 are correspondingly controlled by cell array selection signals .PHI.L and .PHI.R, and the column selection gate 17 is controlled by a column gate control signal CSL.

Further, a bit line precharge circuit 31 is connected to the bit line pair (BLL, bBLL) of the memory cell array on the left side of the sense amplifier 16, and a precharge power supply line 41 is connected to the bit line precharge circuit 31. Is connected.

Similarly, a bit line precharge circuit 32 is connected to the bit line pair (BLR, bBLR) of the memory cell array on the right side of the sense amplifier 16, and a precharge power supply line is connected to the bit line precharge circuit 32. 42 is connected.

The bit line precharge circuit 31 is controlled by an equalize control signal EQL, and connects a correspondingly connected bit line pair (BLL, bBLL) to a precharge power supply line 41.
And is precharged and equalized to the potential Vref supplied from.

Similarly, the bit line precharge circuit 32 is controlled by the equalization control signal EQR, and precharges the correspondingly connected bit line pair (BLR, bBLR) to the potential Vref supplied from the precharge power supply line 42. This is to charge and equalize.

FIG. 10 is a timing waveform diagram showing an operation example of the circuit of FIG.

Next, the operation of the circuit of FIG. 9 will be described with reference to the timing waveform chart shown in FIG.

At the time of access, of the cell array selection signals .PHI.L and .PHI.R, the cell array selection signal to be accessed (.PHI.L in this example) remains at "H", and the cell array selection signal to the non-accessed side (.PHI.R in this example). ) Is set to “L”, and the accessed equalization control signal (EQL in this example) of the bit line equalization control signals EQL and EQR is changed from “H” to “L”. As a result, the selected bit line pair (BLL, bBLL in this example) on the cell array side is brought into a floating state.

Subsequently, the word line (WLL in this example) selected from the external address becomes "H", and the data of the memory cell (11 in this example) is read out to the bit line (BLL in this example).

Subsequently, when the sense amplifier control signal SEN changes from "L" to "H" and the sense amplifier control signal bSEP changes from "H" to "L", the sense amplifier circuit 16
Is activated, and the potential of the corresponding bit line pair BLL, bBLL is detected and amplified.

The amplified output (read data) of the bit line sense amplifier 16 is rewritten to the cell and output to a buffer circuit (not shown) via the data line pair DQ and bDQ.

Thereafter, the access to the cell is stopped by changing the selected word line WLL from "H" to "L". Subsequently, the sense amplifier control signal bSEP is changed from "L" to "H", and the sense amplifier control signal SEN is changed to "H". By switching from “H” to “L”, the sense amplifier circuit 16 is deactivated.

Further, the cell array selection signals .PHI.L, .PHI.R are set to "H", and the equalization control signals EQL, EQR are set to "H", respectively, and the bit line pairs (BLL, bBLL), (BLR,
bBLR) is precharged and equalized and set to the precharge voltage Vref, and the next operation is awaited.

In the above-described conventional sense amplifier circuit, since the left and right cell arrays have the bit line precharge circuits 31 and 32 separately, there is a problem that the pattern area becomes large.

In the case where there is a defect due to a short circuit between the word line and the bit line and the redundant circuit is replaced with a spare memory cell row or a spare memory cell column, a short-circuit defective portion between the word line and the bit line remains. Therefore, at the time of equalization, a leakage current flows from the precharge power supply lines 41 and 42 in the direction of the word line WL in the short-circuit failure portion, so that there is a problem that power consumption during standby increases.

[0022]

As described above, the conventional DRAM has a problem that the pattern area of the bit line precharge circuit becomes large because each of the memory cell arrays shares the bit line sense amplifier. In addition, since a leakage current flows from the precharge power supply line in the direction of the word line at the short-circuit defective portion between the word line and the bit line which has been replaced by the redundant circuit, there has been a problem that power consumption during standby increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it has been proposed to reduce the pattern area of a bit line precharge / equalize circuit and to provide a short circuit between a word line and a bit line which has been replaced by a redundant circuit. It is an object of the present invention to provide a dynamic semiconductor memory capable of reducing leakage current flowing from a precharge power supply line in a part of a word line direction and reducing power consumption during standby.

[0024]

According to a first dynamic semiconductor memory of the present invention, a plurality of memory cell arrays in each of which a plurality of dynamic memory cells are arranged in a matrix, and a memory cell of the memory cell array are selectively driven. A plurality of word lines, a plurality of pairs of bit lines for transmitting and receiving data between selected memory cells of the memory cell array, a plurality of cell array selection switches for selecting the plurality of memory cell arrays, A bit line sense amplifier provided corresponding to each of the bit line pairs of the plurality of memory cell arrays and connected to the bit line pair via the cell array selection switch; and connected to the precharge power supply line and the bit line sense amplifier. Is precharged to the bit line pair selected by the cell array selection switch. A precharge / equalize circuit for precharging a current supplied from a source line and equalizing the bit line pair; and a current limiting element inserted between the precharge / equalize circuit and the precharge power supply line. It is characterized by doing.

According to a second dynamic semiconductor memory of the present invention, there are provided a plurality of memory cell arrays in each of which a plurality of dynamic memory cells are arranged in a matrix, and a plurality of word lines for selectively driving the memory cells of the memory cell array. A plurality of pairs of bit lines for transmitting and receiving data between selected memory cells of the memory cell array;
A plurality of cell array selection switches for selecting the plurality of memory cell arrays; and bit lines provided corresponding to the bit line pairs of the plurality of memory cell arrays, respectively, and connected to the bit line pairs via the cell array selection switches. A sense amplifier connected to the precharge power supply line and the bit line sense amplifier, for precharging a current supplied from a precharge power supply line to a bit line pair selected by the cell array selection switch; A precharge / equalize circuit for equalizing, a current limiting element inserted between the precharge / equalize circuit and the precharge power supply line, and a current limiting element between the precharge / equalize circuit and the precharge power supply line A switching transistor connected in parallel to the In response to operation of the charge-equalizing circuit, and further comprising a control circuit for controlling the ON state of the switching transistor for a predetermined period.

A third dynamic semiconductor memory according to the present invention, in the dynamic semiconductor memory according to the second invention, further comprises a circuit for always controlling the switching transistor to be in an off state when testing the memory cell array. It is characterized by.

According to a fourth dynamic semiconductor memory of the present invention, in a dynamic semiconductor memory of a sense amplifier sharing system in which a plurality of memory cell arrays share a bit line sense amplifier, the potential of a bit line pair is precharged.
A precharge / equalize circuit to be equalized is provided corresponding to the bit line sense amplifier and connected to a precharge power supply line to be shared by a plurality of memory cell arrays, and the bit line is precharged / equalized by the precharge / equalize circuit. In this case, a current supplied from the precharge power supply line to the precharge / equalize circuit is limited.

According to a fifth dynamic semiconductor memory of the present invention, in the fourth dynamic semiconductor memory, the precharge / equalize circuit is provided during a precharge period for the bit line pair selected by the cell array selection switch. The precharge power supply line is temporarily short-circuited to generate a precharge potential on the selected bit line pair.

According to the first and fifth dynamic semiconductor memories of the present invention, since the bit line precharge / equalize circuit is shared by a plurality of memory cell arrays, the area of the bit line precharge / equalize circuit can be reduced. Therefore, a higher degree of integration can be realized and the unit cost per bit can be reduced. Since the current supplied from the precharge power supply line to the bit line precharge / equalize circuit is limited, the precharge power supply line extends in the word line direction of the word line / bit line short-circuit defective portion which has been replaced by the redundant circuit. To reduce the leakage current flowing from
Power consumption during standby can be reduced.

According to the second and sixth dynamic semiconductor memories of the present invention, furthermore, during the precharge period for the bit line pair selected by the cell array selection switch, the precharge / equalize circuit and the precharge power supply line are connected. Since the precharge potential is generated on the selected bit line pair by short-circuiting temporarily, it is possible to avoid the potential drop of the bit line pair during precharge equalization and to correctly detect and amplify the data of the memory cell. As a result, the yield of products can be increased and the cost can be reduced.

According to the third dynamic semiconductor memory of the present invention, the operating conditions can be made stricter at the time of testing at the manufacturing stage than at the time of actual operation, and a circuit including short-circuit failure between word lines and bit lines can be realized. It can be detected reliably.

According to the fourth dynamic type semiconductor memory of the present invention, the gate-type semiconductor device is used as a precharge current limiting element.
Depletion type N-channel M with source short-circuited
When the OS transistor is used, the bit line pair can be precharged to the same potential as the precharge power supply. When the enhancement transistor is used, the threshold control process can be reduced, which is advantageous in cost.

[0033]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, main features of the DRAM of the present invention will be described.

(1) The bit line precharge circuit connected to the bit line sense amplifier circuit shared by a plurality of cell arrays is configured to be shared by the bit line pairs of each cell array.

As a result, the pattern area of the bit line precharge circuit can be reduced, and the chip area of the DRAM can be reduced.

(2) A current limiting element is inserted between the precharge power supply line and the bit line precharge circuit.

With this arrangement, at the time of equalization, the leakage current flowing from the precharge power supply line in the word line direction of the short-circuit defective portion between the word line and the bit line which has been replaced by the redundant circuit is reduced. The bit line equalizing potential is prevented from lowering, and the data in the memory cell is correctly detected by the bit line sense amplifier circuit.
Can be amplified.

(3) A switching MOS transistor is connected in parallel with the current limiting element, and a drive pulse signal is supplied to the gate thereof at a predetermined timing.

Thus, even when a short-circuit between the word line and the bit line exists and a leak current flows due to the short-circuit between the word line and the bit line, a precharge potential can be generated at a high speed in the bit line pair during equalization. it can.

In the test, by not operating the switching transistor, it is possible to efficiently detect a circuit including a short-circuit defective portion between a word line and a bit line.

<First Embodiment> FIG. 1 shows a part of a core circuit (for one column of a memory cell array) of a sense amplifier shared DRAM according to a first embodiment of the present invention and peripheral circuits connected thereto. 3 is an equivalent circuit diagram showing a part (a sense amplifier and the like) of FIG.

The DRAM of FIG. 1 is different from the DRAM of the related art described above with reference to FIG. 9 in that (1) one bit line sense amplifier circuit shared by each pair of bit lines of two cell arrays. Is connected to one bit line precharge circuit (each pair of bit lines of two cell arrays is connected to one bit line).
And (2) a current limiting element is inserted between the precharge power supply line and the bit line precharge circuit. Are the same,
The same reference numerals as in the figure are used.

That is, the DRAM of FIG. 1 exchanges data between a memory cell array in which a plurality of dynamic memory cells 11 and 12 are arranged in a matrix, a plurality of word lines for selecting a memory cell, and a memory cell. A plurality of pairs of bit lines are provided in a direction crossing each other.

FIG. 1 shows one of the bit line sense amplifiers 16 among the bit line sense amplifiers arranged between the memory cell arrays and the memory arranged on the left side of the sense amplifier 16 for simplification of display. A pair of cell array selection switches 13 corresponding to each column of the cell array, a pair of bit lines (BLL, bBLL), one memory cell 11, one word line WLL, and a right side of the sense amplifier 16 are arranged. A pair of cell array selection switches 14 corresponding to each column of the memory cell array, a pair of bit lines (BLR, bBLR),
One memory cell 12 and one word line WLR, one column selection gate 17 shared by each pair of bit lines of the left and right memory cell arrays of the sense amplifier 16, and a pair of data lines connected thereto DQ and bDQ are representatively shown.

The bit line sense amplifier 16 comprises an NMOS sense amplifier controlled by a sense amplifier control signal SEN and a PMOS sense amplifier controlled by a sense amplifier control signal bSEP. This is to detect and amplify a potential difference generated in a corresponding bit line pair when selectively driven.

The cell array selection switches 13 and 14
Are correspondingly controlled by cell array selection signals ΦL and ΦR, and the column selection gate 17 is controlled by a column gate control signal CSL.

Further, one bit line precharge circuit 15 shared by each pair of bit lines of the left and right memory cell arrays of the sense amplifier 16 is connected between a pair of sense nodes of the sense amplifier 16.

A current limiting element Q20 for limiting a leak current is connected between a precharge power supply line 40 to which a precharge power supply (potential Vref) is supplied and the bit line precharge circuit 15.

The bit line precharge circuit 15 is controlled by an equalization control signal EQ at the time of precharge, and is selected by the bit line pair (BLL, bBLL) or (BLR, bB
LR) is precharged and equalized to a potential supplied from the precharge power supply line 40.

As the current limiting element Q20, in this example, a depletion type N-channel MO is used.
Although an S transistor having a short-circuited gate and source is used, the invention is not limited to a depletion type transistor, and an enhancement type transistor may be used. However, when an enhancement transistor is used, a predetermined voltage is supplied to its gate.

In this case, the depletion type transistor is disadvantageous in cost as compared with the enhancement type transistor because the threshold control process is increased, but the bit line pair can be precharged to the potential Vref equal to the precharge power supply.

On the other hand, the enhancement-type transistor is more cost-effective than the depletion-type transistor because the threshold control process is reduced, but the bit line pair is lower than the precharge power supply potential Vref by the threshold voltage. Since only the value can be precharged, the operation speed of the sense amplifier circuit is disadvantageous.

In FIG. 1, Q1 and C1 are charge transfer transistors and information storage capacitors of the memory cell 11, Q2 and C2 are charge transfer transistors and information storage capacitors of the memory cell 12, Q3 to Q5. Is NM
NMOS transistors in the OS sense amplifier section, Q6 to Q8 are PMOS transistors in the PMOS sense amplifier section, Q9 and Q10 are NMOS transistors in the cell array selection switch 13, and Q11 and Q12 are cell array selection switches.
14 NMOS transistors, Q13 to Q15 are NMOS transistors of the bit line precharge circuit 15, Q18 and Q1.
9 is an NMOS transistor of the column selection gate 17.

FIG. 2 is a timing waveform chart showing an operation example of the circuit of FIG.

Next, the operation of the circuit of FIG. 1 will be described with reference to the timing waveform diagram shown in FIG.

At the time of access, of the cell array selection signals .PHI.L and .PHI.R, the cell array selection signal to be accessed (.PHI.L in this example) remains "H", and the cell array selection signal to the non-accessed side (.PHI.R in this example). ) To “L” and the bit line equalize control signal EQ from “H” to “L”.
To As a result, the selected bit line pair (BLL, bBLL in this example) on the cell array side is brought into a floating state.

Subsequently, the word line (WLL in this example) selected from the external address becomes "H", and the data of the memory cell (11 in this example) is read out to the bit line.

Subsequently, the sense amplifier control signal SEN changes from "L" to "H", and the sense amplifier control signal bSEP changes from "H" to "L" to activate the sense amplifier circuit 16 and the potential of the bit line pair. Is detected and amplified.

After rewriting the read data to the cell, the selected word line WLL is changed from "H" to "L" to stop the access to the cell, and subsequently the sense amplifier control signal bS
The EP is switched from “L” to “H”, and the sense amplifier control signal SEN is switched from “H” to “L”.

Further, when the cell array selection signals ΦL and ΦR are set to “H” and the equalization control signal EQ is changed from “L” to “H” to start the precharge operation, each bit line pair is set to the precharge potential Vref. Become.

According to the DRAM of the first embodiment, each pair of bit lines (BLL, bBLL), (BL
R, bBLR) share one bit line precharge circuit 15, so that the conventional DRAM in which one bit line precharge circuit is connected corresponding to each bit line pair of each cell array. In comparison, the pattern area of the bit line precharge circuit can be reduced, and the chip area of the DRAM can be reduced.

Further, even if the short-circuit defective portion between the word line and the bit line to be replaced by the redundant circuit remains after being replaced by the redundant circuit, the precharge power supply line 40 and the bit line precharge circuit 15 And a current limiting element Q20 is inserted between them to limit the precharge current during the precharge / equalize operation.

Therefore, for example, as shown in FIG.
Since the leakage current i flowing from the precharge power supply line 40 and the bit line pair side to the word line direction can be reduced, the reduction of the bit line equalizing potential due to the leakage current i is suppressed, and the data of the memory cell is stored in the bit line. The line sense amplifier circuit 16 can correctly detect and amplify.

The first embodiment has a problem that the bit line precharge circuit 15 is shared by the left and right cell arrays.

When the bit line precharge circuit 15 is not shared by the left and right cell arrays, the cell array opposite to the selected cell array is always precharged. However, due to the sharing, during access to the selected cell array, the cell array on the opposite side is not precharged. That is, in a circuit having a short-circuit defective portion between a word line and a bit line, a leak current flows through the short-circuit defective portion during access to the cell array, so that the potential of the bit line pair is lower than the precharge potential. When the sense amplifier circuit 16 is driven in a state where the precharge potential is lowered, the driving capability of the NMOS transistors Q3 and Q4 in the sense amplifier circuit 16 is reduced, so that the data held in the cell is correctly amplified and detected in a short time. Can not do.

A second embodiment for solving this problem will be described below.

<Second Embodiment> FIG. 3 is an equivalent circuit diagram showing a part of a core circuit and a part of a peripheral circuit of a sense amplifier shared DRAM according to a second embodiment.

The circuit shown in FIG. 3 is different from the circuit described above with reference to FIG. 1 in that (1) a switching NMOS transistor Q30 is connected in parallel with a current limiting element Q20, and a control circuit 30 is connected to its gate. Is supplied with a switch control signal (pulse signal) SW generated by the switch transistor
The difference is that Q30 is driven at a predetermined timing, and the other components are the same.

FIGS. 4A and 4B show an example of the configuration and operation waveforms of the control circuit 30 in the circuit of FIG.

The circuit shown in FIG. 4A has a known configuration including a plurality of inverter circuits IV and one two-input NOR gate NG, and receives a pulse signal input (in this example, an equalization as shown in FIG. 4B). The logic configuration is such that a pulse signal having a short width (a switch control signal SW as shown in FIG. 4B in this example) is output slightly later than the rise of the control signal EQ).

FIG. 5 is a timing waveform chart showing an operation example of the circuit of FIG.

FIG. 6 is a circuit diagram of the circuit shown in FIG. 1 or the circuit shown in FIG. 3 to which a switching transistor Q30 shown by a dotted line is added. FIG. 7 is an equivalent circuit diagram showing a state in which a leak current i flows from a precharge power supply line 40 / bit line BL side to a word line WL during charging.

FIG. 7 shows the precharge / equalization characteristics of the bit line pair (BLL, bBLL) and (BLR, bBLR) during the precharge of the circuit of FIG.

For comparison, the circuit shown in FIG.
1 also shows a precharge / equalization characteristic when there is no leakage current in the circuit of FIG. 1 and a precharge / equalization characteristic when there is a leakage current in the circuit of FIG.

Next, the operation of the circuit of FIG. 3 will be described with reference to FIGS.

The switch control signal SW temporarily becomes “H” during the equalizing period, that is, during the period when the equalizing control signal EQ is “H”, and turns on the switching transistor Q30 to turn on the precharge power supply line 40. And the precharge circuit 15 are temporarily short-circuited.

As a result, even when a short-circuit between the word line and the bit line exists and a leak current i flows due to the short-circuit between the word line and the bit line as shown in FIG. 6, equalization as shown in FIG. Sometimes bit line pairs (BLL, bBLL)
And (BLR, bBLR) can generate the precharge potential Vref at high speed.

The DRAM of the first embodiment shown in FIG.
In particular, consider the case where the cell array on the side where there is no short-circuit failure between word lines and bit lines is active for a long time and then the cell array on the side where there is a short-circuit failure between word lines and bit lines is accessed. In this case, FIG.
As shown in the figure, the time until the completion of the precharge / equalization for the bit line pair of the cell array is delayed, and the equalization level of the bit line pair before the equalization is sufficiently completed is lower than Vref (in other words, the equalization The cell is accessed for a short period of time). This allows
NMOS transistors Q3 and Q4 in the sense amplifier circuit 16
Since the potential difference between the gate and the source is small compared to the case where there is no short-circuit failure between the word line and the bit line, there is a problem that data in the memory cell cannot be correctly detected and amplified.

On the other hand, according to the DRAM of the second embodiment shown in FIG. 3, the operation shown in FIG.
As shown in FIG. 7, the bit line pairs (BLL, bBLL) and (BL
R, bBLR), the precharge potential Vref can be generated in a short time, and the data of the memory cell can be correctly detected and amplified.

As described above, a circuit including a short-circuit between a word line and a bit line cannot correctly detect and amplify data in a memory cell if the bit line equalize level is too low due to a leak current. Such a short-circuit defect is usually detected as a defect during a test in a manufacturing stage, and the short-circuit defective portion is replaced with a redundant circuit.

However, when the test in the manufacturing stage passes, for example, when the leak current due to the short-circuit failure between the word line and the bit line is small, the device may malfunction during the actual use in the product stage.

In order to solve the above-mentioned problem, a method for reliably detecting a circuit including a short-circuit between a word line and a bit line by making operating conditions stricter during a test in a DRAM manufacturing stage than during an actual operation. The circuit and the circuit will be described below.

FIG. 8 is a timing waveform chart showing an operation example of a DRAM according to a test method for detecting a short circuit between a word line and a bit line in the DRAM of the second embodiment.

This test method is different from the DRAM of the second embodiment in that the switch control signal SW30 (Q30 in FIG. 3) is always turned off during the test in the manufacturing stage. In the inactive state (“L”)
Level).

As an example of this change, for example, a two-input gate circuit (not shown) is connected to the input section of the control circuit 30 in FIG.
And an EQL signal is input to one input terminal of the gate circuit, and a signal for controlling passage / inhibition of the gate according to normal / test time (for example, generated based on a test mode signal) is input to the other input terminal. Signal).

As shown in FIG. 8, the operation waveform at the time of the test according to this test method is the DR of the second embodiment shown in FIG.
It is basically the same as the operation waveform of AM, but differs in the following point.

That is, since the switch control signal SW is at the “L” level and the switching transistor Q30 is in the off state, the equalize control signal EQ transitions from “L” to “H”, and all bit line pairs are switched. When precharging and equalizing from the "L" level to a desired potential, if there is a short-circuit failure between word lines and bit lines, precharging takes time.

When the cell is accessed in this state, the equalization level of the bit line pair (BLL, bBLL) and (BLR, bBLR) is lower than the potential Vref of the precharge power supply line 40, NM in circuit 16
The potential difference between the gate and source of the OS transistors Q3 and Q4 is small, and data in the memory cell cannot be detected and amplified correctly. That is, it is possible to easily detect a circuit including a short circuit between the word line and the bit line.

As described above, according to the DRAM of the second embodiment, when testing at the manufacturing stage, the switch control signal SW is kept at "L" and the switch transistor Q30 is turned off as shown in FIG. Since the sense amplifier circuit 16 is operated in this state, a circuit including a short circuit between the word line and the bit line can be easily detected, the yield of products can be increased, and cost reduction can be promoted.

When operating as an actual product, it is operated as shown in FIG. 5, and during the precharge / equalization period, precharge / equalization is performed in a short time to the potential Vref of the precharge power supply line 40. Thus, the data of the memory cell can be correctly detected and amplified.

[0092]

As described above, according to the dynamic semiconductor memory of the present invention, the pattern area of the bit line precharge / equalize circuit is reduced, and the short circuit between the word line and the bit line to be replaced by the redundant circuit is achieved. Leakage current flowing from the precharge power supply line in the word line direction of the defective portion can be reduced, and power consumption during standby can be reduced.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a part of a core circuit and a part of a peripheral circuit of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a timing waveform chart showing an operation example of the circuit of FIG.

FIG. 3 is a circuit diagram showing a part of a core circuit and a part of a peripheral circuit of a DRAM according to a second embodiment of the present invention.

4 is a diagram showing an example of a configuration and operation waveforms of a control circuit in the circuit of FIG.

FIG. 5 is a timing waveform chart showing an operation example of the circuit of FIG. 3;

6 is an equivalent circuit diagram showing a state in which a leak current flows when a short circuit between a word line and a bit line exists in the circuit of FIG. 3;

FIG. 7 is a characteristic diagram showing how a precharge potential is generated in a bit line pair in a short time by the circuit of FIG. 3;

FIG. 8 shows a DRAM according to a test method for detecting a short circuit between a word line and a bit line with respect to the DRAM of the second embodiment.
FIG. 6 is a timing waveform chart showing an operation example of FIG.

FIG. 9 is an equivalent circuit diagram showing a part of a core circuit and a part of a peripheral circuit of a conventional sense amplifier shared DRAM.

FIG. 10 is a timing waveform chart showing an operation example of the circuit of FIG. 9;

[Explanation of symbols]

11, 12: memory cells, 14: cell array selection switch, 15: bit line precharge / equalize circuit, 16: bit line sense amplifier, 17: column selection gate, 30: switch transistor control circuit, 40: precharge power supply line, Q1 to Q5, Q9 to Q19: NMOS transistors, Q6 to Q8: PMOS transistors, Q20: Current limiting elements (depletion type NMOS transistors), Q30: Switching transistors WLL, WLR: Word lines, BLL, bBLL, BLR, bBLR ... Bit line pair, DQ, bDQ: Data line pair, EQ: Equalize control signal, SEN, bSEP: Sense amplifier control signal, SW: Switch control signal, CSL: Column gate control signal, ΦL, ΦR: Cell array selection signal.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B024 AA01 AA07 BA05 BA07 CA07 CA17 5L106 AA01 CC17 CC31 EE02 FF01 GG01 GG07

Claims (6)

[Claims] 1. A plurality of memory cell arrays each having a plurality of dynamic memory cells arranged in a matrix, a plurality of word lines for selectively driving memory cells of the memory cell array, and a selected memory of the memory cell array A plurality of pairs of bit lines for transmitting and receiving data to and from cells; a plurality of cell array selection switches for selecting the plurality of memory cell arrays; and a plurality of bit line pairs for the plurality of memory cell arrays. A bit line sense amplifier connected to the bit line pair via the cell array selection switch; and a precharge circuit connected to the precharge power supply line and the bit line sense amplifier, and precharged to the bit line pair selected by the cell array selection switch. Precharge the current supplied from the power supply line, and Dynamic semiconductor memory characterized by comprising: a precharge equalize circuit for equalizing, and a current limiting element inserted between the pre-charge power supply line and the precharge and equalizing circuit. 2. A memory cell array in which a plurality of dynamic memory cells are arranged in a matrix, a plurality of word lines for selectively driving memory cells of the memory cell array, and a selected memory of the memory cell array. A plurality of pairs of bit lines for transmitting and receiving data to and from cells; a plurality of cell array selection switches for selecting the plurality of memory cell arrays; and a plurality of bit line pairs for the plurality of memory cell arrays. A bit line sense amplifier connected to the bit line pair via the cell array selection switch; and a precharge circuit connected to the precharge power supply line and the bit line sense amplifier, and precharged to the bit line pair selected by the cell array selection switch. Precharge the current supplied from the power supply line, and A precharge / equalizing circuit for equalizing; a current limiting element inserted between the precharge / equalizing circuit and the precharge power line; and a current limiting element between the precharge / equalizing circuit and the precharge power line. A dynamic semiconductor memory, further comprising: a switching transistor connected in parallel to the switching transistor; and a control circuit that receives the operation of the precharge / equalize circuit and turns on the switching transistor for a predetermined period. 3. The dynamic semiconductor memory according to claim 2, further comprising: a circuit that always controls said switching transistor to be in an off state when testing said memory cell array. 4. The dynamic semiconductor memory according to claim 1, wherein said current limiting element is a depletion type N-channel MOS transistor having a gate and a source short-circuited or an enhancement type transistor. A dynamic semiconductor memory characterized in that: 5. A dynamic semiconductor memory of a sense amplifier sharing type in which a bit line sense amplifier is shared by a plurality of memory cell arrays. The precharge / equalization circuit is shared by a plurality of memory cell arrays by connecting to the precharge power supply line, and when the bit line is precharged / equalized by the precharge / equalization circuit, the precharge is performed from the precharge power supply line. A dynamic semiconductor memory characterized by limiting a current supplied to an equalizing circuit. 6. The dynamic semiconductor memory according to claim 5, wherein said precharge / equalize circuit and said precharge power supply line are temporarily connected during a precharge period for a bit line pair selected by said cell array selection switch. A dynamic semiconductor memory, wherein a short circuit is generated to generate a precharge potential on the selected bit line pair.