JP3400135B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a defect repair technique for repairing a defect in a part of a memory cell by a redundant memory cell,
For example, dynamic random access memory (D
(Abbreviated as RAM)) and effective technology.

[0002]

2. Description of the Related Art A redundant configuration has been conventionally used for the purpose of improving the yield of semiconductor memory devices such as DRAM. The redundant structure has spare bits or spare elements, and if a defect is found during the wafer probe test, the defective circuit portion is switched to a predetermined spare element. Address information for such switching (called redundant address) is programmed in the redundant program circuit. If there is no defective bit, redundant repair is not performed, but if a defect is found at the wafer probe test stage and the address information to replace it with the spare element is programmed, the address input from the outside The redundant address is compared, and if they match, the redundant word line or redundant data line is selected instead of the regular word line or regular data line. so,
When the redundant word line or the redundant data line is selected, the inhibit word circuit prohibits the selection of the regular word line or the regular data line. The setting of the redundant address has been performed by using a laser beam or the like to blow a fuse element formed of polysilicon or the like as necessary, but in recent years, instead of the fuse formed of polysilicon or the like, Non-volatile storage elements such as EPROM cells have come to be used.

FIG. 8 shows a conventional redundant decoder.
Redundant address storage circuit 4 for storing redundant addresses
1 to 44 are provided, and addresses A1, A1 * (* means low active or signal inversion) to A4, A4 * given from the outside for memory access, and storage of the redundant address storage circuits 41 to 44. Match comparison circuits CAM1 to CAM4 are provided for comparison with information. A NOR circuit 45 for obtaining the NOR logic of the output signals of the match comparison circuits CAM1 to CAM4 is provided at the subsequent stage of the match comparison circuits CAM1 to CAM4. Based on the output signal of the NOR circuit 45, a redundant row or a redundant column is provided. The selection of is made. That is, the input address and the redundant address are compared in bit units, and when both addresses match,
A redundant row or a redundant column is selected. Match comparison circuit C
AM1 to CAM4 have the same configuration. Match comparison circuit C
As representatively shown in the structure of AM4, the coincidence comparison circuits CAM1 to CAM4 are p-channel MOS transistors, respectively.
It includes a transfer gate formed by connecting a transistor Q1 and an n-channel MOS transistor Q2 in parallel, and has redundant addresses f, f * and input addresses A4, A4 *.
It will be compared with.

FIG. 9 shows the configuration of the redundant address storage circuit. An EPROM 40 is provided as a storage unit of the decoding information regarding the address of the defective line. p-channel type MOS transistors 33 and 34 are connected in series, and p
Channel type MOS transistors 35 and 36 are connected in series. By applying the voltage VREF to the gate electrode of the n-channel type MOS transistor, the n-channel type MOS transistor 39 is operated, and the EP
ROM 40 is coupled to node 42. Inverters 37, 38 are provided to obtain complementary level output signals f, f *. By feeding back the output signal of the inverter 37 to the p-channel type MOS transistor 36, the logical states of the output signals f and f * are held. This hold state is released by the reset signal RESET *.

As an example of a document describing the redundancy repair technique, there is JP-A-2-239800.

[0006]

According to the above prior art, the redundant address storage circuit and the coincidence comparison circuit are separately arranged for each complementary level address signal pair. The chip occupation area of the decoder circuit becomes large. If the capacity of the semiconductor memory device is further increased in the future and the number of redundant repair lines is increased accordingly, the chip area will be increased due to the increase of redundant decoders, which may reduce the yield.

An object of the present invention is to provide a technique for suppressing the chip occupation area of the redundant decoder as much as possible even when the capacity of the semiconductor memory device is increased and the number of redundant repair lines is increased accordingly. is there.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a nonvolatile memory element capable of programming the operation of the redundant circuit, a circuit for forming a complementary address based on the redundant address stored in the nonvolatile memory element, and a state of this circuit, A plurality of comparing means including a transistor for enabling bit-by-bit comparison between the redundant address and the input address are arranged in the row and column directions corresponding to the bit configuration of the input address and the number of redundant repair lines. To do. At this time, a plurality of first transistors driven according to the comparison result of the comparison means are arranged corresponding to the comparison means, and the first transistors are mutually arranged corresponding to the arrangement of the comparison means in the column direction. It can be configured to obtain a match signal between the input address and the redundant address by being connected in series. A plurality of second transistors driven according to the comparison result of the comparison means are arranged corresponding to the comparison means, and the second transistors are connected in parallel to each other corresponding to the arrangement of the comparison means in the column direction. By doing so, it is possible to obtain a mismatch signal between the input address and the redundant address.

[0011]

According to the above means, the flip-flop set based on the redundant address stored in the non-volatile memory element and the bit unit of the redundant address and the input address depending on the set state of the flip-flop. Forming a comparison means including a transistor for enabling comparison, and comparing the comparison means with the bit configuration of the input address;
Also, arranging a plurality of rows in the row and column directions corresponding to the number of redundant relief lines enables efficient layout by the matrix arrangement of the comparison means, and increases the chip occupation area when the number of redundant relief lines is increased. Keep it as low as possible.

[0012]

FIG. 7 shows a DRAM which is an embodiment of the present invention. Although not particularly limited, the DRAM shown in the figure is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique. Figure 7
In 54, 54 is a normal memory cell array in which a plurality of dynamic memory cells are arranged in a matrix, and the selection terminals of the memory cells are connected to word lines in each row direction,
The data input terminal of the memory cell is coupled to the complementary data line in each column direction. And each complementary data line is
It is commonly connected to the complementary common data line through a column selection circuit 57 including a plurality of column selection switches coupled to the complementary data line in a one-to-one relationship. Although not particularly limited, an address multiplex system is adopted, and row and column address input signals are taken in from a common address terminal by shifting their timings. That is, an address signal given from the outside is input to the normal row decoder 52 and the column decoder 56. To smoothly perform such address input, two types of clock signals, a row address strobe signal RAS * and a column address strobe signal CAS *, are externally applied. Read during one memory cycle (one cycle of the row address strobe signal RAS *),
Alternatively, in order to enable only one of the write operations, the row address is taken into the internal circuit when the row address strobe signal RAS * falls, and the column address is taken into the internal circuit when the column address strobe signal CAS * falls. The state of the write enable signal WE * makes it possible to determine whether the relevant cycle is a write cycle or a read cycle. Furthermore, the output enable signal O
When E * is asserted to the low level, the read data can be output to the outside. The control unit 55 performs such determination and operation control of each unit.
The control unit 55 includes a self-refresh control system for refreshing the stored contents of the dynamic memory cell at a predetermined cycle.

Based on the decoded output of the normal row decoder 52, the word line of the normal memory cell array 54 is driven to the selected level. Then, the column selection circuit 57 is driven based on the decoded output of the column decoder 56, and data reading or data writing from the memory cell specified by this is enabled. Further, a sense amplifier 59 for amplifying weak memory cell data is provided. The data input / output circuit 58 includes a main amplifier,
The read data can be transmitted to the outside through the main amplifier. Although not particularly limited, in the refresh operation, the sense amplifier 59 is used as a refresh amplifier circuit. That is, the signal detected and amplified by the sense amplifier 59 is rewritten in the memory cell, so that the dynamic memory cell is refreshed. When a read / write operation is performed, all memory cells coupled to the selected word line are refreshed at the same time. Therefore, the regular memory cell array 5
In order to refresh all four, the refresh operation is performed by the number of word lines in a certain time while changing the selected word line.

A redundant memory cell array 23 and the redundant memory cell array 2 are provided as a redundant structure for relieving a part of the defects of the normal memory cell array 54 in word units.
A redundant decoder 51 for selectively driving the three redundant word lines is provided. The normal memory cell array 54 has a defect, and address information (redundant address) for relieving the defect is programmed in the storage means in the redundant decoder 51. When a redundant address for relieving a part of the defect in the normal memory cell array 54 is programmed in the redundant decoder 51, the row address input from the outside is compared with the redundant address. , The redundant memory cell array 5 instead of the regular word line in the regular memory cell array 54.
The redundant word line in 3 is selected.

FIG. 1 shows a detailed structure of the redundant decoder 51 included in the DRAM. Redundant decoder 51 shown in FIG. 1 includes, but is not limited to, sense level setting circuit group 4, match comparison circuit group 2, drive circuit 18, power supply detection circuit 12, and buffer group 6.

The buffer group 6 has a plurality of buffers 16 arranged corresponding to the number of bits of the complementary level input addresses A0, A0 * to An-1, An-1 *. The output terminals of the plurality of buffers 16 are commonly connected to the address input terminals of the match comparison circuits arranged in the row direction, and the input address signal is transmitted to the corresponding match comparison circuits for address comparison. It is supposed to be done. For example, the address signals DA0 and DA0 * output from the buffers 16 and 16 corresponding to the complementary-level input addresses A0 and A0 * are the same as the match comparison circuits CAM00 to CAM.
i-10, address signals An-1, An-1 are transmitted.
The address signals DAn-1 and DAn-1 * output from the buffers 16 and 16 corresponding to * correspond to the coincidence comparison circuit CA.
It is adapted to be transmitted to M0n-1 to CAMi-1n-1.

The match comparison circuit group 2 includes an EPROM cell for storing a redundant address, and has a function of comparing the redundant address stored in this EPROM cell with an address inputted from the outside for memory access. Have,
A plurality of coincidence comparison circuits CA arranged and formed in a matrix
Includes M00 to CAMi-1n-1. That is, i matching comparison circuits are arranged in the row direction (arrow X direction) and n in the column direction (arrow Y direction) (i and n are both positive integers). The number of arrays in the column direction of the coincidence comparison circuit is the same as the input addresses A0, A0 * to An-1, An-1 of complementary levels.
It corresponds to *. For example, when the input address has an 8-bit structure, n = 8. The number i of arrays of the coincidence comparison circuits in the row direction corresponds to the number of redundant relief lines, for example, redundant word lines in the redundant memory cell array 53. For example, when the number of redundant word lines is 4, i = 4. That is,
The bit configuration of the input address determines the number of arrays of the match comparison circuit in the column direction, and the number of redundant word lines determines the number of arrays of the match comparison circuit in the row direction. Then, the addresses DA0, DA0 * ...
DAn-1 and DAn-1 * are commonly input to each of the coincidence comparison circuits arranged in the row direction. For example, the addresses DA0 and DA0 * are assigned to the match comparison circuit CAM.
00 to CAMi-10 are commonly input, and similarly, the addresses DAn-1 and DAn-1 * are coincidence comparison circuits CAM0.
It is commonly input to n-1 to CAMi-1n-1.

A plurality of coincidence comparison circuits CAM00 to CAMi
The n-channel MOS transistors QH00 to QHi-1n- are connected to the comparison result output terminals of -1n-1.
1 and p-channel type MOS transistors QM00 to QM00
QMi-1n-1 are coupled so that they are driven by the output signals of the corresponding coincidence comparison circuits. N-channel type MOS transistors QH00 to QH
i-1n-1 are connected to each other in series for each column, and are provided to form the match signals HS0 to HSi-1 by obtaining the NAND logic of the output signals from the corresponding match comparison circuits. The p-channel type MOS transistors QM00 to QMi-1n-1 are connected in parallel for each column and form the mismatch signals MS0 to MSi-1 by obtaining the NOR logic of the output signals from the corresponding match comparison circuits. It is provided in.

Further, the power supply detection circuit 12 has a function of detecting power-on of the power supply voltage and generating a power-on set signal, and the power-on set signal from the power supply detection circuit 12 is supplied to the drive circuit 18 in the subsequent stage. It is being transmitted. The drive circuit 18 has a function of supplying a power-on set signal and a write high voltage signal to the coincidence comparison circuits CAM00 to CAMi-1n-1 via the control line 24.

The sense level setting circuit group 4 sets the sense level of the coincidence signal or the non-coincidence signal from the coincidence comparison circuit group 2 and is not particularly limited. A plurality of sense level setting circuits 14 corresponding to the number of signals are included. The plurality of sense level setting circuits 14, as one of which is representatively shown, is an n-channel type MOS for precharge.
A transistor Qpr, an n-channel MOS transistor Qdis for discharging, and an n-channel MOS transistor Qds for transfer are coupled.
The n-channel type MOS transistor Qpr is coupled to the high potential side power supply Vcc and precharges the signal transmission path at the timing when the precharge control signal φpr is asserted to the high level. Further, the n-channel type MOS transistor Qdis is coupled to the low potential side power source Vss and discharges the electric charge in the signal transmission path at the timing when the discharge control signal φdis is asserted to the high level. Furthermore, an n-channel MOS transistor Q
ds is a timing at which the transfer control signal φds is asserted to a high level, and fetches the comparison result from the match comparison circuit group 2. n-channel type MOS transistor Qpr
With the signal transmission path precharged by, the comparison result is fetched from the coincidence comparison circuit group 2 through the n-channel MOS transistor Qds.

Further, the coincidence signals HIT0 to HITi-1.
Alternatively, a sense amplifier SA for outputting the disagreement signals Miss0 to Missi-1 is provided. Matching signals HIT0 to HITi output via the sense amplifier SA
The number of -1 corresponds to the number of redundant word lines in the redundant memory cell array 53. That is, when the coincidence signal is asserted to the high level, the redundant word line corresponding to it is driven to the selection level. At this time, the normal word line in the normal memory cell array 54 is prohibited by an inhibit circuit (not shown).

FIG. 2 shows the redundant word line 1 for convenience of explanation.
The structure of the part corresponding to the book is extracted and shown. Incidentally, FIG.
In, the transfer MOS transistor Qds is omitted. Complementary level input address DA0, DA0 * to DA
n-1 and DAn-1 * are coincidence comparison circuits CAM00 to C
The signal is input to AM0n-1 in complementary bit units. n-channel type MOS transistor QH00
To QH0n-1 are connected in series, and the comparison result signal 20 from the coincidence comparison circuits CAM00 to CAM0n-1 is input to the gate electrodes of the n-channel MOS transistors QH00 to QH0n-1. M
The OS transistor QH0n-1 is coupled to the low potential side power supply Vss, and the MOS transistor QH00 is coupled to the high potential side power supply Vcc via the precharge n-channel type MOS transistor Qpr and the discharge n-channel type. MOS transistor Qdis
Is connected to the low potential side power source Vss via. When the precharge signal φpr is at high level, the n-channel type MOS transistor Qpr is turned on to precharge the node HS0. Further, when the discharge signal φdis is at high level, the n-channel type M
The node HS0 is discharged by turning on the OS transistor Qdis. The logic level of the node HS0 is output to the subsequent circuit via the sense amplifier SA1.

Further, the coincidence comparison circuits CAM00 to CAM0
The comparison result signal 20 from n-1 is the match comparison circuit CAM.
Input to the gate electrodes of p-channel type MOS transistors QM00 to QM0n-1 arranged corresponding to 00 to CAM0n-1. The p-channel type MOS transistors QM00 to QM0n-1 are connected in parallel with each other. p-channel type MOS transistors QM00-Q
The drain electrode of M0n-1 is coupled to the low potential power supply Vss. p-channel type MOS transistor QM00-
The source electrode of QM0n-1 is a node MS0, and this node MS0 is an n-channel MO for precharging.
It is coupled to the high potential side power source Vcc via the S transistor Qpr, and is connected to the low potential side power source Vs via the discharge n-channel type MOS transistor Qdis.
bound to s. Further, the logic level of the node MS0 is output to the subsequent circuit via the sense amplifier SA2.

The coincidence comparison circuits CAM00 to CAMi-
1n-1 have the same configuration, and FIG. 4 representatively shows a configuration example of the coincidence comparison circuit CAM00. A flip-flop FF for holding a redundant address is provided. An EPROM cell Q9 and n-channel MOS transistors Q5 and Q6 are coupled to one node N1 of the flip-flop FF, and the other node N2 is coupled to the other node N2.
EPROM cell Q10 and n-channel type MOS transistors Q7 and Q8 are coupled. EPROM cells Q9, Q
A control line 24 is coupled to the gate electrode of 10, and a power-on set signal and a writing high voltage can be applied via the control line 24. The n-channel type MOS transistors Q5 and Q7 are transfer MOS transistors,
When the data set word line 22 is driven to the high level, the address signals DA0 and DA0 * are transferred to the node N.
1 and N2 can be transmitted. The n-channel type MOS transistors Q6 and Q8 are MOS transistors for outputting the address comparison result, and are respectively connected to the nodes N1 and N1.
When N2 is at high level, address signals DA0, DA
The logic state of 0 * is output as the comparison result signal 20. The flip-flop FF includes a p-channel type MOS transistor Q1 and an n-channel type MOS transistor Q3.
And a second inverter formed by a p-channel type MOS transistor Q2 and an n-channel type MOS transistor Q4.

The write operation to the EPROM cells Q9 and Q10 will be described. Writing to the EPROM cells Q9 and Q10 is performed by first erasing the EPROM cells Q9 and Q10 by irradiating ultraviolet rays or applying a voltage, and then, the potential difference (Vcc / Vcc / D0 *) of the address signals DA0 and DA0 * of complementary levels
Vss) is used to set one node N1 to high level and the other node N2 to low level. Next, the writing high voltage Vpp is applied to the control line 24 in a pulse form. Although not particularly limited, the high voltage for writing Vpp is 12
V. By applying such high voltage, EPROM
The potential difference between the gate and drain of cell Q10 is 12V, E
The potential difference between the gate and drain of PROM cell Q9 is 9V
Becomes Electrons due to hot electrons are injected into the floating gate of the EPROM cell Q10, and the threshold Vth of the EPROM cell Q10 is raised. At this time, the threshold Vth of the EPROM cell Q9 is hardly changed, and the low level state of the threshold Vth immediately after the erasing is maintained. As a result, the flip-flop FF
Is the EPROM whose threshold Vth is low.
Since a current flows on the cell side, the node N2 is at low level,
The node N1 goes high. That is, the logical state of the flip-flop FF is set according to the storage states of the EPROM cells Q9 and Q10. EPROM cell Q9,
Although the writing to Q10 has been described, the actual writing of the redundant address is performed for each match comparison circuit row. The redundant address once written in the EPROM cell is retained even when the power is cut off, and the retained information (retained address) is retained.
It is set in the flip-flop FF by power-on set every time the power is turned on.

As described above, the redundant address (node N1
Consider the case where the address signal DA0 is at the high level and the address signal DA0 * is at the low level in the state where the flip-flop FF is set to the low level and the node N2 is at the high level. At this time, since the node N2 is at the high level from the set state of the flip-flop,
The n-channel MOS transistor Q8 is turned on, and the comparison result signal 20 is set to the low level due to the current flowing according to the driving capability of the address signal DA0 *.
This state means that the stored information in the EPROM cell and the input address do not match. Since the node N1 is at low level, the n-channel type MOS transistor Q6 is turned off. Conversely, the address signal D
When A0 is at low level and the address signal DA0 * is at high level, the comparison result signal 20 is at high level, which means that the stored information of the EPROM cell matches the input address. Since the power-on set signal is applied to the control line 24 in a pulse form, the gate electrodes of the EPROM cells Q9 and Q10 after power-on set become the low-potential-side power supply Vss. This makes it possible to retain stored information for a long period of time as compared with the case where a voltage is constantly applied to the gate electrodes of the EPROM cells Q9 and Q10. That is,
It is possible to improve the disturbance resistance of the EPROM cell.

Next, the operation of the redundant decoder 51 will be described. N-channel type MOS transistor QH00-
Since the QH0n-1s are connected in series with each other, the node H can be output only when the comparison result signals 20 from all the match comparison circuits CAM00 to CAM0n-1 are at the high level.
S0 becomes low level, which causes the sense amplifier SA
The match detection signal HIT0 from 1 is asserted to a high level. In other words, when all the bits of the input address signal match the redundant address set in the flip-flop FF, the node HS0 is set to low level and the match detection signal HIT0 from the sense amplifier SA1 is set to high level. Asserted.

On the contrary, in the above address comparison, if all the bits do not match, the node HS0 becomes high level, so the match detection signal H from the sense amplifier SA1.
IT0 is set to low level. At this time, one of the p-channel type MOS transistors QM00 to QM0n-1 is turned on, so that the node MS0 is set to low level,
As a result, the mismatch detection signal M from the sense amplifier SA2
iss0 is asserted to a high level. In the match comparison circuit group 2, it is possible to set a different redundant address for each match comparison circuit arranged in the column direction, and therefore it is possible to repair a plurality of normal word lines by the setting.

The coincidence signals HIT0 to HITi-1 and the non-coincidence signals Miss0 to Missi-1 are formed in a pulse shape as shown in FIG. When the match signal HIT0 is asserted to the high level, it means that the input address and the redundant address match, that is, the input address signal selects the defective bit in the normal memory cell array 54. Since it is an address, the redundant decoder 51 selects a redundant word line instead of the normal word line. The redundant word line is not selected unless the match detection signal HIT0 is asserted to the high level.

In the above address comparison, if the input address and the redundant address do not match, the mismatch detection signal Miss0 is asserted to the high level to form a pulse signal. The reason for generating the non-coincidence signal separately from the coincidence signal is as follows.
Due to the comparison between the input address and the redundant address, it takes a predetermined time from the input of the address to the assertion of the match detection signal HITO. In order to accurately switch between the normal word line and the redundant word line, it is preferable that the timing at which the normal word line is selected after the address is given and the timing at which the redundant word line is selected are equal.
However, since the match detection signal is a signal that is asserted only when the input address and the redundant address match, the timing of selecting the normal word line when such a signal does not match is selected when the redundant word line is selected. Can not be adjusted to. Therefore, the p-channel type MOS transistors QM00 to QMi-1n-1 are connected in parallel to each other in correspondence with the arrangement of the coincidence comparison circuits in the column direction, whereby the non-coincidence signal Miss of the input address and the redundant address is generated.
Is generated, and the selection timing of the normal word line is matched with the selection timing of the redundant word line based on that. By thus generating the mismatch signal in addition to the match signal, it is possible to easily match the timing when the normal word line is selected and the timing when the redundant word line is selected after the address is given. .

According to the above embodiment, the following operational effects can be obtained. (1) EPROM cell Q9 as a non-volatile memory element,
Flip-flop FF set based on the redundant address stored in Q10, and this flip-flop FF
According to the set state of, the coincidence comparison circuits CAM00 to CAMi-1n-1 are formed including the n-channel type MOS transistors Q6 and Q8 for enabling the bit-by-bit comparison of the redundant address and the input address, By arranging a plurality of the match comparison circuits in the row and column directions corresponding to the bit configuration of the input address and the number of redundant word lines, the redundant decoder 51 can be efficiently laid out and the number of redundant word lines can be reduced. Even if the number is increased, the increase in the chip occupation area of the redundant decoder 51 can be suppressed as much as possible. As a result, it is possible to prevent a decrease in chip yield. (2) Matching comparison circuits CAM00 to CAMi-1n-
N-channel type MOS driven according to the comparison result of 1
A plurality of transistors QH00 to QHi-1n-1 are arranged corresponding to the coincidence comparison circuit, and the n-channel type M
By connecting the OS transistors QH00 to QHi-1n-1 in series corresponding to the arrangement of the coincidence comparison circuits in the column direction, a coincidence signal between the input address and the redundant address can be easily obtained. (3) The coincidence comparison circuit CAM00 to CAMi-1n-
P-channel type MOS driven according to the comparison result of 1
A plurality of transistors QM00 to QMi-1n-1 are arranged corresponding to the coincidence comparison circuit, and the p-channel type M
By connecting the OS transistors QM00 to QMi-1n-1 in parallel to each other corresponding to the arrangement of the coincidence comparison circuits in the column direction, a non-coincidence signal between the input address and the redundant address can be easily obtained. Then, by obtaining the non-coincidence signal, it is possible to easily match the timings when the redundant word line is selected and when the normal word line is selected. (4) The match / mismatch detection speeds of the above-described embodiments are the same as the MOS transistors Q6, Q8, QH00 to QHi-1n-1,
Since it is determined by the ON current value such as QM00 to QMi-1n-1, high-speed operation can be expected by supplying a sufficient ON current.

FIG. 5 shows another configuration example of the coincidence comparison circuit. The match comparison circuit shown in FIG. 5 differs from that shown in FIG. 4 in that n-channel type MOS transistors Q11 and Q12 are coupled to EPROM cells Q9 and Q10, respectively.

This n-channel MOS transistor Q
11 and Q12 respectively connect the drain electrodes of the EPROM cells Q9 and Q10 to the node N according to the level of the control line 24.
1, acts to bind to N2. That is, only when the control line 24 is at the high level, the n-channel type MOS
By turning on the transistors Q11 and Q12, the drain electrodes of the EPROM cells Q9 and Q10 are coupled to the nodes N1 and N2, respectively.
The control line 24 is set to the high level only when the power-on set and the write high voltage are applied. Therefore, the EPR is not performed except when the power-on set and the write high voltage are applied.
Since the drain electrodes of the OM cells Q9 and Q10 are opened, the drain / disturb resistance of the EPROM cells Q9 and Q10 can be improved. In addition, the control line 24
By controlling the high level of the EPROM cell Q
Since the drain voltages of 9 and Q10 can be controlled to a low level, the durability can be further improved. In some cases, M
Similar effects can be expected even if the gate electrodes of the OS transistors Q11 and Q12 are separated from the control line 24 and controlled to a low level.

FIG. 6 shows another further configuration example of the coincidence comparison circuit. The match comparison circuit shown in FIG. 6 is different from that shown in FIG. 4 in that EPROM cells Q9 and Q10 are applied instead of the n-channel type MOS transistors Q3 and Q4 for forming the flip-flop FF. . The match comparison operation in the match comparison circuit shown in FIG. 6 is the same as that in the configuration shown in FIG. 4, but the write operation is different. Therefore, the write operation will be described below.

Writing is enabled by applying a writing high voltage Vpp (for example, 12V) from the address signal DA0 to one node N1 via the n-channel MOS transistor Q5. At this time, the other node N2 is set to the low-potential-side power supply Vss level. As a result, in the erased EPROM cell Q10, the potential of the gate electrode becomes the high voltage Vpp level for writing, the drain electrode becomes the low potential side power source Vss level, electrons are injected into the floating gate by the tunnel phenomenon, and the threshold Vth becomes High level. On the other hand, in the EPROM cell Q9, the gate electrode is set to the low-potential-side power supply Vss level and the drain electrode is set to the writing high voltage Vpp level, and a slight drain disturbance is caused, but the fluctuation of the threshold value Vth is negligible and the low level. It is said that In this way, the redundant address is written.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the redundant remedy by the redundant word line has been described, but the redundant remedy by the redundant data line can be similarly carried out. The device used is an n-channel MO
Either an S transistor or a p-channel type MOS transistor may be used. Furthermore, either positive or negative may be used as the power supply, and the value of the voltage applied to the EPROM cell and the like can be set arbitrarily. Further, by providing a current cutoff MOS transistor in the coincidence comparison circuit so that the current is not consumed except when it is activated, the current consumption of the chip can be reduced. A row address strobe signal RAS * basically indicating the validity of the row address can be basically used as a drive control signal for such a current cutoff MOS transistor. Further, in the above embodiment, the p-channel type MOS transistor is applied as the load MOS transistor in the flip-flop FF, but a high resistance element or an n-channel type MOS transistor can be applied instead. Then, the n-channel type MOS transistor Qds is matched /
The operation of the mismatch detection is activated by the timing signal φds, but as shown in FIG. 2, the match / mismatch detection can be performed even if the MOS transistor Qds is omitted.

In the above description, the invention made by the present inventor is the field of application behind the invention.
Although the case where the present invention is applied to M has been described, the present invention is not limited to the above embodiment, and a static RAM
The present invention can be widely applied to various semiconductor memory devices such as read-only memory and batch erasing type flash memory, and data processing devices including such semiconductor memory devices.

The present invention can be applied on the condition that at least the operation of the redundant circuit includes a non-volatile memory element which is electrically programmable.

[0040]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a nonvolatile memory element capable of programming the operation of the redundant circuit, a flip-flop set based on the redundant address stored in the nonvolatile memory element, and a set state of the flip-flop are Comparing means is formed by including a transistor for enabling bit-by-bit comparison between the redundant address and the input address, and the comparing means is configured by the bit configuration of the input address,
Also, by arranging a plurality of rows in the row and column directions corresponding to the number of redundant repair lines, an efficient layout of the redundant decoder can be achieved, and the chip occupation area can be increased when the number of redundant repair lines is increased. It can be suppressed as much as possible. Also, a plurality of first transistors driven according to the comparison result of the comparison means are arranged corresponding to the comparison means, and the first transistors are connected in series corresponding to the arrangement of the comparison means in the column direction. By connecting, a match signal between the input address and the redundant address can be easily obtained. Further, a plurality of second transistors driven according to the comparison result of the comparison means are arranged corresponding to the comparison means, and the second transistors are arranged in parallel corresponding to the arrangement of the comparison means in the column direction. By connecting, a mismatch signal between the input address and the redundant address can be easily obtained. Then, by obtaining the non-coincidence signal in this way, it is possible to easily match the timings when the redundant word line is selected and when the normal word line is selected.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a configuration example of a redundant decoder included in a DRAM which is an embodiment of the present invention.

FIG. 2 is a circuit diagram of a configuration example of a main part of the redundant decoder.

FIG. 3 is an operation timing chart of the redundant decoder.

FIG. 4 is a circuit diagram of a configuration example of a match comparison circuit included in the redundant decoder.

FIG. 5 is a circuit diagram of another configuration example of the coincidence comparison circuit.

FIG. 6 is a circuit diagram of another configuration example of the coincidence comparison circuit.

FIG. 7 is a circuit diagram of an overall configuration example of the DRAM.

FIG. 8 is a block diagram of a conventional redundant decoder.

FIG. 9 is a circuit diagram of a configuration example of a main part of a conventional redundant decoder.

[Explanation of symbols]

2 Matching Comparison Circuit Group 4 Sense Level Setting Circuit Group 6 Buffer Group 12 Power Supply Detection Circuit 14 Sense Level Setting Circuit 16 Buffer 18 Drive Circuit 51 Redundant Decoder 52 Regular Row Decoder 53 Redundant Memory Cell Array 54 Regular Memory Cell Array 55 Controller 56 Column Decoder 57 Column selection circuit 58 Data input / output circuit 59 Sense amplifiers CAM00 to CAMi-1n-1 Match comparison circuit SA, SA1, SA2 Sense amplifier FF Flip-flop Q1, Q2 p-channel type MOS transistors Q3, Q4, Q5, Q6, Q7, Q8 , Q11, Q12
n-channel type MOS transistors Q9, Q10 EPROM cells QH00 to QHi-1n-1 n-channel type MOS transistors QM00 to QMi-1n-1 p-channel type MOS transistors

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 29/00 G11C 11/401 G11C 15/04

Claims (5)

(57) [Claims] 1. A storing defective addresses, viewing including a redundant circuit for comparing an input address signal, the redundancy circuit, compared with the address signal of the memory and the bitwise of the defective address A plurality of comparison circuits for performing each of the plurality of comparison circuits, each of the plurality of comparison circuits, non-volatile storage means capable of programming the bit unit information of the defective address,
A first circuit for forming complementary address information based on the information programmed in the non-volatile storage means, and the complementary address information output from the first circuit and the bit unit of the address signal are compared and compared. A plurality of comparison circuits are provided in correspondence with the number of bits to be compared in the first direction, and the number of redundant relief lines is provided in the second direction intersecting the first direction. Storage device
And corresponding to each of the comparison circuits arranged in the first direction.
A plurality of first matched comparison transistors, and a program
The defective address and the address signal
A first signal line for transmitting a coincidence signal when
The first match comparison transistor is connected to the first signal line.
Are connected in series and the corresponding comparison result signals are
It is input to the gate and set corresponding to each of the comparison circuits arranged in the first direction.
A plurality of second coincidence comparison transistors, and a program
The above-mentioned defective address and the above-mentioned address signal do not match.
And a second signal line for transmitting a mismatch signal when
And the plurality of second coincidence comparison transistors are
It is connected in parallel to the second signal line, and the corresponding comparison result is
A semiconductor memory device characterized by being input to each gate . 2. The first circuit comprises a first and a second M connected in series between the first potential and the second potential at the first node.
An OS transistor and third and fourth MOs connected in series at the second node between the first potential and the second potential.
An S-transistor and first and second non-volatile storage elements forming the non-volatile storage means, wherein the gates of the first and second MOS transistors are connected to the second node, and the third and fourth MOS transistors are connected. The gate of the transistor is connected to the first node, and the source / drain path of the first nonvolatile memory element is
The source / drain path of the second nonvolatile memory element, which is connected between the first node and the second potential, is
The second node, according to claim 1 Symbol placing the semiconductor memory device, characterized in that it is connected between the second potential. 3. A fifth non-volatile memory element, comprising: fifth and sixth MOS transistors, wherein said first non-volatile memory element is connected to said first node via said fifth MOS transistor.
Of the nonvolatile memory element according to claim 2 Symbol mounting of the semiconductor memory device is characterized in that through the first 6MOS transistor is connected to the second node. 4. The first circuit includes a first MOS transistor and a first non-volatile memory element connected in series at the first node between a first potential and a second potential, the first potential and the first non-volatile memory element. A second MOS transistor and a second nonvolatile memory element connected in series at the second node between two potentials;
Wherein the non-volatile storage means is formed by the first and second non-volatile storage elements, the gates of the first MOS transistor and the second non-volatile storage element are connected to the second node, 2MOS transistor and a gate of the second nonvolatile memory element according to claim 1 Symbol mounting of the semiconductor memory device, characterized in that it is connected to the first node. 5. The plurality of first write transistors having source / drain paths coupled between the first node and a corresponding one of the plurality of first address signal lines, wherein the comparison circuit includes a plurality of first write transistors. Further comprising a plurality of second write transistors having source / drain paths coupled between two nodes and a corresponding one of the plurality of second address signal lines, wherein the plurality of first and second write transistors are , Above first
And when writing the corresponding bits of the defective address in the second nonvolatile memory element, semiconductor memory device of any one of claims 1 to 4, characterized in that it is conductive.