JPS6457491A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6457491A
JPS6457491A JP62212829A JP21282987A JPS6457491A JP S6457491 A JPS6457491 A JP S6457491A JP 62212829 A JP62212829 A JP 62212829A JP 21282987 A JP21282987 A JP 21282987A JP S6457491 A JPS6457491 A JP S6457491A
Authority
JP
Japan
Prior art keywords
delay circuits
timing setting
semiconductor integrated
delay
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62212829A
Other languages
Japanese (ja)
Inventor
Kazunari Kurokawa
Masayuki Hikiba
Mitsuo Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Consumer Electronics Co Ltd
Japan Display Inc
Original Assignee
Hitachi Device Engineering Co Ltd
Hitachi Ltd
Hitachi Consumer Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Device Engineering Co Ltd, Hitachi Ltd, Hitachi Consumer Electronics Co Ltd filed Critical Hitachi Device Engineering Co Ltd
Priority to JP62212829A priority Critical patent/JPS6457491A/en
Publication of JPS6457491A publication Critical patent/JPS6457491A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To control a delay time at every chip, by disposing plural delay circuits selectively brought into an effective state by a fusing means in a timing setting circuit. CONSTITUTION:In a dynamic type RAM, the plural timing setting circuits TG including the delay circuits D1-D5 is disposed, and in the inverse of RAS system timing generating part thereof, the fuse means F1 and F2 are disposed in parallel on the delay circuits D3 and D4. By selectively disconnecting the fusing means F1 and F2, the delay circuits D3 and D4 are selectively brought into the effective state to control a time from the start of the selecting operation of a word line to the start of an amplifying operation by a sense amplifier SA. Thereby, the delay time of the timing setting circuit is controlled at every chip to improve the yield of a semiconductor integrated circuit device.
JP62212829A 1987-08-28 1987-08-28 Semiconductor integrated circuit device Pending JPS6457491A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62212829A JPS6457491A (en) 1987-08-28 1987-08-28 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62212829A JPS6457491A (en) 1987-08-28 1987-08-28 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6457491A true JPS6457491A (en) 1989-03-03

Family

ID=16629050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62212829A Pending JPS6457491A (en) 1987-08-28 1987-08-28 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6457491A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04356789A (en) * 1990-07-17 1992-12-10 Nec Corp Semiconductor memory device
KR100242720B1 (en) * 1996-12-30 2000-02-01 윤종용 Column select control circuit of semiconductor device
KR100403342B1 (en) * 2001-09-13 2003-11-01 주식회사 하이닉스반도체 A timing control circuit of a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04356789A (en) * 1990-07-17 1992-12-10 Nec Corp Semiconductor memory device
KR100242720B1 (en) * 1996-12-30 2000-02-01 윤종용 Column select control circuit of semiconductor device
KR100403342B1 (en) * 2001-09-13 2003-11-01 주식회사 하이닉스반도체 A timing control circuit of a semiconductor device

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