JP2523736B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a high access time.

[Conventional technology]

In recent years, in a highly integrated memory device such as a dynamic MOSRAM, a higher access rate (a time required for reading) has been desired along with higher integration.

FIG. 2 is a diagram showing a simplified example of the concept of a memory cell and a sense amplifier circuit of a conventional semiconductor memory device, in which 1 is a memory cell composed of an n-channel MIS transistor Q ₀ and a capacitor C ₀ , 2 is n channel MI
A first flip-flop type sense amplifier composed of S transistors Q ₁ and Q ₂ , 3 is a second flip-flop type sense amplifier composed of p-channel MIS transistors Q ₃ and Q ₄ , and 4 is an n-type.
First flip-flop activating means comprising a channel MIS transistor Q _5, 5 are p-channel MIS transistor Q ₆
Is a second flip-flop activation means. Also, the n-channel MIS transistor Q ₇ is connected to the bit line BL by ▲.
The transistors for equalizing the potential of ▼ and the n-channel MIS transistors Q ₈ and Q ₉ are the bit line BL and ▲, respectively.
A transistor for precharging ▼ to a predetermined potential (for example, V _CC / 2; V _CC is a power supply voltage), n-channel MIS transistors Q ₁₀ and Q ₁₁ are bit lines BL and ▲ ▼ are I / O, respectively.
This is a transistor for connecting to the O line and ▲ ▼ line (read / write line).

Next, the operation of this conventional example will be described with reference to the timing chart of FIG.

When the signal EQ falls from the high level to the low level at time T ₁ , the equalizing transistor Q ₇ and the precharge transistors Q ₈ and Q ₉ are turned off, so that the bit line BL and ▲ ▼ are in a floating state. When the word line WL changes from low level to high level at time T ₂ , the transistor Q ₀ turns on. For example, when the high level is stored in the memory cell, the level of the bit line BL slightly rises like the solid line. Therefore, at time T _3, when S ₀ changes from the low level to the high level and ₀ changes from the high level to the low level, the transistors Q ₅ and Q ₆ are turned on and the node N ₁ becomes 0V and the node N ₂ becomes V _CC . Then flip-flops 2 and 3 are activated,
The aforementioned slight potential difference generated between the bit line BL and ▲ ▼ is amplified to change BL to V _CC level and ▲ ▼ to 0V. At time T ₄ , the column decoder signal Y changes from low level to high level and the potential difference generated on the bit line is transmitted to the I / O line (which is precharged to, for example, the intermediate potential in advance), and then amplified and output to the outside. A high level output appears at the terminal (not shown). When the low level is stored in the memory cell,
The level of ▼ becomes V _CC and the level of BL becomes 0V. Time T
_When the word line falls from high level to low level at ₅ and the signal EQ becomes high level again at time T ₆ , the equalizing transistor Q ₇ and the precharge transistors Q ₈ and Q ₉ are turned on, and the bit lines BL and ▲ ▼ are set to V Connect to _CC / 2 level internal power supply V _BL .

The above is the outline of the read operation. Regarding the write operation, external write data is applied to the I / O line _in a complementary form (for example, D _in , ▲ ▼) by a write buffer (not shown). Then, when the column decoder signal Y changes from the low level to the high level at time T ₄ , the levels of the I / O line and ▲ ▼ line are transmitted to the bit lines BL and ▲ ▼, which is the reverse of the read operation. At this time, since the word line WL is at the high level, the level of the bit line is transmitted to the memory cell and writing is performed.

[Problems to be solved by the invention]

Since the conventional semiconductor memory device is configured to read and write by using the same I / O bus pair as described above, the bit line pair and the I / O line pair are connected to the transistor Q when reading. Connected via ₁₀ and Q ₁₁ . In order to increase the speed, it is necessary to speed up the connection between the bit line pair and the I / O line pair. However, for example, the rise time of the word line WL
If this bit line pair is connected between T ₂ and the sense start time T ₃ , the load level of the I / O line is added to the bit line, which lowers the read level and may cause malfunction. . That is, when reading and writing are performed using the same I / O bus pair, it is difficult to increase the speed.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor memory device capable of significantly speeding up access time.

[Means for solving problems]

The semiconductor memory device according to the present invention is provided with a read-only data line pair and a write-only data line pair, and the read-only data line pair is one of the current mirror type amplifiers activated by the output of the column decoder. The output node, which is a section of the current mirror type amplifier, is connected to the input gate of the current mirror type amplifier.

[Action]

In the present invention, the current mirror type amplifier immediately amplifies the minute potential difference generated between the bit lines to expand the potential difference between the read data lines.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a simplified concept of a memory cell and a sensor amplifier circuit of a semiconductor memory device according to an embodiment of the present invention. In the figure, 1 is composed of an n-channel MIS transistor Q ₀ and a capacitor C _0. Memory cell 2, 2 is a first flip-flop type sense amplifier composed of n-channel MIS transistors Q ₁ and Q ₂ , 3 is a second flip-flop type sense amplifier composed of p-channel MIS transistors Q ₃ and Q ₄ , and 4 is n first flip-flop activating means comprising a channel MIS transistor Q _5, 5 denotes a second flip-flop activating means comprising a p-channel MIS transistor Q _6. Also, the n-channel MIS transistor Q ₇ is a bit line B
The transistors for equalizing the potentials of L and ▲ ▼, and the n-channel MIS transistors Q ₈ and Q ₉ are precharged to the predetermined potential (for example, V _CC / 2; V _CC is the power supply voltage) on the bit line BL, ▲ ▼, respectively. The n-channel MIS transistors Q ₁₀ and Q ₁₁ are provided for the bit line BL and ▲ respectively.
▼ through IL through n-channel MIS transistors Q ₁₂ , Q ₁₃
This is a transistor for connecting to the line and ▲ ▼ line (write-only data line). n-channel MIS transistor
Q ₁₂ and Q ₁₃ are write control transistors that are turned on during writing. The p-channel MIS transistors Q ₁₄ and Q ₁₅ and the n-channel MIS transistors Q ₁₆ , Q ₁₇ , Q ₁₈ and Q ₁₉ are transistors forming a current mirror type amplifier, and the OL line, ▲
The line (read-only data line) constitutes an internal node (output node) of the current mirror type amplifier. Bit line B is used for the gates of the n-channel MIS transistors Q ₁₆ and Q _17.
L and ▲ ▼ are connected and serve as an input of the current mirror type amplifier. n-channel MIS transistor
A column decoder output signal Y is connected to the gates of Q ₁₈ and Q ₁₉ and is an activation transistor of the current mirror type amplifier.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG.

 First, the read operation will be described.

When the signal EQ falls from the high level to the low level at time T ₁ , the equalizing transistor Q ₇ and the precharge transistors Q ₈ and Q ₉ are turned off, so that the bit line BL and ▲ ▼ are in a floating state. When the word line WL changes from low level to high level at time T ₂ , the transistor Q ₀ turns on. For example, when the data is stored in the memory cell at a high level, the level of the bit line BL slightly rises like a solid line. On the other hand, when the column decoder output Y is changed from low level to high level at time T ₁ , for example, p-channel MIS transistors Q ₁₄ and Q ₁₅ and n-channel MIS transistors Q ₁₆ and Q are generated.
_The current mirror type amplifier consisting of ₁₇ , Q ₁₈ , Q ₁₉ and OL line, ▲ ▼ line is activated. Therefore, at time T ₂ , the word line WL changes from low level to high level and the level of the bit line BL slightly rises, so that the current mirror type amplifier immediately amplifies the potential difference between the read-only data line pair forming its output node. Increase the potential difference. That is, in this example, the ▲ ▼ line is set to low level. After that, the potential difference between the read-only data line pair is further amplified by another amplifier, and a high level output appears at the external output terminal (not shown). Here, since the bit line pair BL, ▲ ▼ and the read-only data line pair OL, ▲ ▼ are not directly connected,
The load capacitance and level of the read-only data line pair OL, ▲ ▼ have no influence on the level of the bit line pair BL, ▲ ▼. In addition, the write-only data line pair IL, ▲ ▼ also has the transistor Q because the write signal W is at the low level during reading.
₁₂ and Q ₁₃ are off, and have no effect on the level of the bit line pair BL, ▲ ▼. That is, the read operation can be performed immediately after the rise of the word line, and the access time can be significantly shortened.

When S ₀ changes from the low level to the high level and S ₀ changes from the high level to the low level at time T ₃ , the transistors Q ₅ and Q ₆ are turned on and the node N ₁ becomes 0V and the node N ₂ becomes V _CC . Then, the flip-flops 2 and 3 are activated, and the bit lines BL and ▲
▼ Amplify the slight potential difference between
To V _CC level and ▲ ▼ to 0V. When the low level is stored in the memory cell, the level of ▲ ▼ becomes V _CC and the level of BL becomes 0 V as shown by the dotted line.
At time T ₅ , the word line drops from high level to low level, and at time T ₆ , the signal EQ becomes high level again, the equalizing transistor Q ₇ and the precharge transistors Q ₈ and Q _{9
Turns on} to connect the bit lines BL and ▲ ▼ equally to the V _CC / 2 level internal power supply V _BL .

The above is the outline of the read operation. Regarding the write operation, external write data is applied to the IL line pair _in a complementary form (for example, D _in , ▲ ▼) by a write buffer (not shown). Since the write signal W is at high level, it is a transistor
Q ₁₂ and Q ₁₃ are on, and when the column decoder signal Y changes from low level to high level at time T ₄ , the IL line and ▲
The level of the ▼ line will be transmitted to the bit lines BL and ▲ ▼. At this time, since the word WL is at the high level, the bit line level is transmitted to the memory cell and writing is performed.

〔The invention's effect〕

As described above, according to the present invention, the read-only data line pair and the write-only data line pair are provided, and the read-only data line pair is a part of the current mirror type amplifier activated by the output of the column decoder. Since a certain output node is configured and the bit line pair is connected to the input gate of the current mirror type amplifier, the read operation can be performed even immediately after the rising of the word line, and the access time can be significantly shortened. The effect is that you can.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a connection of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a connection of a conventional semiconductor memory device, and FIG. 3 is an operation of the conventional semiconductor memory device. FIG. 4 is a timing chart for explaining the operation, and FIG. 4 is a timing chart for explaining the operation of the semiconductor memory device of the present invention. 1 is a memory cell, 2 and 3 are sense amplifiers, and 4 and 5 are flip-flop activation means. The same reference numerals in the drawings indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiro Konishi 4-1-1 Mizuhara, Itami-shi, Hyogo Prefecture, LSE Research Laboratory, Mitsubishi Electric Corporation (72) Takahiro Komatsu 4-1-1 Mizuhara, Itami-shi, Hyogo Prefecture Address Mitsubishi Electric Co., Ltd. LSI Research Laboratory (72) Inventor Yama-saki Hiroyuki 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. LSI Research Laboratory (56) References Special Kai 62-46486 (JP, A) JP 62-183098 (JP, A) JP 62-192997 (JP, A)

Claims (2)

(57) [Claims] 1. A plurality of word lines and a plurality of bit line pairs,
A plurality of memory cells arranged at the intersections of the word lines and the bit lines, a column decoder, and a read-only data line pair and a write-only data line pair commonly provided for the plurality of bit line pairs are provided. In a semiconductor memory device having the same, a current load is commonly connected to the plurality of bit line pairs and is connected to the read-only data line pair, and a current is passed through both read-only data lines of the read-only data line pair. Means and a plurality of bit line pairs are provided corresponding to each of the plurality of bit line pairs, and are connected in series between one read-only data line of the read-only data line pair and a predetermined potential node.
A first activation element whose conduction / non-conduction is controlled based on a column decoder signal corresponding to the corresponding bit line pair output from the column decoder and a potential appearing on one bit line of the corresponding bit line pair. Of the first variable conductance element whose conductance changes in accordance with each of the plurality of bit line pairs and the read-only data line of the read-only data line pair and the predetermined potential node. A second activating element and a corresponding bit line pair, which are connected in series between and are controlled to be conductive / non-conductive based on a corresponding column decoder signal output from the column decoder. The conductance changes according to the potential appearing on the other bit line of the second
And a variable mirror conductance element, and a current mirror type amplifier for amplifying the potential difference appearing on the bit line pair selected by the column decoder and giving it to the read-only data line pair as read data. Semiconductor memory device. 2. The current mirror type amplifier includes at least a first conductivity type first, second, third and fourth MIS transistors and a second conductivity type first and second MIS transistors. The drain of the first MIS transistor of the second conductivity type is connected to the first power supply, the gate and the source thereof are connected to the first output node, and the drain of the second MIS transistor of the second conductivity type is The first power source, the gate is connected to the first output node, the source is connected to the second output node, the drain of the first conductivity type first MIS transistor is connected to the first output node. , The gate is connected to one of the bit line pairs, the source is connected to the first internal node, the drain of the first conductivity type second MIS transistor is to the second output node, and the gate is to the bit line. On the other side of the pair, the source is the second internal node The drain of the third MIS transistor of the first conductivity type is connected to the first internal node, the gate is connected to the output signal of the column decoder, and the source is connected to the second power supply. The drain of the conductivity type fourth MIS transistor is connected to the second internal node, the gate is connected to the output signal of the column decoder, and the source is connected to the second power supply. A semiconductor memory device according to claim 1.