JP2002313083A - Semiconductor memory integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device provided with a memory circuit whose operation speed is accelerated with a simple configuration. SOLUTION: In the memory circuit, in which memory cells are provided at intersections of a plurality of word lines and a plurality of pairs of complementary bit line, the circuit is provided with a pair of common bit line for read operation, a pair of common bit line for write operation, a P-channel MOSFET is provided between the pair of bit line and the pair of common bit line for read operation, and a N channel MOSFET is provided between the pair of bit line and the pair of common bit line for write operation. Then these are switch-controlled based on a Y selection signal in the same way.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology effective for use in a specific semiconductor integrated circuit device having a static RAM (random access memory). is there.

[0002]

2. Description of the Related Art Conventionally, ASICs (Application-Specified Integrated Circuits) have been used.
That is, there is a special purpose IC, in which a memory circuit such as a CPU or a static RAM is mounted. AS
Although it will be understood that ICs generally comprise input / output circuits and logic circuits that are dedicated to a particular application, recent technological advances have focused on a processor including a plurality of central processing units and its surroundings. A more complicated configuration including a circuit and the like is also possible.

[0003]

SUMMARY OF THE INVENTION In developing the SRAM macro for mounting the ASIC, the present inventors have
In order to respond to the demand for higher speed, it has been considered to provide a common bit line for each of read and write in the SRAM.
However, when the read and write common bit lines are provided in this manner, it is necessary to provide corresponding column switches, and the column switches and their selection signals increase, thereby increasing the layout area. Faced.

An object of the present invention is to provide a semiconductor integrated circuit device provided with a memory circuit which has a high speed with a simple configuration. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a memory circuit in which a memory cell is provided at an intersection of a plurality of word lines and a plurality of complementary bit line pairs, a read common bit line pair and a write common bit line pair are provided, A P-channel MOSFET is provided between the pair and the common bit line pair for reading, and an N-channel MOSFET is provided between the pair of bit lines and the common bit line for writing. Switch control based on the

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a block diagram showing one embodiment of a memory circuit mounted on a semiconductor integrated circuit device according to the present invention. Although the memory circuit of this embodiment is not particularly limited, the ASI having a microcomputer function
It constitutes a RAM macro mounted on a C (specific application) integrated circuit.

[0008] X address signal XA, Y address signal YA
Are address buffers XAD each having a latch function.
B, YADB. Address buffer X
The X-system address signal taken into the ADB is applied to the row decoder X.
The Y-system address signal taken into the address buffer YADB is transmitted to the column decoder YDEC.

The memory array section is configured by arranging memory cells MC in a matrix at intersections of word lines and complementary bit line pairs. The memory cell is not particularly limited, but is constituted by a static memory cell including a CMOS latch circuit as described later. In this embodiment, the bit line pair of the memory array section includes the memory cell MC.
In addition, a precharge circuit PC for precharging and equalizing the bit line pair to the same potential is provided.

In this embodiment, a complementary bit line (read) and a complementary common bit line (write) are separately provided in the common bit line pair for speeding up. Among the plurality of bit line pairs of the memory array, the column selection circuit Y
The one selected by S is connected to the two pairs of common bit lines (read and write). Of the common bit line pairs, a read common bit line pair is provided with a sense amplifier SA. The amplification operation of the sense amplifier SA is controlled by the SA activation signal. The output signal of the sense amplifier SA is output from the output terminal DOUT through the output buffer DOB.

The write signal input from the input terminal DIN is transmitted to the input buffer DIB. The output signal of the input buffer is supplied to the write common bit line pair, and transmits the write signal to the bit line pair selected by the column selection circuit YS. Since one memory cell is selected by the word line selection to the bit line pair to which the write signal has been transmitted, the write signal is transmitted to the memory cell.

Although not particularly limited, the external clock signal E
CLK is input to the clock buffer CKG. The clock signal CL formed by the clock buffer CKG
K is supplied to the address buffers XADB, YADB and the like. The control signal R / W is transmitted to the read / write control circuit RWC via the control buffer RWB. The read / write control circuit supplies an activation pulse to the sense amplifier SA during a read operation and an activation signal to the input buffer DIB during a write operation. The control signal RW includes RA / RA in addition to the read / write control signal.
Control signals such as an M macro selection signal (chip selection signal) and an output enable signal may be included.

FIGS. 2 and 3 are circuit diagrams of an embodiment of a memory circuit mounted on a semiconductor integrated circuit device according to the present invention. FIG. 2 shows specific circuits of the memory array, precharge circuit, and column selection circuit (Y selector) of FIG. FIG. 3 shows specific circuits of the precharge circuit, column selection circuit (Y selector), input buffer, amplifier and output buffer of FIG. 2 and 3, the P-channel MOSFET has an N-channel MOSFET by adding a 〇 to its gate.
T is distinguished.

The memory cell is an N-channel type MOSFE
CM consisting of TQ1 and P-channel MOSFET Q2
OS inverter circuit and N-channel MOSFET Q
3 and a CMOS comprising a P-channel MOSFET Q4
The input and output of the inverter circuit are cross-connected to each other to form a CMOS latch. N-channel MOSFETs Q5 and Q6 are provided between a pair of input / output nodes of this CMOS latch circuit and a complementary bit line pair.
The gates of these MOSFETs Q5 and Q6 are connected to a word line. Although not particularly limited, 256 similar memory cells are provided for one complementary bit line. Word lines WD (0) to WD (0) to
A WD (255) is provided.

The precharge circuit is composed of P-channel MOSFETs Q7 and Q8 provided between the power supply voltage terminal VDD indicated by 〇 and the complementary bit line pair, and a P-channel MOSFET provided between the bit line pair. MOSFET Q9
Consists of The gates of these MOSFETs Q7 to Q9 are supplied with a Y select signal (column select signal) YSW (0) via an inverter circuit N1.

The Y selector includes N-channel MOSFETs Q10 and Q11 provided between the complementary bit line pair and the write common bit line pair, the complementary bit line pair and the read common bit line pair. And P-channel type MOSFETs Q12 and Q13 provided between them. The N-channel MOSFETs Q10 and Q
The output signal of the inverter circuit N1 is supplied to the gate of the gate 11 in the same manner as the input of the precharge circuit. The above P
The Y select signal transmitted to the gates of the MOSFETs Q10 and Q11 is inverted and supplied to the gates of the channel type MOSFETs Q12 and Q13 by the inverter circuit N2.

In this embodiment, the common bit line pair is separated for reading and writing as described above. As a result, the common bit line capacity is reduced, and the access time can be shortened. That is, during a read operation, the bit line operates near VDD. In the Y selector, a high level such as the power supply voltage VDD is supplied to the gate of the selected N-channel MOSFET. Therefore,
In the vicinity of VDD, N-channel MOSFETs Q10 and Q10
The voltage applied between the gate and the source 11 becomes small, and the current flowing therethrough becomes very small.

On the other hand, the gate voltages of the selected P-channel MOSFETs Q12 and Q13 are set to a low level such as the ground potential of the circuit by the output signal of the inverter circuit N2. Therefore, the Y selector of the lead
Substantially only a P-channel MOSFET can be used. Due to such an operation of the Y selector, the diffusion capacitance connected to the common bit line (lead) becomes smaller than when a CMOS switch in which a P-channel MOSFET and an N-channel MOSFET are connected in parallel is used for the Y selector during the read operation. The access time can be shortened.

At the time of a write operation, the Y selector functions to extract charges from the bit lines. When the bit line voltage changes from VDD to VSS, the P-channel type MO
Since the current flowing through the SFET is very small, the Y selector at the time of the write operation can be only the N-channel MOSFET Q10 or Q11. As a result, the N-channel MOSFETs Q10 and Q11 can be replaced by a CMOS switch in which a P-channel MOSFET and an N-channel MOSFET are connected in parallel to the Y selector.
, The cycle time can be shortened.

In this embodiment, as described above, only the P-channel MOSFET is used for the Y selector during the read operation, and the N-channel MOSFET is used for the Y selector during the write operation.
Only. During the read operation as described above, the bit line
Since the operation is performed in the vicinity of the DD, even if the write Y selector is selected, the current flowing through the N-channel MOSFET is very small and does not significantly affect the read operation. On the other hand, during the write operation, one of the bit line pairs changes from VDD to VSS in response to the write signal. Therefore, even if the read Y selector is selected, the current flowing through the P-channel MOSFET is very small, and Has no significant effect. Therefore, the Y select signal can be shared and the read and Y selectors can be simultaneously selected. As a result, the number of Y select signals is reduced to half and the number of elements in the control unit is reduced as compared with the case where a CMOS switch circuit is provided for each of the read and write common bit lines. The area can be reduced.

Although not particularly limited, a pair of input terminals of an amplifier (sense amplifier) are provided with a precharge circuit similar to the bit line pair. The precharge operation of this precharge circuit is controlled by a timing signal CDPCG. The amplifier (sense amplifier) uses an N-channel MOSFET for the signal on the common bit line (lead).
Is supplied to the gate. On the source side of this input MOSFET, an N-channel differential M
An OSFET is provided. The sources of these differential MOSFETs are provided with N-channel MOSFETs that receive a sense amplifier activation signal SAK (0) and a sense amplifier activation signal formed in response to the control signal CDPCG.

On the drain side of the input MOSFET,
A P-channel MOSFET is provided. These P
The gate of the channel MOSFET and the gate of the differential MOSFET are shared, and the drain and the output of the input MOSFET are cross-connected to form a latch. The P-channel MOSFET is provided with a P-channel MOSFET for precharging in a parallel form, and precharges the drain output of the input MOSFET to a power supply voltage. The output buffer includes a latch circuit formed by a gate circuit and an output inverter circuit that sends an output signal of the latch circuit to an output terminal OUT.

The input buffer includes a plurality of stages of inverter circuits that receive a write signal input from an input terminal DIN, and an N-channel switch MO that is turned on at the time of a write operation by a read / write control signal RW.
The write signal input through the inverter circuit row through the SFET is taken into the latch circuit. The input signal taken into the latch circuit is a write signal WE
One of the common bit lines (write) is changed from VDD to a low level such as VSS through a write amplifier that is operated.

In this embodiment, although not particularly limited, R
For testing the AM macro, there is provided a test circuit that allows a write signal input from an input buffer by a test signal TEST to be output as it is through the output buffer.

In this embodiment, the read Y selector is constituted by a P-channel MOSFET and the write Y selector is constituted by an N-channel MOSFET as described above.
The Y select signal is common to read and write. By making the Y selector read / write common,
The number of Y select signal lines is reduced by half, and the number of elements of the circuit that generates the Y select signal is reduced. Therefore, the layout area can be reduced.

FIG. 4 is a timing chart for explaining an example of the read operation of the memory circuit according to the present invention. The word line and the Y select signal enter a selected state according to the external clock and the address. A memory cell is selected by these signals. The selected memory cell lowers the potential on one side of the bit line to cause a potential difference on the bit line. The read operation is performed by amplifying the potential difference of the bit line by a sense amplifier which is an operation amplifier circuit.

In such a read operation, the complementary bit line is precharged to the power supply voltage VDD, and one potential of the bit line pair is turned on by the word line selection state.
Q5 (or Q6) and an N-channel MOSFET Q1 (or Q3) that is turned on corresponding to stored information
As a result, one of the pair of bit lines and one of the pair of common bit lines for reading are changed toward the low level depending on the ON state of the P-channel MOSFET constituting the column switch.

As described above, the bit line is connected to a large number of memory cells, so that it has a relatively large parasitic capacitance.
These signals are gradually changed by connecting one of the read common bit lines via a read Y selector made of ET. Since the sense amplifier is a high-sensitivity amplifier, even if the potential difference between the bit line pair and the common bit line pair is small, the read operation can be sufficiently performed in response. That is, at a timing when a voltage difference required for the amplification operation of the sense amplifier is obtained, a read control signal, which is a sense amplifier activation signal, is generated, the sense operation is performed, and a data output signal is formed.

As described above, at the time of reading, the potentials of the bit line pair and the common bit line pair are near the power supply voltage VDD. Therefore, even if the write Y selector is selected, the current flowing through the N-channel MOSFET is very small. The read operation is not greatly affected, and the high-speed operation as described above can be performed. Note that the Y select signal represents an output signal of the inverter circuit N1 in FIG. This is the same in FIG. 5 below.

FIG. 5 is a timing chart for explaining an example of the write operation of the memory circuit according to the present invention. As described above, the word line and the Y select signal are set to the selected state by the external clock and the address. The write operation is performed by writing the write data signal to the selected memory cell via the bit line. In other words, the common bit line (write) and the bit line are connected by a Y selector composed of an N-channel MOSFET, and one of the common bit line and the bit line is connected to a pre-voltage such as VDD in response to a write data signal. The charge potential is changed to a low level such as VSS (0 V).

In the inversion write of the memory cell, the gate voltage of the storage MOSFET Q1 (or Q3) which is turned on is pulled down to a low level corresponding to the low level of the bit line, so that it is turned off. This MOSF
The P-channel MOSFET is turned on by the low level of the gate voltage of the ETQ1 (or Q3), the output signal is changed from the low level to the high level, and the inversion write operation of the memory cell is performed.

As described above, at the time of writing, the P-channel MOSFET Q1 is applied to the low-level potentials of the bit line pair and the common bit line pair that govern the inversion writing.
2 (or Q13) is very small, so the Y selector during the write operation as described above is
Only the OSFET Q10 or Q11 can be used.

The operation and effect obtained from the above embodiment are as follows. (1) In a memory circuit in which memory cells are provided at intersections between a plurality of word lines and a plurality of complementary bit line pairs, a read common bit line pair and a write common bit line pair are provided, A P-channel MOSFET is provided between the bit line pair and the read common bit line pair, and an N-channel MOSFET is provided between the bit line pair and the write common bit line pair. By similarly performing switch control based on the Y selection signal, it is possible to obtain an effect that a memory circuit that achieves high speed with a simple configuration can be obtained.

(2) In addition to the above, a pair of P-channel type Ms for supplying a power supply voltage to the bit line pair, respectively.
An OSFET and a precharge circuit comprising a P-channel type switch MOSFET for short-circuiting the bit line pair are provided. The precharge circuit responds to the Y selection signal when the Y selector is in a non-selection state. A semiconductor integrated circuit device performing a charging operation.

(3) In addition to the above, by transmitting the Y selection signal to the Y selector via the precharge circuit, it is possible to simplify the circuit, and to make the read signal available after the precharge is completed. The effect that the Y selector can be turned on can be obtained.

The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say. For example, the sense amplifier of the memory circuit may be composed of a CMOS latch circuit and a power switch MOSFET that flows the operation current. In order to stably generate a sense amplifier activation signal as quickly as possible, a dummy memory cell in which fixed information is stored is provided, a read signal thereof is monitored, and a sense amplifier activation signal is generated. Is also good. Various embodiments can be adopted for the configuration of the peripheral circuits such as the input buffer and the output buffer.

The memory array section may have a structure in which word lines are hierarchized. That is, the word line may be divided into a main word line and a local word line to which a memory cell is connected, and a plurality of local word lines may be provided in the main word line. The memory circuit according to the present invention includes:
In addition to the RAM macro for the ASIC as described above, the present invention can be widely used for those mounted on various semiconductor integrated circuit devices such as a microcomputer.

[0038]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a memory circuit in which a memory cell is provided at an intersection of a plurality of word lines and a plurality of complementary bit line pairs, a read common bit line pair and a write common bit line pair are provided, A P-channel MOSFET is provided between the pair and the common bit line pair for reading, and an N-channel MOSFET is provided between the pair of bit lines and the common bit line for writing. By performing switch control in the same manner based on the above, it is possible to obtain a memory circuit that achieves high speed with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a memory circuit mounted on a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a partial circuit diagram showing one embodiment of a memory circuit mounted on the semiconductor integrated circuit device according to the present invention.

FIG. 3 is a remaining part circuit diagram showing one embodiment of a memory circuit mounted on the semiconductor integrated circuit device according to the present invention.

FIG. 4 is a timing chart for explaining an example of a read operation of the memory circuit according to the present invention;

FIG. 5 is a timing chart for explaining an example of a write operation of the memory circuit according to the present invention.

[Explanation of symbols]

CKG: clock buffer, XADB, YADB: address buffer, RWB: control buffer, XDEC: row decoder, YDEC: column decoder, MC: memory cell, P
C: precharge circuit, YS: Y selector, SA: sense amplifier, DOB: output buffer, DIN: input buffer, Q1 to Q13: MOSFET,

Continued on the front page. (72) Inventor Kenji Noguchi 5-2-12-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Super-LSI Systems Co., Ltd. (72) Inventor Hitoshi Endo On Kodaira-shi, Tokyo 5-22-1, Mizumotocho Inside Hitachi Ultra-LII Systems Co., Ltd. (72) Inventor Takashi Ikewaki 5-2-2-1, Kamimizu-Honcho, Kodaira-shi, Tokyo Hitachi Ultra-LSE Corporation・ Inside I-Systems (72) Inventor Yayoi Hayashi 5-2-12-1 Kamimizu Honcho, Kodaira-shi, Tokyo In-house Hitachi Cho LSI Systems Inc. (72) Inventor Yoichi Sato Kodaira, Tokyo 5-22-1, Ichijomizuhoncho, Japan Inside Hitachi Ultra-LII Systems Co., Ltd. (72) Inventor Kazuyoshi Sato Hitachi, Ltd. Device Development Center 3-6-1, Shinmachi, Ome-shi, Tokyo F term (reference) 5B015 HH01 HH03 JJ21 JJ36 JJ37 KA33 KB08 RR00

Claims (3)

[Claims] 1. A plurality of word lines, a plurality of bit line pairs, a memory cell provided at an intersection of the word line and the bit line pair, a read common bit line pair, and a write common bit line And a pair of P bits provided between the bit line pair and the read common bit line pair, which are turned on in response to the Y selection signal.
A semiconductor integrated circuit comprising a memory circuit including a channel type MOSFET and a Y selector including an N-channel type MOSFET provided between the bit line pair and the write common bit line pair. apparatus. 2. The precharge circuit according to claim 1, wherein the pair of bit lines includes a pair of P-channel MOSFETs for supplying a power supply voltage, and a P-channel switch MOSFET for short-circuiting the pair of bit lines. A semiconductor integrated circuit device provided with a circuit, wherein the precharge circuit performs a precharge operation in response to the Y selection signal when the Y selector is in a non-selection state. 3. The semiconductor integrated circuit device according to claim 2, wherein the Y selection signal is transmitted to the Y selector via the precharge circuit.