JPS6226690A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To speed up operation by supplying intersectionally complementary signals sent out from two pairs of differential amplifier circuits, to an NPN type transistor and an N channel MOSFET a push-pull form. CONSTITUTION:A address buffer ADB receives address signals A0-A13 supplied from an external terminal and forms internal complementary address signals a0-a13 basing on them. The internal complementary address a0 is constituted of an internal address signal of the same phase with the address signal A0 and an internal address signal phase inverted to the address signal A0. Remaining internal complementary address signals a1-a13 are constituted similarly. A bipolar type transistor is used in the output circuit of the address buffer ADB. Thereby, operation is speed up.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit device, for example, 0MO3 (complementary MO3 > static RAM).
The present invention relates to a technique that is effective for use in a semiconductor memory device configured by incorporating a bipolar transistor into a part of the peripheral circuit of a (random access memory).

[Background technology]

The applicant of this application uses CM OS static type RA
In order to increase the speed of M, we have already developed a RAM that incorporates bipolar transistors into the address buffer, address decoder, and part of the input/output circuit to achieve increased speed. In this RAM, in order to increase the storage capacity and operate at higher speed, a sense amplifier that amplifies the minute read signal from the memory cell and has a large current driving ability has become necessary.

For a CMOS static RAM that uses bipolar transistors as part of it to speed up its operation, see, for example, Japanese Patent Laid-Open No. 56-58193.

(Object of the Invention) An object of the invention is to provide a semiconductor memory device that operates at high speed.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, two pairs of differential amplifier circuits constituted by MOSFET's that cross-receive complementary read signals from memory cells, and complementary output signals sent from these two pairs of differential amplifier circuits are arranged in a bush-pull configuration. The signal is supplied crosswise to an NPN transistor and an N-channel MOSFET to form an output signal.

〔Example〕

FIG. 1 shows a static type RA to which this invention is applicable.
A block diagram of M is shown. This figure shows the internal configuration of a RAM with a storage capacity of approximately 64 bits and an output of 4 bits. In the figure, each circuit section surrounded by a broken line is formed on a single semiconductor substrate such as single crystal silicon using semiconductor integrated circuit technology.

Each static type RAM in this embodiment has 12
It has four matrices (memory arrays M-ARY1 to M-ARY4) with a storage capacity of 8 columns (rows) x 12B rows (columns) = 16384 bits (approximately 16 bits), which makes a total of approximately 64 bits. It has a storage capacity of . An address circuit for selecting a desired memory cell MC from each memory array M-ARY1 to memory array M-ARY4 having a plurality of memory cells MC is as follows:
Address buffer ADB, row address decoder R
-DCR, column address decoder C-DCR, column switches C-3WI to C-3W4, etc.

Although not shown, the memory cells MC have the same configuration.1. Although not particularly limited, a pair of N-channel storage MOSFETs whose gates and drains are cross-connected to each other, an information retention resistor provided at each drain, and a pair of complementary data lines (bit lines) connected to the storage MOSFETs are or digit line)D,
N-channel transmission game installed between D and D)
It is composed of MOSFET. The above memory cell MC
holds stored information by supplying power supply voltage Vcc to the connection point of the resistor. The above-mentioned resistor is set to a high resistance value, for example, several megohms to several gigaohms, in order to reduce the power consumption of the memory cell MC in a state in which stored information is held.

Furthermore, in order to reduce the area occupied by the memory cell, the above-mentioned resistor is, for example, a relatively high-resistance polysilicon layer formed on the surface of the semiconductor substrate forming the MOSFET via a relatively thick field insulating film. It consists of

Signal circuits that handle reading/writing of information are not particularly limited, but include data input ports BDI B 1 to DIB4.
Data output time f@D OB・~DOB4. It is composed of sense amplifiers S A 1 = S A L 6.

The timing circuit for controlling the information read/write operation includes, but is not particularly limited to, an internal control signal generation circuit COM-G E and a sense amplifier selection circuit GS.

The row address selection line (word lines W1 to W128) has 128 lines obtained based on address signals AO-A6.
A decoded output signal according to the row decoder R-DCR is sent out. This decode output signal is transmitted from two memory arrays M-ARYI arranged on the left and right sides of the row address decoder R-DCR, although not particularly limited.
M-ARY2 and memory array MARY3-, M
It is commonly supplied to the word lines W1 to W128 of ARY4.

128 decoded output signals obtained based on address signals A7 to A13 are sent to column-system address selection lines Y1 to Y128 from a column decoder C-DCR. This decoded output signal is not particularly limited, but
Two column switches C-3WI and C- are arranged on the left and right sides of the column address decoder C-DCR.
5W2 and C-3W3. C-, which is commonly supplied to SW4.

Address buffer ADB receives address signals AO to A13 supplied from external terminals and forms internal complementary address signals 10 to 13 based thereon. Note that the internal complementary address signal aQ is composed of an internal address signal aO having the same phase as the address signal AO, and an internal address signal 0 having a phase inverted with respect to the address signal AO. Similarly, the remaining internal complementary address signals A1-a13 are composed of the in-phase internal address signals a1-a13 and the phase-inverted internal address signal al-a13. This address buffer ADB is intended to operate at high speed by using bipolar transistors in its output circuit, although this is not particularly limited.

Of the internal complementary address signals aO-a13 formed by address buffer ADB, although not particularly limited,
Internal complementary address signals 17 to 13 are supplied to column address decoder C-DCR. Column address decoder C-DCR uses these internal complementary address signals
~a13 is decoded, and the selection signal (decoded output signal) obtained by the decoding is sent to the column switch C-3WI ~C-3W4 internal switch MOS F.
ET (insulated gate field effect transistor) Q6゜Q
6~Q7. Supplied to gates such as Q7.

Each memory array M-ARY 1 to memory array M-
Among the word lines Wl-W12B in ARY4, one word line designated by a combination of external address signals AO to A6 is selected by the above-mentioned row address decoder R-DCR, and is selected by the above-mentioned column address decoder C-0CR. Accordingly, a pair of complementary data lines designated by a combination of address signals A7 to A13 from the outside is selected from among 128 pairs of complementary data lines. As a result, each memory array M-ARY1 to M-ARY
-ARY4, each one memory cell MC arranged at the intersection of the selected word line and the selected complementary data line is selected.

Note that, although not particularly limited, the address decoder C-
DCR and R-DCR are designed to operate at high speed by configuring the output section of the logic gate circuit that constitutes them using bipolar transistors.

The storage information read from the selected memory cell MC is stored on four pairs of sub-common complementary data lines CDi, CDI~
CD4. Appears on one of CD4. That is, the subcommon complementary data lines CD1°CDI to CD4. CD4
corresponds to memory blocks M1 to M4 in which 128 pairs of complementary data lines are divided into 32 pairs each, as in the representative memory array MARYI. Sense amplifiers SAI to SA4 are connected to the divided sub-common complementary data lines CD1. CDI~CD4. Each one is provided corresponding to CD4.

In this way, subcommon complementary data lines CDI, CD1 to CD
4. The purpose of dividing into CD4 and providing sense amplifiers SAI to SA4 for each is to divide (reduce) the parasitic capacitance of the common complementary data line and to speed up the information read operation from the memory cell.

The sense amplifier selection circuit GS receives the address signal A12.
．． Based on A13, it is decoded into four combinations to form sense amplifier selection signals m1 to m4.

The above four sense amplifiers SAI to SA4 (SA5 to S
A8, SA9 to 5A12 and 5A13 to 5A16), one sense amplifier corresponding to the complementary data line selected by the column switch receives selection signals m1 to
is put into operation by m4 and timing signal Sac,
The output is transmitted to the common complementary data lines CDL, CDL.

The common complementary data lines CDL, CDL are coupled to the input terminal of the data output circuit DOB and the output terminal of the data input circuit DIB. In the write operation, the divided sub-common complementary data lines CDi, CDI~C
D4. CD4 is connected to transmission gate MOSFET QI, Ql which receives write control signal -+Ve -Q5. Shorted by Q5.

The internal control signal generation circuit COM-GS receives two external control signals CS (chip select signal) and WE (write enable signal) and generates internal chip selection signals csl and sa.
c (sense amplifier operation timing signal), we (write control signal), die (data manual accumulation control signal) and d
oc (data output control signal), etc.

FIG. 2 shows a specific circuit diagram of one embodiment of the sense amplifier SAI. Other sense amplifier S A 2
.about.5A16 are also constituted by a circuit similar to the one-pin amplifier SAI shown in FIG.

The subcommon complementary data lines CD and CD are connected to N-channel 7 line/L/ type differential MOSFETs QI O, Ql 1 and Q.
l6. Cross-coupled to the gate of Ql7.

N-channel MOSFETs QI4 and Q20, which receive the timing signal m1·sac, are provided between the common sources of the differential MOSFETs QIO, Ql1 and Ql6°Ql7 and the ground potential point of the circuit, respectively. The above differential MOSFET Q10. Qll and Ql
6. At the drain of Ql7, there is a P-channel MOSFET Q12, each configured in a current mirror configuration.
, Q13 and Ql8. Ql9 is provided. These P-channel MOSFETQ12. Ql3 and Ql8
．． Ql9 each operates as an active load.

Complementary output signals sent out from the two pairs of differential amplifier circuits are supplied to the next output circuit. The output circuit includes the base of the NPN transistor T1 in push-pull configuration and the N
These are respectively supplied to the gates of channel MOSFETQ15. Also, NPN similarly configured in push-pull configuration
) Base of transistor T2 and N-channel MOSFE
Complementary output signals sent out from the two pairs of differential amplifier circuits are cross-supplied to the gate of TQ21. In other words, the base of transistor T1 and MOSFETQ
Gate number 21 is the differential Mo5FETQI O,Q
The output signal from the differential MOSFET Q16 and Q17 is commonly supplied to the base of the transistor T2 and the gate of the MOSFET Q15.

As a result, the transistor T1 and MOSFET Q15 and the transistor T2 and MOSFET Q21 are operated in a complementary manner, and complementary output signals are transmitted from their respective connection points to the common complementary data lines CDL and CDL.

The common complementary data lines CDL, CDL connect the output terminals of a total of four sense amplifiers SAI to SA4, the output terminal of one data input buffer DIBI, and the data output buffer DOB1 of 1[1. Therefore, the common complementary data lines CDL and CDL have a relatively large parasitic capacitance due to the gate capacitance and junction capacitance of the circuit elements constituting each of the circuits mentioned above being added to the capacitance of the wiring itself. be done. In this embodiment, an NPN transistor Tl with large current supply capacity is used.
, T2 complementarily charges up the common complementary data lines CDL and CDL, which have parasitic capacitances as described above, to a high level.
The read signal can be sent out much faster than when using ET.

FIG. 3 shows an N-channel MOSFET (NMO3) and a P-channel MOSFET that constitute the sense amplifier SAI.
A schematic cross-sectional view of the structure of an OSFET (PMO3) and a bipolar transistor (Tl, T2) is shown.

In this embodiment, a P-type semiconductor substrate 1 is used, and the following semiconductor layers and the like are formed on its surface by a known semiconductor integrated circuit manufacturing method.

So-called N is selectively applied to the element formation region on the surface of the substrate 10.
+Collector buried layer 2 is formed. N'''' is applied to the surface of the substrate 1 including the collector buried layer 2.

An epitaxially grown layer is formed, and this epitaxially grown layer is electrically isolated from each other by a P element isolation region 4 as device forming regions 3a and 3b.

In the element formation region 3a, there are sense amplifiers SAI and other C
N-channel MOSFET (N
MO3) and a P-channel MOSFET (PMOS) are formed. N-channel MOSFET (NMO3)
is an N-type source S formed in a P-type semiconductor region constituting a well region.

It consists of a drain D region and a gate electrode G formed on the surface of this semiconductor substrate with a gate insulating film interposed therebetween. A P-channel MOSFET (PMOS) is composed of P1 type source S and drain D regions formed in the element formation region 3a, and a gate electrode G formed on the surface of the semiconductor substrate with a gate insulating film interposed therebetween. Ru.

Since the collectors of the transistors T1 and T2 are commonly supplied with the power supply voltage Vcc, they are formed in common in the element formation region 3b. That is, this element formation region 3b is
The P-type regions forming the collector regions of both transistors TI and T2 and formed in the element forming region 3b respectively constitute the base B, and the N" formed in the P-type head region constitutes the base B.
The mold region constitutes an emitter E. Note that the N4 type region formed in this element forming region 3b constitutes an ohmic contact region of the collector C.

In this embodiment, as in the above embodiment, a MOSFET and a bipolar transistor can be formed on the same semiconductor substrate using the same manufacturing technology as the known method for manufacturing bipolar semiconductor integrated circuit devices. can.

〔effect〕

(1) A small complementary signal read out from the memory cell,
Complementary output signals formed by two pairs of differential amplifier circuits formed by MOSFETs are
By supplying the signal crosswise to two pairs of push-pull output circuits each consisting of a channel MOSFET, it is possible to drive a common complementary data line having a relatively large parasitic capacitance value at high speed.

(2) According to the above (1), a sense amplifier having a large current amplification gain can be constructed, so that the signal read from the memory cell can be outputted at a sufficiently high speed even if it is a very small signal.

Therefore, since the elements constituting the memory cells can be miniaturized and a large number of memory cells can be connected to a common data line, it is possible to achieve the effect of increasing the storage capacity while increasing the operation speed.

(3) By configuring the sense amplifier output circuit by a combination of an NPN l-transistor and an N-channel MOS FET, MOSFETs and transistors can be formed using known bipolar transistor manufacturing technology, and the transistor By being able to form both elements in the same element form region, it is possible to achieve the effect of achieving a high degree of integration.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples (although it is understood that various changes can be made without deviating from the gist of the invention). Needless to say, for example, when a plurality of sense amplifiers are coupled to the common complementary data lines CDL and CDL as shown in FIG.
In other words, transistors Tl, T2 and MOS
FETQ15. In order to turn off Q21, a MOSFET is connected between the output of the differential amplifier circuit and the ground potential point of the circuit, which is turned on when it is in an inactive state.
may also be provided. Further, the subcommon complementary data line may be omitted, and the input terminal of the sense amplifier may be coupled to the complementary data line to which the memory cell is coupled. In this case, a substantial column selection operation may be performed by selective operation of the sense amplifier. Memory cell MC is a P-channel MOSFE instead of a resistor.
A CMOS flip-flop circuit using T may also be used.

Furthermore, the specific circuit configurations of other peripheral circuits constituting the static RAM can take various embodiments.

[Application field]

The present invention can be widely used in semiconductor memory devices such as static RAM.

[Brief explanation of the drawing]

FIG. 1 shows a static type R showing an embodiment of the present invention.
A block diagram of AM, FIG. 2 is a specific circuit diagram showing one embodiment of the sense amplifier, and FIG. 3 is a schematic cross-sectional view of the structure of MOSFETs and bipolar transistors constituting the sense amplifier and the like.

Claims (1)

[Scope of Claims] 1. Two pairs of differential amplifier circuits configured by MOSFETs that receive complementary read signals from memory cells crosswise, and the output signals of the two pairs of differential amplifier circuits are respectively supplied to the base. and an N-channel MOSFE provided on the emitter side of the NPN transistor and to which the output signal of the differential amplifier circuit is cross-supplied.
1. A semiconductor memory device comprising: a sense amplifier that transmits a complementary output signal from a connection point between the NPN transistor and an N-channel MOSFET provided correspondingly thereto; 2. The differential amplifier circuit is an N-channel M in a differential configuration.
N is provided between the OSFET, its common source and the ground potential point of the circuit, and receives an operation timing signal.
Claims characterized in that it is constituted by a channel type MOSFET and a P channel type load MOSFET which is provided at the drain of the differential type N channel MOSFET and is configured as a current mirror. 2. The semiconductor memory device according to item 1. 3. The semiconductor memory device according to claim 1 or 2, wherein the memory cell is a static type memory cell.