JPS6028096A - Static ram - Google Patents

Abstract

PURPOSE:To attain a large memory capacity with high-speed operation and small power consumption by constituting a memory cell with a latch circuit and using a differential bipolar FET to a sense amplifier. CONSTITUTION:The memory cell MC consists of memory MOSFETQ1 and Q2 where a gate and a drain are formed alternately into a latch form and high resistances R1 and R2 made of polysilicon layers. While a sense amplifier consists of differential bipolar transistors TRT5 and T6. Then the memory cell reading voltages emerging at common data lines CD and -CD are supplied to the bases of the TRT5 and T6. The collector outputs of the TRT5 and T6 are transmitted to a data output buffer DOB through emitter follower TRT7 and T8.

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to a static RAM (random access memory), for example, a MOSFET.
The present invention relates to a technology that is effective for increasing the speed of a device in which a latch circuit constructed using an insulated gate field effect transistor (insulated gate field effect transistor) is used as a memory cell.

[Background technology]

For high-speed reading of a memory cell composed of MOSFETs, a device using a bipolar transistor as an amplification element has been proposed in Japanese Patent Laid-Open No. 56-58193. This readout circuit is shown in FIG. In this method, bipolar transistors TI and T2 are used as a column switch circuit, and a current is supplied to a selected memory cell through this column switch circuit to obtain a read signal from the selected memory cell. If MO3FETQI is on, this MO
3FETQI and transmission gate 1- installed on the data line side
Current flows through M03FETQ3. By passing this through resistor RLI, a low level readout signal is obtained. On the other hand, on the data line side, MO3FE
Since no current flows due to the off state of TQ2, the resistance RL
A high level read signal is obtained from 2.

The inventor of the present application has revealed that such a sense amplifier has the following drawbacks. That is, the current value of the read current is the MO5 of the memory cell.
It cannot be increased because it is determined by the conductance characteristics of FETQI, Q3 (Q2, Q4). This is because in order to increase the current value, the element size must be increased, but the element size of the memory cell cannot be increased in order to increase the storage capacity.

Therefore, even though bipolar type L transistors are used, the read operation cannot be made very fast. In addition, since the column switch circuit is configured with bipolar transistors, the output signal of the column address decoder circuit (
Setting the selection/non-selection) level becomes difficult.

[Purpose of the invention]

An object of the present invention is to provide a new static type RAM with a large storage capacity and high speed operation.

Another object of the present invention is to provide a new static RAM that achieves low power consumption and high-speed operation.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, high-speed reading is achieved by constructing a memory cell using a latch circuit constructed of MOS FETs and using a differential bipolar transistor as a sense amplifier that amplifies the read level.

[Embodiment 1] FIG. 2 shows a circuit diagram of an embodiment of the present invention. Although not particularly limited, the RAM shown in the figure is formed on a semiconductor substrate, such as a single silicon crystal, by known bibold (Bi) and OMO3 (complementary MO3) integrated circuit (IC) technology. Terminals Ax, Ay, Di
n, Dout, WE and ε balls are its external terminals. Note that the power supply terminal is omitted in the figure, and a negative voltage -VDD is used, although this is not particularly limited.

One specific circuit of memory cell MC is shown as a representative, and the gate and drain are cross-connected (
Latched form) memory (drive) MO3FETQI,Q
2 and the above MO3FETQI.

Between the drain of Q2 and the ground potential point of the circuit, there is a high resistance R formed of a polysilicon layer for information retention.
1 and R2 are provided. And the above MO3FET
A transmission gate) MO3FETQ3. is connected between the common connection point of QI and Q2 and the complementary data lines DO and DO. Q4 is provided. Other memory cells MC also have similar circuit configurations. These memory cells are arranged in a matrix. Transmission gate type MO3FETQ3 of memory cells arranged in the same row. Gates such as Q4 are commonly connected to corresponding word lines W1 and W2, respectively,
The input/output terminals of memory cells arranged in the same column are connected to a corresponding pair of complementary data lines (or bit lines) DO.
, Do and DI, connected to DI.

In the memory cell MC, in order to reduce power consumption, the resistor R1 is set to a level that allows the gate voltage of MOS FETQ2 to be maintained above the threshold voltage when MO3FETQ1 is turned off. It is made to have a high resistance value. Similarly, the resistor R2 is also made to have a high resistance value.

In other words, the resistor R1 has enough current supply capability to prevent the information charges stored in the gate capacitance (not shown) of the MO3FET Q2 from being discharged due to the drain leakage current of the MO3FET QI.

According to this embodiment, although the memory array is manufactured by CMO5-IC technology, the memory cells MC are composed of n-channel MO3FETs and polysilicon resistance elements as described above. Compared to the case where a p-channel MOSFET is used in place of the polysilicon resistance element, the size of the memory cell and memory array can be made smaller. That is, when a polysilicon resistor is used, it can be formed integrally with the gate electrode of the drive MO3FET QI or G2, and its size can be reduced. Further, unlike when p-channel MO3FETs are used, there is no need to separate them from the driving MO5FETs QI and Q2 by a relatively large distance, so no wasted blank space is generated.

In the figure, the word line W1 is connected to the X address decoder
- Drive circuit DVI that receives the selection signal formed by DCR
selected by The same applies to the other word line W2.

The X-address decoder X-DCR is composed of mutually similar NOR gate circuits Gl, G2, etc. The inputs of these NOR gate circuits Gl, 02, etc. receive an external address signal A supplied from an appropriate circuit device (not shown).
Internal complementary address signals processed by the X address buffer X-ADB receiving x are applied in a predetermined combination.

The pair of data lines DO1Do and DI, DI in the memory array are each connected to a transmission gate MO3FETQ9 . It is connected to common data lines CD and CD via a column switch circuit composed of QIO, Qll, and G12. The input terminal of the read circuit R and the output terminal of the write circuit W are connected to the common data IfilCD, CD. The output terminal of the readout circuit R is the data output terminal Dou.
A read signal is sent to the input terminal t, and a write data signal supplied from the data input terminal Din is applied to the input terminal of the write circuit W.

MO5FETQ9 that constitutes the above column switch circuit.
The gates of QIO, Qll, and G12 each receive selection signals qY1. Y2 is supplied. This Y-address decoder Y-DCR is composed of mutually similar NOR gate circuits G3, G04, etc. These NOR gate circuits G3. A predetermined combination of internal offset address signals processed by a Y address buffer Y-ADB receiving an external address signal Ay supplied from an appropriate circuit device (not shown) is applied to the input of G4.

The control circuit CON receives control signals from external terminals WE and C3 and forms an internal control timing signal.

In this embodiment, although not particularly limited, when the chip is not selected, any one of the negative ij MO3FETQ5 etc. of the data line is connected.
Memory cell M connected to one selected word line
In order to prevent direct current from flowing through the transmission gate MO5FETQ3 etc. of C and the memory MO3FETQ1 etc. which are in the on state, the above-mentioned X address decoder X-DC
All word lines are set to a non-selected state by the high level of the non-selected internal chip selection signal crystal formed by the control circuit CON at the inputs of the NOR gate circuits G1, 02, etc. constituting R.

FIG. 3 shows a circuit diagram of one embodiment of the sense amplifier constituting the readout circuit.

In this embodiment, a differential bipolar transistor T5. T6 is used. That is, the common data lines CD, CD
The read voltage of the memory cell appearing at the differential transistor T5. Supplied to the base of T6. These differential transistors T5. The common emitter of T6 is provided with MO3FETQI3 which receives the operation timing signal φpa. Further, the differential transistor T5. Load resistors R3 and R4 are provided at the collector of T6, respectively.

The collector outputs of these differential transistors T5, T6 are connected to emitter follower transistors T7, . It is transmitted to the data output buffer DOB through T8. Although not particularly limited, the emitter follower transistor T7
．． By providing T8, the output signal of the sense amplifier is brought to ECL (emitter coupled logic) level. Therefore, the data output buffer is constituted by an ECL circuit.

[Embodiment 2] FIG. 4 shows a circuit diagram of a readout circuit showing another embodiment.

In the readout circuit shown in the figure, a column decoder function is added to the sense amplifier. That is, the second. M as shown in Figure 3
If the memory cell read signal is obtained through a column switch circuit composed of OSFETs,
The read signal supplied to the sense amplifier is delayed accordingly.

Therefore, in this embodiment, the differential transistors T9. T.I.
O, Tll, and T12 are provided, respectively. Similar differential transistors are also provided for the other complementary data line pairs. MO3FETQI provided at the common emitter of each differential transistor 4. The selection signals Yl and Y2 formed by the Y address decoder circuit are supplied to the gate of Ql5. Also, the differential transistors T9 provided in each column. TIO and corresponding transistors T9.Tll, T12, etc. Tll and TIO, T12
The collectors of transistors TI3. T
14 emitters. These transistors T
13. The base of T14 has a write enable signal -7.
1 is supplied.

Further, each emitter is provided with a constant current source, and the collector is provided with a load resistance R.5. R6 is provided respectively. The collector outputs of these transistors T13, T14 are connected to emitter follower transistors T15. Tl(i through data output buffer DOB
can be conveyed to.

The operation of this embodiment circuit is such that during a read operation, the write enable signal W1 becomes high level, so that the transistors T13. Tl-4 is in operation. and,
MO3FETQI4 of the sense amplifier of the selected column, for example, data line Do, Do is at that! /S decoder output signal Y1 turns on state, so a current according to the read signal from the selected memory cell in that column flows through the transistors T13. Load resistance R5, R6 through T14
flows to On the other hand, M of the sense amplifier in the unselected column
O3FF, TQ15, etc. are turned off by their address decoder output signal Y2, etc. Therefore, no current flows through the differential transistor. Thereby, a read signal according to the selected memory cell is obtained.

Further, when the write enable signal 71 is set to low level during a write operation, the transistor T13 is
．． , T14 are turned off. As a result, no write signal is output on the data line. In addition, transistor T13. The T140 base potential may be clamped at a reference potential. In this case, the write enable signal is applied to the data output buffer DOB so as not to output the write signal on the data line.

〔effect〕

(Since a differential transistor composed of 11 bipolar transistors is used, only a small current according to the inverse ratio of the current amplification factor flows through the data line.In other words, by reducing the cell size of the memory cell, Even if the current drive capability is reduced, the operating current of the sense amplifier (M
By increasing the current flowing through the O3FETs Q13 to Q15, etc., it is possible to achieve the effect of realizing a high-speed read operation.

(2) According to (11) above, the elements constituting the memory cell can be miniaturized, so it is possible to achieve the effect of realizing high-speed reading while realizing a large storage capacity.

(3) By providing a sense amplifier using a differential I transistor composed of bipolar transistors for each data line pair and controlling its operating current circuit with a column address decoder output signal, the memory cell can be connected to a sense amplifier. Since the read signal transmitted to the device can be made faster, it is possible to achieve the effect of further increasing the read speed.

(4) By providing the sense amplifier with an address decoder function, it is possible to achieve the effect of realizing the high-speed readout described in (3) above with a relatively simple circuit configuration.

(5) By using the readout circuit R consisting of a sense amplifier and data output buffer as an ECL circuit made up of bipolar transistors, it is possible to achieve higher readout speed and to make it compatible with ECL semiconductor integrated circuit devices, so its application The effect is that it is possible to increase the number of people. In other words, although the static RAM of this embodiment is slower than the ECLC static RAM, it is significantly faster than the MOS static RAM, and is a new static RAM that achieves large storage capacity and low power consumption. It can be used as.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, instead of the above-mentioned information holding resistor, the memory cell may be a p-channel MO3F
It may also be one that uses ET. In addition, the above CMO3
Instead of the circuit, it may be configured with either an n-channel MOSFET or a p-channel MOSFET. Further, the specific circuit configuration and timing control of the peripheral circuit can take various embodiments.

Furthermore, the embodiment shown in FIG. 3 and the embodiment shown in FIG. 4 may be combined. That is, the common data line shown in FIG. 3 may be divided and a sense amplifier having an address decoder function as shown in FIG. 4 may be provided for each of the lines, resulting in a two-stage address decoding configuration.

In addition, the data output buffer DOB is a CMOS circuit or a TTL () transistor transistor logic...
・ri) etc. may be used.

[Application field]

This invention can be widely used as a static RAM.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the prior art, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram showing an embodiment of the readout circuit in FIG. FIG. 4 is a circuit diagram showing another embodiment of the readout circuit in FIG. 2. X-ADB...X address buffer, Y-ADB...Y
Address buffer, X-DCR...X address decoder, Y-DCR...X address decoder, MC...memory cell, W...write circuit, R...read circuit, DOB
...Data output buffer, CON...Control circuit patent attorney Akio Takahashi Figure 1

Claims (1)

[Claims] 1. As a sense amplifier for amplifying a read signal of a memory array including memory cells using a launch circuit composed of MOSFETs, the amplifying element thereof is composed of differential bipolar transistors. Characteristic static type RAM. 2. The common emitter of the above-mentioned differential type bipolar transistor is a MOSFET that receives an operation timing signal.
The static type RAM according to claim 1, characterized in that the static RAM is provided with:. 3. The operation timing signal is a column address decoder output signal, and the collector of the differential bipolar transistor is shared with the corresponding collector of the differential bipolar transistor provided in another column. A static type RAM according to claim 2, characterized in that the static RAM is: 4. The data output buffer 7 circuit that amplifies the output signal of the sense amplifier and sends out a read output signal, and the data manual buffer that supplies a write signal to the memory array are configured by ECL circuits. A static RAM according to claim 1, 2, or 3.