JPS6235191B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Field of Application of the Invention The present invention relates to semiconductor memories, particularly insulated gate field effect transistors (hereinafter referred to as MOS transistors).
The present invention relates to a static random access memory (static RAM) constructed using the static random access memory (static RAM).

(2) Prior Art Random access memory (RAM) is a memory that can temporarily store necessary information and read it when necessary, and is called a read/write memory. RAM is configured to control the operations of memory cells that store information arranged in a matrix, address circuits that select specific memory cells from the outside, and signal processing circuits that read and write information. A specific memory cell is selected by specifying the intersection of a matrix.

As RAM memory cells, memory cells made of MOS transistors (MOS memory cells) have become popular because they have excellent features such as high integration, low power consumption, and low cost. MOS memory cells are broadly divided into static type and dynamic type, and each type is used depending on the purpose.

FIG. 1 shows a typical static MOS memory cell consisting of four MOS transistors and two load resistors. In this memory cell, information is transmitted through drive MOS transistors T ₁ and T ₂ and load resistance.
It is stored in a flip-flop circuit consisting of R ₁ and R ₂ . T ₃ and T ₄ are transfer transistors for reading or writing information in the flip-flop circuit, and reading and writing are performed via these MOS transistors. In the flip-flop circuit shown in Figure 1, _T2 is in the on state,
When T ₁ is in the off state, the drain of T ₂ becomes a low level potential (“0” state almost zero potential), and the gate of T ₁ and the drain of T ₄ are also kept at a low level potential. Since the gate potential of T ₁ is at a low level, it maintains an off state, and its drain potential becomes a high level (“1” state, approximately the power supply voltage V _DD ), and in this state, current flows through T ₁ . Zuko's flip-flop becomes stable.

When reading information from this memory cell, for example, a high voltage pulse voltage is applied to the load line W.
By opening the gates of T ₃ and T ₄ , the potential state of the flip-flop circuit passes through T ₃ and T ₄ and appears on the data line D as a signal with a minute potential difference.
This potential state is amplified by an externally provided readout amplifier and taken out as an output signal. To write information into this memory cell, a pulse voltage is applied to either the word line W or the data line D.

In the above memory cell, N-channel MOS
Using a transistor, V _DD is the positive voltage supply, V _SS is the load voltage supply, and the P channel
When using a MOS transistor, the voltage polarity is reversed. In addition, in either case of N channel or P channel, it is also possible to use one power supply type by setting V _SS to the ground potential.

Note that MOS transistors can also be used as the load resistors R ₁ and R ₂ .

In addition to the above MOS memory cells, complementary type
A flip-flop memory cell using a MOS circuit (CMOS circuit) is also known.

Summary of the Invention A data system circuit including memory cells of a conventional MOS static RAM is as shown in FIG. Here, 1 to 4 are 50, 52, 54, 5
Transfer MOS transistors 6, 58, 60, 62, 64 and 51, 53, 55, 57, 59,
This is the aforementioned MOS memory cell consisting of drive MOS transistors 61, 63, and 65 and a current supply resistor R. 12-15 are data lines 16-
Bias MOS to keep 19 at a constant potential
Transistors 22 and 23 are for biasing the common data lines 9 and 10 to a constant potential.
It is a MOS transistor. 70 to 73 are switching MOS transistors for transferring signals on the data line to the common data line, and gate terminals 7 and 8 thereof are connected to a Y decoder (column selection decoder). Word lines 5 and 6 are used to select X-system memory cells and are connected to an X decoder (row selection decoder).

Next, the operation of the MOS static RAM shown in FIG. 2 will be described. Here, the explanation will be given on the case where all the MOS transistors in FIG. 2 are constructed using N-channel MOS transistors. However, even when configured using P-channel MOS transistors, the same explanation can be given by reversing the voltage polarity.

For example, if the potentials of 5 and 8 are high and the potentials of 6 and 7 are low, memory cell 2 is selected and its information is transferred from 18 and 19 to 9 and 10,
The signal is sent to the sense amplifier 20 and output from the output buffer 21 to the outside of the chip.

FIG. 3 shows operating waveforms when storage nodes C, D and data lines 18, 19 of memory cell 4 in FIG. 2 are in a selected state (8 is high level). In the figure, "0" is stored in A of cell 2, "1" is stored in B, "1" is stored in C of cell 4, and "0" is stored in D, and after reading of cell 2 is completed, cell 4 is read. That is, this is a case where inversion reading is performed, which corresponds to the worst case of the reading state.

On the other hand, in FIG. 2, the memory in the non-selected state (7 is low level and 70 and 71 are OFF state)
Cells 1 and 3 operate similarly to cells 2 and 4 as word lines 5 and 6 are selected. FIG. 4 shows the storage nodes G and H of the unselected cell 3 and the data line 16,
This figure shows the operation waveforms of No. 17, and shows the case where inverted reading of information is performed in the same way as in Fig. 3 (F,
"1" in G, "0" in E and H). Comparing FIG. 3 and FIG. 4, it is found that in FIG. 4, that is, in the operation of non-selected cells, the potential difference between data lines is larger, and the potential difference between storage nodes immediately after selection is smaller.
The reason for this is that in the case of the selected cell, 8 is at a high level and the switch MOS transistors 72 and 73 are in the ON state, and the data lines 18 and 19 and the common data lines 9 and 10 are in a conductive state.
This is because the transistors 22 and 23 act as loads for the cells 2 and 4, and the potential difference between the data lines 18 and 19 is small, so there is no fear that the information in the memory cell 4 will be inverted. On the other hand, in the case of unselected cells 1 and 3, the load is only 12 and 13, so when the word line 5 is at a high level, the current flowing through 50 and 51 creates a large potential difference between the data lines 16 and 17. When the memory cell 3 storing the inverted information is subsequently read out, as shown in FIG. 4, the potential difference between the storage nodes becomes small and process variations occur.
Depending on the degree of overlap between the waveforms of the word lines 5 and 6, the information may be reversed.

For example, depending on the degree of process variation (threshold voltage, processing dimensions, etc.), word lines 5 and 6 may be
The waveforms of cells 1 and 6 in FIG. A case arises where 3 are similarly selected (referred to as multiple selection). In this case, the data line 16 is pulled to a low level because 50 and 51 are in the ON state, and a large potential difference is maintained between the data lines 16 and 17. At this time, when 6 becomes high level and cell 3 is selected, the high level potential stored in G decreases because 50 and 51 of cell 1 are conductive, and the potential difference between G and H is The potential difference becomes even smaller than the potential difference shown in FIG. 4, and eventually the information is reversed. These phenomena are problems that can be avoided if the potential difference during reading between the data lines 16 and 17 is small.

(3) Purpose of the Invention The present invention improves the above-mentioned drawbacks of the prior art and provides a method that eliminates the risk of information inversion in unselected memory cells.
The purpose is to provide MOS static RAM.

That is, an object of the present invention is to provide a semiconductor memory which is a MOS static RAM having a high operating margin and reliability.

(4) Examples Hereinafter, the present invention will be explained in detail with reference to examples.

FIG. 5 is a diagram showing a first embodiment of the present invention, and shows a data output system circuit of a static RAM whose memory cells are composed of N-channel MOS transistors. In FIG. 5, 70 to 73 are N-channel MOS transistors for column selection switches, and 101 to 104 are N-channel MOS transistors that serve as loads for non-selected memory cells during reading.
In the MOS transistor, signals having opposite phases to terminals 7 and 8 are input to terminals 105 and 106, respectively. Further, 22 and 23 are N-channel MOS transistors for biasing the common data lines 9 and 10. N-channel MOS transistors for biasing data lines 16-19 are also necessary, although not shown here.

The effects of the present invention shown in FIG. 5 are as follows. In other words, if 7 is a low level and 3 is a non-selected cell, the same explanation as in FIG. 4 is given.
Terminal 105 goes high and transistor 10
1,102 becomes conductive and loads the memory cell. As a result, as shown in FIG. 6, the potential difference between the data lines 16 and 17 and the storage nodes G,
The potential difference between H is for the selected memory cell (third
Figure).

As described above, according to the present invention, the operating margin of memory cells can be dramatically improved, and a static RAM with high reliability can be obtained.

Here, “memory cell operating margin” is
For example, it refers to the potential difference during non-selective reading between storage nodes E, F or G, H of the memory cell shown in FIG. This potential difference is 2V from various experimental results.
The above value is desirable; under this condition, even if multiple selection occurs, the information in the memory cell will not be inverted. The ideal storage node potential during reading is such that a low level is a potential below the threshold voltage of the driving MOS transistors (eg, 59, 61, etc.), and a high level is the power supply voltage level (V _CC ).

FIG. 7 shows a block diagram of the configuration of the semiconductor memory (static type MOS, RAM) of the present invention including peripheral circuits. In FIG. 7, 702 is a memory matrix in which memory cells 701 are arranged in a matrix, 703 is a medecoder that selects a row in the matrix, 704 is a Y decoder that selects a column in the matrix, and 705 is a Y decoder signal. A column selection circuit for selecting a data line; 706 is a data line load circuit; 707 is a data line load circuit controlled by an inverted signal of a selection signal from a Y decoder. Further, in FIG. 7, 708 is a data input terminal D _IN , 709 is a data input circuit, and 71
0 is a sense amplifier, 711 is an output buffer circuit,
712 is a data output terminal D ₀ , 713 is an address input terminal, 714 is an address buffer circuit, 71
5 is a chip select signal terminal CS, 716 is a write enable signal terminal WE, 717 is an inverter, 718 is a word line, 719 and 720 are data lines, 720 and 721 are NAND circuits, and 722 is a common data line bias MOS transistor. be.

Figure 7 shows an asynchronous static MOS.
RAM is shown, but synchronous static MOS
The present invention can be similarly applied to RAM.

FIG. 8 is a diagram showing a second embodiment of the present invention, and shows a data output system circuit of a MOS static RAM whose memory cells are composed of N-channel MOS transistors. Here, 110 to 113
is a P-channel MOS transistor, 22,2
3,70 to 73,114,115 are N channels
It is a MOS transistor. In this example,
Although the bias load on the data line is omitted, it goes without saying that it is necessary. transistor 1
Signals 7 and 8 are input to gates 10 to 113. When 7 is low level and memory cell 3 is not selected, 110 and 111 are conductive, and when 8 is high level and cell 4 is selected, 112 and 113 are nonconductive, and the operation is the same as the first embodiment. It's the same. According to this embodiment, as compared to the first embodiment, it is possible to eliminate variations in the voltages of the data lines 16 and 17 due to variations in the threshold voltages of the N-channel MOS transistors. Since only one signal line is required, the layout is easy and the area occupied by the circuit is reduced. You can get this big advantage.

In each of the above embodiments, N-channel MOS
Even if the transistor is a P-channel MOS transistor and the P-channel MOS transistor is changed to an N-channel MOS transistor, the present invention can be realized by changing the voltage polarity.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a typical memory cell of a MOS static RAM, Fig. 2 is a schematic circuit diagram showing a data output system circuit including memory cells of a conventional MOS static RAM, and Fig. 3 is a circuit diagram showing a typical memory cell of a MOS static RAM. Storage nodes C, D of selected cell 4 and data line 18,
19, FIG. 4 shows the storage nodes G and H of the non-selected cell 3 and the data line 1 in FIG.
6 and 17, and FIG. 5 is a diagram showing the operation waveforms of
6 is a schematic circuit diagram showing a data output system circuit of an embodiment of the MOS static RAM. FIG. Figure 7 is a block diagram showing an embodiment of the MOS static RAM of the present invention, and Figure 8 is the MOS static RAM of the present invention.
FIG. 3 is a schematic circuit diagram showing a data output system circuit of another embodiment. 1, 2, 3, 4: Memory cell, 5, 6: Word line, 7, 8: Column selection signal input terminal, 9, 10: Common data line, 11: Power supply voltage terminal, 12, 1
3, 14, 15: MOS transistor for data line bias, 16, 17, 18, 19: data line,
20: sense amplifier, 21: output buffer circuit,
22, 23: Common data line bias MOS
Transistor, 70, 71, 72, 73: MOS transistor for column selection switch, 50, 52,
54, 56, 58, 60, 62, 64, T ₃ ,
T ₄ : Transfer MOS transistor, 51, 53, 5
5, 57, 59, 61, 63, 65, T ₁ , T ₂ :
Drive MOS transistor, R ₁ , R ₂ , R: Load resistance (polycrystalline Si resistance, etc.), 101, 102, 10
3,104,110,111,112,113,
114, 115: Load MOS transistors for unselected data lines.

Claims (1)

[Claims] 1 A memory matrix formed by arranging a plurality of memory cells consisting of flip-flops formed from MOS transistors in a matrix, and a plurality of memory cells formed by commonly connecting the output ends of the memory cells arranged on the same column of the memory matrix. It has a pair of data lines, a first bias load MOS for the plurality of pairs of data lines, and a common data line to which the plurality of pairs of data lines are connected via a switch MOS transistor. , said switch
A MOS transistor is made conductive by applying a column selection signal to its gate, one of the plurality of pairs of data lines is selected, and storage information of one of the memory cells connected to the selected data line is stored. is read out onto the common data line, and a second load terminal is connected between each of the plurality of pairs of data lines and the power supply voltage terminal.
A semiconductor memory comprising a MOS transistor, the second load MOS transistor being made conductive when the data line is not selected.