JPS61264590A - Signal generating circuit - Google Patents

Abstract

PURPOSE:To operate a sense amplifier after completing surely read of contents of a memory cell by starting operation of the sense amplifier by the use of a delay of word line and a dummy bit line. CONSTITUTION:A drain of an insulating gate electric field effect transistor Q12 is connected to a bit line BL3 of a dummy and a drain of an insulating gate electric field effect transistor Q13 is connected to an opposite bit line -BL3 of the drain, respectively. Further, the gate of an insulating gate electric field effect transistor Q14 is connected to a source of the insulating gate electric field effect transistor Q12, the drain is connected to a source of the insulating gate electric field effect transistor Q13 and the source is connected to an earth potential, respectively. Since in the signal generating circuit 4, by the use of a delay of a word line and an insulating gate line, a timing for starting the operation of a sense amplifier 2 is determined, the contents of a memory cell 5 are effectively read and thereafter the sense amplifier 2 can be operated.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a signal generation circuit.

Conventional technology Figure 2 shows static random access memory (
This is an example of a conventional delay signal generation circuit in a SRAM (hereinafter abbreviated as SRAM). To explain the circuit operation of the conventional example, the delay signal generation circuit 1 generates the delay signal φ1 from the address input input, and this determines the timing at which the sense amplifier 2 starts operating. When reading the contents of a memory cell in an SRAM, first, the contents of the memory cell selected by the word line WL are transferred to the bit line B through insulated gate field effect transistors Q1 and 92, respectively.
L, opposite phase P), 1ilB I, read out to 1,
A potential difference occurs between both pit lines. After that, the delay signal φ1
bit line B by the sense amplifier 2 selected by
The potentials of the bit line BL1, which are in phase opposite to the L bit line, are amplified and become the no level and the low level, respectively. In this case, the contents of memory cell 3 are definitely shared between bit line BL1 and bit line BL1.
If the contents of the memory cell 3 are not amplified by the sense amplifier 2 after being read out, the contents of the memory cell 3 will be read out incorrectly.

Conventionally, as shown in FIG. 1, the timing at which the sense amplifier 2 starts operating has been determined using an address input input and a delay signal generation circuit 1. In other words, the delay signal generation circuit 1 is used to independently create a delay from when the address input input IN is input until the word line WL1 is selected and the contents of the memory cell 3 are read.

Problems to be Solved by the Invention In the conventional system, the contents of the memory cell 3 are transferred to the bit line BL.
, and the opposite phase pit line BL, the sense amplifier 2 operates before the data is read out to the opposite phase pit line BL, causing a problem in that incorrect contents are likely to be read out. Further, when using the conventional circuit described above, it is necessary to provide a sufficient delay time, which poses a problem in terms of high-speed operation of the circuit.

The present invention provides a circuit that uses word line delays and dummy memory cells to generate a delayed signal.

Means for Solving the Problems The present invention has a first bit line and a second bit line that form a pair, and a drain is connected to the first bit line and a gate is connected to a word line. a first insulated gate field effect transistor whose drain is connected to the second bit line and whose gate is connected to the word line; and a second insulated gate field effect transistor whose gate is connected to the first insulated gate field effect transistor. The signal generation circuit includes a third insulated gate field effect transistor whose drain is connected to the source of the second insulated gate field effect transistor and whose source is connected to ground potential.

As a result, the sense amplifier can be operated after the contents of the memory cell have been reliably read.

Embodiment FIG. 1 is a configuration diagram of an SRAM using an embodiment circuit of the present invention. The part surrounded by the dashed line in the figure is the signal generating circuit 4 of the present invention. In the figure, Q12, QCs, and Q14 are insulated gate field effect transistors, and the drain of the insulated gate field effect transistor Q12 is connected to the dummy bit line BL3.
The drains of the insulated gate field effect transistors Q13 are respectively connected to dummy anti-phase bit lines BL3. Further, the gate of the insulated gate field effect transistor Q14 is connected to the source of the insulated gate field effect transistor Q1□, and the drain thereof is connected to the insulated gate field effect transistor Q1
5 and the source is connected to the ground potential, respectively. The circuit operation of this embodiment will be explained below with reference to FIG.

First, before reading the contents of the memory cell 6, the clock φP
is set to high level, bit line BL2° and opposite phase bit line BL2. The dummy bit line BL3 and its opposite phase bit line BL3 are respectively connected to the insulated gate field effect transistor Q.
4, Q7. Qll, Q9 to precharge each bit line B L2. BL2゜Dummy bit line BL3
．． Set BL3 to power supply potential. Next, when the word line WL2 is set to high level, the insulated gate field effect transistor Q+
The same Qt+ as o is turned on, and furthermore, the word line WL
After a delay of 2, the insulated gate field effect transistor Q12 (h5) turns on. When the insulated gate field effect transistor Q1o and the same Qu turn on, the contents of the memory cell 6 are read out. The dummy bit line B
Since L3 is already precharged to the power supply potential, it is an insulated gate field effect transistor (same Q+ as h2).
3 is turned on, the insulated gate field effect transistor Ql is also turned on. As a result, the charge on the dummy anti-phase bit line BL3 is extracted through the insulated gate field effect transistors Q1s and Q14, and its potential begins to drop. One end of the bit line BL3 is connected to the gate of an insulated gate field effect transistor Qz+ constituting the comparison circuit 6. Insulated gate field effect transistor Q20
The gate of is connected to a reference potential vR intermediate between the ground potential Vs and the power supply potential VD determined by high resistances r1 and r2. When the opposite phase bit line BL3 is at the power supply potential V, the node N2 is at low level and Qlsr Q+
When the potential of the dummy bit line BL becomes lower than vR due to the charge extraction by the dummy bit line BL, the node N2 is inverted to high level, and the delayed signal φ is also set to the high level through the waveform shaping inverter 7.8. When φ2 becomes high level, the sense amplifier 2 amplifies the potentials of the bit line BL2 and the opposite phase bit line BL2. Here bit line BL
2. Opposite phase bit line BL2 and dummy bit line BL3.
The opposite phase bit lines BL have the same structure,
The behavior is the same when it comes to charging and discharging charges. therefore,
Rather than determining the potentials of the bit line BL2 and the anti-phase bit line BL2 by reading the contents of the memory cell 5, it is better for the charge on the dummy anti-phase bit line BL to be extracted and the delay signal φ2 to become -. Late sense amplifier 2
can reliably amplify the contents of the memory cell 6.

In the signal generating circuit 4 of this embodiment configured as described above, the timing at which the sense amplifier 2 starts operating is determined using the word line delay and the dummy bit line, so the contents of the memory cell 6 are reliably read. The sense amplifier 2 can be operated after the signal is read out, and there is no need to provide a delay time margin unlike the conventional circuit.

Effects of the Invention The signal generation circuit of the present invention starts the operation of the sense amplifier by using a word line delay and a dummy bit line, so the sense amplifier is operated only after the reading of the contents of the memory cell is reliably completed. can be done. Further, there is no need to provide a margin for delay time as in the conventional circuit. Therefore, the present invention is very effective in terms of stabilizing and speeding up circuit operation.

WLl) WL2 ・Mountain...Word line, BL1+BL1°BL2+BL2+...Bit line, BL5 r
B L5・.

...Dummy bit line, (h + Q2 +, Qs
+ Q4 v Qs.

Q6+ Qyr Qs r Q? P QHJI Q+
++ (h2νQ+x+ Q+a+Q15+ Q16t
Q171 Q1B! Q1? + Q201 Q21
...Insulated gate field effect transistor, 3,6...
...Memory cell, 2... River sense amplifier, 1.4
・Old...(No. generation circuit, 6... Comparison circuit, 7
, 8...mark, inverter, N1°N2...node, rj+r2...mark, resistance, φ1. φ2゛・・・・・・
Delay signal, φP...clock pulse, muin...
...Address Kugata, vR...Reference voltage,
vb・mountain: power supply potential, Vs: ground potential.

Name of agent: Patent attorney Toshio Nakao 1 person 2-
-' and listen 7th ``4'-f light FE floor 5--Sosoitnom

Claims (1)

[Claims] There is a first bit line and a second bit line that form a pair,
and a first insulated gate field effect transistor having a drain connected to the first bit line and a gate connected to the word line, a drain connected to the second bit line, and a gate connected to the word line, respectively. a second insulated gate field effect transistor with a gate connected to the source of the first insulated gate field effect transistor and a drain connected to the second insulated gate field effect transistor;
A signal generating circuit comprising a third insulated gate field effect transistor whose sources are connected to a ground potential.