JPH01185896A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To drastically shorten time required for access and to enable high speed read operation by constituting the output node of a current mirror type amplification circuit means and providing the plural sets of a sub-read data line in common with the fixed number sets of a bit line. CONSTITUTION:As the plural sets of a block 7 including a set of the bit line and one part of the current mirror type amplifier are connected to a set of the sub-data line OLS and the inverse of OLS in parallel, the plural sets of N channel MIS transistors Q16 and Q17 are connected to a set of the sub-data line OLS and the inverse of OLS in parallel. As the result of that, much gate capacity is connected and the load capacity of the current mirror type amplifier is made to be big. Then as only the block 7 of the fixed number sets of the bit line is connected to each set of a read only sub-data line and the current mirror type amplifiers are respectively provided to each set of sub-data line, the load capacity of a set of the read only sub-data line can be reduced and the high speed operation is realized. Thus, the time required for access can be drastically shortened and the high speed read operation is made to be possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a structure of a semiconductor memory device that can significantly shorten access time and realize high-speed read operation.

[Prior Art] In recent years, in highly integrated memory devices such as dynamic MO3RAM (random access memory using MOS transistors), with the increase in integration,
It is desired to speed up the read operation by significantly shortening the access time (time required to read data).

FIG. 4 is a conceptually simplified diagram showing an example of a memory cell and sense amplifier structure in a pair of bit lines in a conventional dynamic random access memory (hereinafter referred to as DRAM). In FIG. 4, bit lines BL and BL form a pair and constitute a folded bit line pair. That is, mutually complementary signals appear on the bit lines BL, BL. A plurality of word lines are provided in a direction perpendicular to the bit lines BL and BL. However, in FIG. 4, only one word line WL is representatively shown. Memory cells are provided at the intersections of word lines and bit lines, and the memory cells are arranged in rows and columns. Further, in the figure, only one memory cell 1 provided at the intersection of the bit line BL and the word line WL is representatively shown.

The memory cell 1 has a one-transistor/one-capacitor type configuration, and has a memory capacity CO for storing information and a word line W.
N channel M turns on in response to a signal applied to L and connects memory cell capacitor CO to bit line BL.
IS (metal-insulating film-semiconductor) transistor QO.

A flip-flop type sense amplifier 2.3 is provided to amplify the signal potential difference on the bit line pair BL, BL. Sense amplifier 2 is an N-channel MIS transistor Q
1. Q2, which discharges the bit line potential on the low potential side to the ground potential. The gate of MIS transistor Q1 is connected to bit line BL, and the drain is connected to bit line BL.

Mis) The gate of the transistor Q2 is connected to the bit line BL, and the drain is connected to the bit line BL. The sources of MIS transistors Ql and Q2 are connected to node N1. Sense amplifier activation means 4 for activating sense amplifier 2 in response to sense amplifier activation signal SO is connected to node N1. Sense amplifier activation means 4 is turned on in response to sense amplifier activation signal SO, and is composed of an n-channel MIS transistor Q5 that connects node N1 to the ground potential.

Sense amplifier 3 is a p-channel MIS transistor Q3
．． Q4 is activated in response to a signal from sense amplifier activation means 5, and charges the bit line potential on the high potential side to power supply potential Vcc. MIS transistor Q3
The gate of MIS transistor Q4 is connected to bit line BL, and the gate of MIS transistor Q4 is connected to bit line BL. MIS transistor Q3. One conduction terminal of Q4 is bit line BL.

BL, and the other conductive terminals are commonly connected to node N2. The output from the sense amplifier activation means is transmitted to the node N2. The sense amplifier activation means 5 is
P channel M turns on in response to sense amplifier activation signal SO and transmits power supply potential Vcc to node N2.
It is composed of an IS transistor Q6.

Bit line pair BL in response to equalize signal EQ.

Precharging/equalizing means 6 is provided to precharge and equalize the potential on BL. The equalize/precharge means 6 is turned on in response to the equalize signal EQ, and includes an equalizing N-channel MIS transistor Q7 that electrically shorts the bit line pair BL, BL, and a precharge potential in response to the equalize signal EQ. (2) The precharge N-channel MIS transistor Q8 transmits the signal 6 onto the bit line BL, and turns on in response to the equalize signal EQ, and precharges the precharge potential Va.
The precharge N-channel MIS transistor Q9 transmits L onto the bit line BL. Normally, the precharge potential V[IL is generated by an internal voltage generation circuit, and is set to a predetermined potential (for example, half of the power supply voltage Vcc, that is, a potential of Vcc/2).

Furthermore, each bit line BL, BL is turned on in response to a bit line pair selection signal (column decode signal) Y from a column decoder (not shown), and the bit lines BL, BL
N for connecting to the data input/output bus I10゜Ilo
Channel MIS transistors QIO and Qll are provided, respectively. Data input/output bus pair I10. I10 is an N-channel MIS transistor Q22.I10 that is normally turned on in response to a clock signal CLK. It is precharged to a predetermined potential V[IL by Q23. Data input/output bus pair I10. I10 exchanges data via a human output buffer.

FIG. 5 is a signal waveform diagram showing the operation of the semiconductor memory device shown in FIG. 4, and the same symbols as the signals shown in FIG. 4 indicate the waveforms of the respective signals. The operation of the conventional semiconductor memory device will be described below with reference to FIGS. 4 and 5.

When equalize signal EQ falls from high level to low level at time T1, MIS transistor Q7. Q
8. Both Q9 are turned off, and the bit lines BL and BL
The precharging and equalizing operations of are completed, and the bit lines BL and BL become in a floating state.

At time T2, when one word line WL is selected in response to an external address, the potential of the selected word line WL begins to rise. In response, transistor QO of memory cell 1 connected to selected word line WL
turns on, and a signal potential change occurs on the bit lines BL, BL in accordance with the information held by the memory cell 1. In FIG. 5, the change in signal potential on the bit line when memory cell 1 stores information "1" is shown by a solid line, and the change in signal potential on the bit line when memory cell 1 stores information "0" is shown by a solid line. Signal potential changes are indicated by dashed lines.

When the read signal potential on the bit line pair BL, BL is determined,
At time T3, sense amplifier activation signals so and so begin to rise and fall, respectively. As a result, MIS transistor Q5. Q6 is turned on, the node N1 is charged and discharged to the ground potential, and the node N2 to the power supply potential Vcc. As a result, flip-flop type sense amplifier 2
．． 3 are activated, and the potential of the bit line BL on the higher potential side of the bit lines BL and BL is charged to the power supply potential Vcc via the sense amplifier 3, while the bit line BL on the lower potential side is charged to the power supply potential Vcc through the sense amplifier 3. is discharged to ground potential via the That is, by activating the sense amplifier 2.3, the minute signal potential difference occurring on the bit line pair BL, BL is amplified.

After the amplification operation of the sense amplifier, at time T4, when the bit line pair selection signal (column decode signal) Y from the column decoder becomes high level, the MIS transistor Q
IO, Qll are turned on, and the potentials on the bit lines BL, BL become the data input/output buses I10. I10 respectively.

This data input/output bus I10. The potential transmitted onto I10 is then amplified by an amplifying means such as a preamplifier (not shown), and then transmitted to the outside via a data output buffer and an external output terminal (not shown).

When the transmission of data to the external terminal is completed, the potential of the word line WL decreases from high level to low level at time T5, and the level of bit line pair selection signal Y also decreases from high level to low level.

This causes data input/output bus pair I10. The potential on I10 returns to the precharge potential.

Next, at time T6, the sense amplifier activation signal so,
so transitions from high level to low level and from low level to high level, respectively, and both sense amplifiers 2 and 3 are rendered inactive. At this time, the equalize signal EQ
becomes high level, precharge/equalization means 6
is activated, the potential on the bit lines BL, BL is precharged to a predetermined potential V[IL, and each bit line pair BL,
The BL potential is equalized.

The above operation is an outline of the operation when reading data.

On the other hand, in the data write operation, the timing of the signal waveform is similar to that shown in FIG. Becomes a cell. That is,
A data write buffer (not shown) allows externally provided write data to be written in complementary form (e.g. D+N, D
+N) to the data input/output bus I10. transmitted on I10. After passing through the operation sequence from time T1 to T3, when the bit line selection signal Y changes from low level to high level at time T4, MIS transistor QIO
, Qll are turned on, and the data input/output bus pair I10
．． The signal potential on I10 is transmitted to the selected memory cell, thereby indicating that writing has been performed. At this time, sense amplifiers 2 and 3 are also activated at time T3, and the transition of the word line WL to high level amplifies the signal potential difference on the bit lines BL and BL. The data input/output bus I10. Since the write data is transmitted on I10, even if the signal potential level amplified by the sense amplifier 2.3 and the signal potential level of the write data are opposite, the signal potential changes depending on the write data. This causes the MIS transistor QO to appear on the lines BL and BL, thereby preventing writing of write data into the selected memory cell.
This will be done through.

[Problems to be Solved by the Invention] As described above, in the configuration of a conventional semiconductor memory device, data reading and writing are performed using the same data input/output bus pair I.
10. Since this is done via I10, bit line pair BL is also used when reading data.

BL and data input/output bus pair I10. I10 is connected via MIS transistors QIO and Qll. For high-speed reading, it is preferable to connect this bit line pair to the data input/output bus pair as soon as possible. However, if the bit line pair and the data input/output bus pair are connected, for example, between the rise time T2 of the word line WL and the sense start time T3 when the sense amplifier 2.3 is activated, the data input/output bus Since the load capacitance of the bit line is applied to the bit line, the level of successive signals on the bit line decreases, making it impossible for the sense amplifier to perform a reliable sensing operation, and possibly causing a malfunction. Therefore, the connection between the bit line pair and the data input/output bus pair must be made after the sense amplifier 2.3 is activated and the signal potential on the bit line pair BL, BL is determined. The bit line pair and the data input/output bus pair cannot be connected before time T3. Therefore, there is a problem in that there is a limit to speeding up the read operation, and it is difficult to further shorten the access time. In other words, in the case of a configuration in which data reading and writing are performed using the same data input/output bus pair,
There was a problem in that it was difficult to shorten the access time when data continued to flow.

Therefore, an object of the present invention is to provide a semiconductor memory device that can eliminate the problems of conventional semiconductor memory devices as described above, can significantly shorten access time, and achieve high-speed reading. It is.

[Means for Solving the Problems] A semiconductor memory device according to the present invention separately provides a read-only data line pair and a write-only data line pair, and each of the read-only data line pairs has a predetermined number. It consists of a plurality of sub data line pairs provided in common to the plurality of bit line pairs, and a main data line pair provided in common to the plurality of sub data line pairs, and each bit line pair and sub data line pair are connected to each other. In between, a current mirror amplifier is provided which uses the sub data line pair as an output node and uses the bit line pair potential as its input signal. This current mirror type amplifier is activated by the column decoder output.

[Operation] The current mirror amplifier amplifies a minute signal potential difference on a selected bit line at high speed without adversely affecting the bit line potential, and transmits the amplified signal to the main data line pair via an output node (sub data line pair). Therefore, the information of the selected memory cell can be reliably read onto the main data line before activation of the sense amplifier, and the access time when reading data can be significantly shortened.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, parts that are the same as or corresponding to those of the conventional semiconductor memory device shown in FIG. 4 are given the same reference numerals.

FIG. 1 is a diagram schematically showing the configuration of the main parts of a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1, a flip-flop type sense amplifier 2.3 and a precharge/equalization circuit means 6.1 transistor/1 capacitor type memory cell 1 are connected to the bit line pair BL, BL as in the conventional case. Ru. Further, the bit line pairs BL, BL are provided with MIS transistors QIO, Qll that are turned on in response to a bit line pair selection signal (column decode signal) Y from a column decoder (not shown).

Also, as in the conventional case, a sense amplifier activation transistor Q5 generates a signal for activating the sense amplifier 2.
, a sense amplifier activation transistor Q6 that generates a signal for activating the sense amplifier 3 are provided, respectively. Further referring to FIG. 1, in order to shorten the access time of the semiconductor memory device, a data line pair for transmitting only write data and a data line pair for transmitting only read data are provided separately. It becomes.

That is, data is written from the data write circuit to the write-only data line pair IL, the ILSMIS transistor Q12,
On the other hand, data reading is performed through the read data dedicated sub data line pair OLs, OLs and the read data dedicated main data line pair OLm.

The configuration is such that this is done via OLm.

The write-only data line pair IL, IL is connected to MIS transistors Q12 . Q1
The selected bit line pair is connected to the selected bit line pair via line 3. In other words, QIO and Qll turn on in response to column decoder output Y and write-only data line pair IL and I
A transistor Q12.L is connected between Q12. Q13 is provided for each.

As a data read path, a current mirror type amplifier is provided to detect and amplify the signal potential on the bit line pair BL, BL. This amplifier consists of transistors Q14-QQ1
9, the bit line pair BL, BL is connected to its input gate, and the output node is the read-only sub data line pair OL.
s and OLs.

゛ More specifically, in a current mirror amplifier, for example, a power supply potential Vcc is connected to a P-channel MIS transistor Q14, one of which is connected to a conductive terminal, and whose other conductive terminal is connected to a sub-data line OLS, and one of which is conductive. A P-channel MIS transistor Q15 has a terminal connected to, for example, power supply potential VCC, the other conductive terminal is connected to its gate and the gate of transistor Q14, and is connected to the sub data line OLs, and one conductive terminal is connected to the sub data line OLs. is connected to the bit line BL, and its gate is connected to the bit line BL.
an N-channel MIS transistor Q16 connected to;
(N-channel MIS whose one conduction terminal is connected to the sub data line OLS and whose gate is connected to the bit line BL)
Transistor Q17 is turned on in response to bit line pair selection signal Y from a column decoder (not shown), and transistors Q16. The other conductive terminals of Q17 are both connected to the ground potential via node N3, and N-channel MIS transistors Q18 and Q1 are used to activate this amplifier.
It consists of 9.

Transistor Q16. Since the input impedance of the gate of Q17 is extremely large, the bit line BL.

When activated, the signal potential difference on the bit line pair is amplified at high speed and transmitted onto the output node, that is, the sub data line pair OLs, OLs without any adverse effect on the signal potential difference on BL. The current mirror type circuit is used here because of its low power loss, high speed operation, and electrical isolation between the bit line and the sub data line.

Further, as seen from FIG. 1, the sub data line pair OLs
, OLs are connected to a predetermined number of bit line pairs 7, forming one block 8. In the memory cell array configuration, a plurality of blocks 8 are provided, and the output from each block 8 is connected to a common read-only main data line pair OL m,
The configuration is such that the information is transmitted to OL m. With this configuration, the sub data line pair O constituting the output node
Ls.

The load capacitance of the OLs can be reduced, and reliability and high speed of amplification operation can be ensured.

FIG. 2 is a signal waveform diagram showing the operation of a semiconductor memory device according to an embodiment of the present invention, and the same symbols as those shown in FIG. 1 indicate changes in signal potential of corresponding portions.

The operation of a semiconductor memory device according to an embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

First, the read operation will be explained. First, write instruction signal W
is at a low level, and the write-only data line pair is separated from the bit line pair. Before time T1, since the equalize signal EQ is at a high level, all MIS transistors Q7 to Q9 are in the on state, and the bit lines BL,
BL are each precharged to a predetermined precharge potential VBL. On the other hand, at this time, the read-only main data line pair OLm, OLm and the read-only sub data line pair OLs, OLs are also at the power supply potential Vcc, respectively.
is precharged.

At time T1, when the equalize signal EQ falls from a high level to a low level, all transistors Q7 to Q9 of the equalize/precharge circuit section 6 are turned off, and thereby each bit line BL and BL are both placed in a floating state.

At time T2, one word line WL is selected in response to an externally applied address signal, and the word line WL
When the potential shifts from low level to high level, transistor QO of memory cell 1 is turned on. Now, when the memory cell 1 stores information "1", the potential on the bit line BL rises slightly, as shown by the solid line in FIG. At this time, when the bit line pair selection signal Y from the column decoder (not shown) is shifted from low level to high level at time T1 in response to the external address signal, transistor Q18. Q19 is turned on, and a current mirror amplifier made up of transistors Q14 to Q19 is activated. Therefore, when the word line WL potential changes from low level to high level at time T2, the signal potential on the bit line BL slightly increases, and on the other hand, the bit line BL potential slightly decreases, this current mirror amplifier immediately The potential difference is amplified and the sub data line O
The Ls potential is discharged from the precharge potential to the ground potential.

The signal potential appearing on the sub data line pair OLs, OLs is transmitted onto the main data line pair OLm, OLm. This makes it possible to read data before activating the sense amplifier 2.3, making it possible to achieve high-speed access. At this time, the bit line pair BL, BL is connected to the read-only sub data line pair OLs, OLs and the transistor Q16. Q1
Since the read-only sub-data line pair OLs and the signal potential thereof have no adverse effect on the signal potential on the bit line pair BL, BL. Further, the sub data line pairs OLs and OLs are only provided in common for a predetermined number of bit line pair blocks 7, and their load capacitance is small, and the sub data line pairs BL and OLs are provided in common for a predetermined number of bit line pair blocks 7, and their load capacitance is small, and the sub data line pairs BL and OLs are provided in common for a predetermined number of bit line pair blocks 7, and their load capacitance is small. The output signal can be transmitted to the output nodes OL s and OL s at high speed.

After this, at time T3, the sense amplifier activation signal so
, so respectively to the active state, and the transistor Q
5. Q6 is turned on to activate sense amplifiers 2 and 3. As a result, the signal potential difference between bit lines BL and BL is further amplified. This amplification operation by sense amplifiers 2 and 3 is performed for a restore operation for rewriting read information into memory cell 1.

At time T5, when the selected word line WL potential and the column decoder output Y shift from high level to low level, the current mirror amplifier also becomes inactive, and the sub data line pair OLs, OLs and main data line pair OL
m and OLm return to the predetermined precharge potential.

Next, at time T6, the sense amplifier activation signal so,
When so transitions to an inactive state and equalize signal EQ rises to high level, each bit line BL and BL are precharged and equalized, and one memory cycle is completed.

Note that at time T2, when the bit line pair selection signal Y from the column decoder becomes high level, the transfer gate transistors QIO and Qll also transition to the on state at the same time. However, when reading data,
Since write instruction signal W is at a low level, transistors Q12. Q13 is in the off state, and the write-only data line pair IL, IL does not affect the data read operation.

In the above embodiment, the case where the selected memory cell 1 has the information "1" has been explained, but if the selected memory cell 1 has the information '0', the In FIG. 2, a signal waveform diagram indicated by a broken line appears.

Further, in the above embodiment, data line pairs OLs, O
The precharge potentials of Ls, OLm, and OLm are set to the power supply potential level, but the precharge level of the main data line pair is not set to the power supply potential level, but is set to an intermediate potential, for example, V[IL, as in the past. However, the same effect as in the above embodiment can be obtained.

Further, in the above configuration, one set of sub data line pair OLs
, OLs, a plurality of blocks 7 including a bit line pair and a part of a current mirror amplifier are connected in parallel, so that a plurality of N-channel MIS transistors Q16 . Q1
7 are connected in parallel to a pair of sub data lines OLs, OLs, and many gate capacitances are connected, resulting in a large load capacitance of the current mirror amplifier.

However, only a predetermined number of bit line pair blocks 7 are connected to each successive sub data line pair, and each sub data line pair is provided with a current mirror amplifier. The load capacitance of the pair can be reduced, and high-speed operation is achieved.

Next, a data write operation will be schematically explained. At this time,
External write data is sent from a data write circuit (not explicitly shown) in complementary form (eg, DIN).

D+N) to the write-only data line pair IL, IL. During this write operation, since write instruction signal W is at a high level, transistor Q12.013 is in an on state. Therefore, at time T4, the bit line pair selected by the column decoder output Y is connected to the data write-only data line pair IL, IL, making it possible to write data to the selected memory cell. . In the waveform diagram of FIG. 2, the column decoder output Y is shown to shift to high level at time T4 during data writing. Such intentional shift of column decoder output Y to the active state during writing and data reading can be easily realized based on write instruction signal W and column address strobe signal CAS.

Furthermore, in the above embodiment, it is explained that the column decoder output Y shifts to a high level at the same time as the equalize signal EQ shifts to a low level during data reading. The transition to is not limited to the operation timing shown in FIG. 2, but may be configured to shift the column decoder output to high level at the same time as the word line WL shifts to high level. In either configuration, the transition of the column decoder output Y, which provides the activation timing of the current mirror amplifier, to a high level is an operation that is appropriately determined taking into account the operating characteristics of the semiconductor memory device used in practical use. It is a parameter.

In addition, in the operation waveform diagram shown in FIG. 2, during data writing, the column decoder output Y is activated at time T4, that is, transitions to a high level as shown by the dashed line in FIG. The timing of shifting to the high level is not limited to time T4, and even if it is performed at time T2, the write operation can be performed reliably.

Further, in the above embodiment, the current mirror amplifier is formed by transistor Q14. Q15 is the electric potential Vcc
and transistors 018. Although a configuration is shown in which Q19 is connected to the ground potential, the connected power supply potential and the polarity of each transistor are not limited to the illustrated structure, and may be appropriately selected depending on the structure of the semiconductor memory device to which it is applied. It is something that should be done. Furthermore, in the above configuration, the current mirror amplifier is activated also during data writing. However, from the viewpoint of power consumption, the current mirror amplifier can also be activated only during reading. This can be easily realized by a configuration that ANDs the write instruction signal W and the column decode signal Y.

FIG. 3 is a diagram showing the overall schematic configuration of a semiconductor memory device having the structure shown in FIG. 1. Referring to Figure 3,
A semiconductor memory device according to the present invention includes a memory cell array 100 having a folded bit line structure and an internal row address signal from an address buffer 101 that receives an external address to select one row of memory cells from the memory cell array (i.e., one In response to internal column address signals from the address buffer 101, a Y decoder (column) outputs a bit line pair selection signal Y for selecting a pair of bit lines. decoder) 103, a read-only sub-data line pair provided for each bit line block consisting of a predetermined number of bit line pairs, a successive-only sub-data line pair provided in common for each sub-data line pair, and a read-only sub-data line pair provided in common for each sub-data line pair; Consists of a current mirror type amplifier provided (current mirror amplifier + output line)
A block 104, a preamplifier 105 for further amplifying the read data from the block 104, a read buffer 106 for outputting the read information from the preamplifier 105 to an external terminal, and internal write data generated from the write data DIN. and a write buffer 108 for transmitting data to the data input line pair IL included in the input block 107 and IL. The write instruction signal W is transmitted to each required circuit portion via the terminal 109. This configuration is merely an example, and other configurations are of course applicable.

[Effects of the Invention] As described above, according to the present invention, data line pairs for continuous output and data line pairs for write only are provided separately, and read-only data line pairs correspond to a predetermined number of bit line pairs. It consists of a read-only sub-data line pair provided as a sub-data line, and a read-only main data line pair provided in common with each sub-data line pair, and each read-only sub-data line pair is connected to the output of a current mirror amplifier. Since the bit line pair is connected to the input gate of the current mirror amplifier, the minute signal potential difference on the bit line pair can be amplified and read even immediately after the word line rises. This makes it possible to significantly shorten the access time when reading data, making it possible to realize high-speed reading.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing the configuration of the main parts of a semiconductor memory device which is an embodiment of the present invention. FIG. 2 is a signal waveform diagram showing the operation of a semiconductor memory device according to an embodiment of the present invention. FIG. 3 is a diagram illustrating the overall schematic configuration of a semiconductor memory device which is an embodiment of the present invention. FIG. 4 is a diagram schematically showing the configuration of a pair of bit lines and related circuit portions in a conventional semiconductor memory device. FIG. 5 is a signal waveform diagram showing the operation of a conventional semiconductor memory device. In the figure, 1 is a memory cell, 2 and 3 are flip-flop type sense amplifiers, 4.5 is a sense amplifier activation signal generation circuit section, 6 is an equalize/precharge circuit section, and 7
8 is a bit line pair block, 8 is a block consisting of a predetermined number of bit line pairs, read-only sub data line pairs and a current mirror amplifier, dedicated main data lines, BL, BL are bit lines,
Q14゜Q15. Q16. Q17. Q18. Q19 is an MIS transistor forming a current mirror type amplifier. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A plurality of memory cells arranged in rows and columns, a plurality of word lines for selecting one row from the memory cells,
a plurality of bit lines for selecting one column of the memory cells, and the plurality of bit lines are arranged so as to form a folded bit line pair, the semiconductor memory device comprising: a plurality of bit lines for selecting one column of the memory cells; a pair of write data transmission lines that are connected to the selected bit line pair and transmit only write data; current mirror type amplifier circuit means for differentially amplifying the bit line pair potential as an input signal; A semiconductor memory device comprising: a plurality of sub-read data line pairs; and a main read-data line pair that receives signals on the plurality of sub-read data line pairs and transmits read data.