JPS63222386A - Dynamic semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain the high speed of a device by inputting the output of a bipolar MOS type differential amplifying circuit to a MOS-FF circuit and restoring. CONSTITUTION:The data of a memory cell 20a and a dummy cell 12a is read to bit lines BL, BL, and a small potential difference is inputted to the base of the driver bipolar transistors T10, T12 of a circuit 56 through a C-MOS current mirror circuit 52a functioning as the impedance element of the bipolar C-MOS differential amplifier 56. Then, the amplified output of the circuit 56 is transferred to output lines OL1, OL2. It is fed back to an FF circuit 54 a through transfer gates FETQ54, Q56 and restored at high speed. Further, the potential difference in the bit lines goes to about 2V, an FF circuit 50a is operated to raise a voltage substantially to a supply voltage. Thereby, the high speed device can be attained.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a dynamic semiconductor memory device.

(Prior Art) MOS type semiconductor memory devices are becoming increasingly finer and faster. d
In the field of RAM, bipolar technology is also being used to increase speed. For example, IEDM 1986 p.
802-804 contains the paper “Bipolar CM O
S merged 5structure forhig
h5peed MbU DRAM" was introduced and there was a presentation on the basic process. Also, regarding the circuit, there is, for example, Japanese Patent Application Laid-Open No. 142594/1983.

FIG. 12 shows a DRAM circuit disclosed in the publication. MO3 circuit 11 and resistor Rl + R on the bit line
BI has greater ability to amplify minute signals than a MOS flip-flop circuit through a MOS differential amplifier circuit consisting of 2.
A MOS differential amplifier circuit 12 is connected to increase the output speed. Furthermore, a MOS flip-flop 13 having a high input impedance and easily connected to a destructive memory cell is used for storing memory cell data, which has more time than data output.

(Problems to be Solved by the Invention) Although this circuit configuration can connect a destructive memory cell and an IMO8 type O8 amplifier circuit with a large amplification capacity, it has the following problems.

First, although a MOS flip-flop is used to store memory cell data, the minimum signal that can be amplified at high speed is as large as approximately 100 m1/, so the memory cell capacity Cs
The future high-density d that cannot be secured with the conventional 40fF
RAM has a problem with speeding up. For example, dR of 4M or more
Considering AM, the bit line capacity 'mCB is approximately 600 f.
F, and the potential difference between the bit line pair is +voo(C8/
CB), the class memory cell capacity Cs requires 4 x aoo-aorp. Therefore, d of 4M or 16M or more
Since RAM does not have sufficient memory cell capacity, the restore time must be increased by an order of magnitude or more to compensate for this, which affects the speed-up achieved by bipolar.

Second, since the BIMO3 differential amplifier circuit is activated by the column selection signal, it is difficult to increase the access time using the address multiplex method.

In other words, since bipolar transistors require time to move from the blocking region to the active region, if the CAS input is slow, the BI
The operation of the MO3 amplifier circuit is delayed and high-speed operation cannot be achieved.

Third, resistors R1 and R2 are connected to the load of the MOS circuit 11 that constitutes the MO3 type differential amplifier circuit that receives bit line data.
is used, so it is vulnerable to parameter variations. This changes the output voltage of the MO5 type differential amplifier circuit, making it difficult to achieve optimal operation of the BIMOS type differential amplifier circuit and impairing high speed.

[Structure of the Invention] (Means for Solving Problems) In the present invention, the output of the BIMOS differential amplifier circuit is input to a MOS flip-flop circuit for restoration. In addition, the BIM
The feature is that the OS type differential amplifier circuit is pre-activated.

Furthermore, as an MO8 type differential amplifier circuit, for example, the output can be connected to a load M.
Another feature is that it is fed back to the gate of the OS transistor.

(Function) The minute potential difference appearing on the bit line pair is sensed at high speed by the BIMO5 type differential amplifier circuit, and this is used as input to
The OS flip-flop applies a wide potential difference to the bit line pair to perform restoration.

In addition, the row address strobe (RAS) signal
By pre-activating the OS type differential amplifier circuit,
Even if the column address slope (CAS) signal arrives late, one data list can be output at high speed.

In addition, by using such an MO8 type differential amplifier circuit, even if process parameters vary during the manufacturing process, stable operation can be maintained by feeding back the output, and the next stage BIMOS type differential amplifier circuit This makes it possible to maintain high-speed operation.

(Embodiment) FIG. 1 shows a circuit configuration of a first embodiment of the present invention. In this first embodiment, 81 MO
This uses a three-structure sense amplifier.

In FIG. 1, two bit line pairs BLI and BL
I', BL2 and BL2', one word line WL and one dummy word line DW intersecting these.
L is shown. At the intersections of the bit lines BLI, BL2 and the word line WL, memory cells 20a,
20b is provided. Bit line BLI, BL
2 and the dummy word line DWL is a dummy cell 22a.

22b is provided. Each memory cell has one MO
It consists of an SFET and one capacitor.

Furthermore, dummy cells 12a and 12b are write MOs.
The drain 48 of each SFET is given a predetermined write potential, and the potential is simultaneously applied to the gate 49 of each MOSFET for writing to a "H" level, thereby forming the dummy cells 12a, 12b. Since the connection structure of these cell transistors and cell capacitors is well known, a description thereof will be omitted, and reference numerals thereto are also omitted in FIG.

Word line WL and dummy word line DWL have memory cells and dummy cells at the intersection with one bit line of the bit line pair.

In FIG. 1 one of a number of word lines WL is shown. The next word line shown has a memory cell at its intersection with the bit lines BLI' and BL2', respectively. In addition, in FIG. 1, two dummy word lines D
One of the WLs is shown, and the dummy word line not shown is the bit line BL1. A dummy cell exists at each intersection with BL2.

The sense amplifier circuit section connected to each bit line pair is
A first flip-flop circuit composed of CMOS FETs (hereinafter referred to as "CMOS flip-flop circuit") MOS type differential amplifier circuit composed of 50.0 MO8FETs (hereinafter referred to as "CMOS current mirror circuit") 52, second flip-flop circuit (hereinafter referred to as “CMOS
Flip-flop circuit °) 54, and BIM
It includes a differential amplifier circuit section 56 having an OS structure. However, one BIMOS differential amplifier circuit section 56 is provided in common for two adjacent bit line pairs. In FIG. 1, the BIMO6 differential amplifier circuit section 56 includes two bit line pairs BLI and BLI', BL2 and BL.
2'. In this figure, the subscript "a" is attached to the first and second flip-flop circuits 50, 54 and the current mirror circuit 52 provided on the first bit line pair BLI, BLI', and the second bit line pair BL2. The subscript "b" is attached to the first and second flip-flop circuits 50, 54 and the current mirror circuit 52 provided in BL2'. (However, in the following explanation, these subscripts will be omitted if there is no need to specifically distinguish between them.) Common BIM
The OS differential amplifier circuit 56 has a pair of output lines OLI and OL.
A short circuit 58 connected to the output line OL
I, OL2, and functions to latch and hold the data potential on these lines.

The first CMOS flip-flop circuit 50a amplifies the potential difference between the bit line pair BLI and BLI'.
It is constructed by connecting four MOSFETs in a known manner. The current mirror circuit 52 includes six MOSFETs.
Consisted of.

MOSFET Q30. Q32 and MOSFET Q30. Q Yanel MO
8FET Q30. Q32. Q34゜P in addition to Q36
Channel MO8FET Q38°Q40 exists. The configuration of the CMOS current mirror circuit 52b provided on the other bit line pair BL2, BL2' is the same as above, so in order to simplify the explanation, a dash symbol "" is added to the corresponding reference numerals in FIG. Therefore, their explanation will be omitted.

Second CMOS flip-flop circuit 54a includes a path. MOSFET Q42. The gates of Q44 are commonly connected to each other by signal line 60, and the gates of MOSFET
Q46. The gates of Q48 are commonly connected to each other by signal line 62. MOSFET Q50 is connected between line 60 and the common connection electrode of MOSFETs 42.44 (connected to bit line BL1).

MOSFET Q52 connects the signal line 62 and the MOS
Common connection electrode of FET 46.48 (bit line B
LI'). M
OSFET Q50. The gates of Q52 are connected together. Signal line 60°62 is an M05FET Q54. which functions as a transfer gate. They are connected to the differential amplifier circuit 56 via Q56, respectively. M.O.S.
The gates of FETs Q54 and Q56 are connected to each other.

The other bit line pair BL2. The configuration of the CMOS flip-flop circuit 54b provided in BL2' is the same as that of the circuit 54a, so to simplify the explanation, the first
In the figures, corresponding reference numerals are marked with a dash "" and their explanation is omitted. As mentioned above, the differential amplifier circuit connects two pairs of bit lines BLI and BL2'.
, coexist for BL2 and BL2', so
Signal lines 60.60' and 62.62' are each connected to the same output terminal of differential amplifier circuit 56, as shown. In each bit line pair, a two-stage flip-flop circuit 50 is used to store memory cell data.
．． 54 is provided.

The BIMOS differential amplifier circuit 56 includes a series circuit of a MOSFET Q58 and a bipolar transistor TIO, and a MOS
FET Q60 and a series circuit of bipolar transistor T12. Bipolar transistor TIO,T
12 commonly connected emitters are parallel MOSFE
T Q62° Connected to Q64. The base of the bipolar transistor TIO, T12 is connected to the signal line 64
．． 66, the CMOS current mirror circuit 52a
, 52b. Therefore, the output signals of the CMOS current mirror circuits 52a and 52b are transmitted to the bipolar transistors TIO and T12 of the differential amplifier circuit 56.
supplied to the base of Bipolar transistor TIO
The collector is a flip-flop circuit 54a,
54b and to signal line 68. Signal line 68 is M.O.
It is connected to the output line OLI via SFETQ66.

The collector of the bipolar transistor T12 is connected to the signal line 62 of the flip-flop circuits 54a and 54b.
．． 62' and to signal line 70. Signal line 70 is connected to output line OL2 via MOSFET Q68. MOSFET
The gates of Q6B and Q68 are connected to column selection line 72. Output lines OLI and OL2 are connected to a known output circuit (not shown).

Further, the outputs of the CMOS current mirror circuits 52a and 52b are connected to a gate FET Q73. between the transfer gates Q70 and Q72°. Q75. Q75' is provided.

Also, each bit line pair BLI and BLI'.

BL2 and BL2' are each a precharge circuit 74a.
, 74b. When the access period ends and the data is restored to the memory cell, the precharge circuit 7
4, the potential of each bit line is precharged to a predetermined level.

Precharge circuit 74 is MOSFET Q74゜Q7
B, 07g, and further includes a control line 76 and a precharge line 78 to which a predetermined potential is applied.

BICMOS differential amplifier circuit 56 configured as described above
The operation mode of the dRAM having the sense amplifier circuit section will be explained with reference to the signal waveform diagrams shown in FIGS. 2(a) and 2(b). In the description of the operating modes, bit line vs. BLI.

Assume that bit data "0" stored in the memory cell 20a of BLI' is read.

Row address strobe RA in active state
S (a row address group is manually input to the chip in synchronization with RAS) and column address strobe CAS (CA
Column address group is input in synchronization with S) Figure 2 (
As shown in a), it becomes a logic "L" level. R
When AS becomes the logic "L" level, the logic "H" level activation designation signal φA is supplied to the differential amplifier circuit 56 and the current mirror circuits 52a and 52b, respectively. FET 06% gate 80, and at the same time current mirror circuits 52a, 5
2b FET Q34. Q34' game) 84.84
' will be supplied. Next, the CAS current mirror circuit 5
2a and the differential amplifier circuit 56. That is, the column selection signal φY1 is applied to the FET of the current mirror circuit 52a.
Manually operated at gate 86 of Q36. Column selection signal φYA is supplied to the gate 82 of FET Q64 of differential amplifier circuit 56. The column selection signal φYα is sent to the FETs Q66 and Q of the differential amplifier circuit 56 via the signal line 72.
68 gates. In addition, column selection signal φY
1 is MOSFET Q70. Q72 gate 11α,
112.

FET Q34. The dimensions of Q34' and QB2 are the corresponding FETs Q3B and 03B'.

It is set smaller than that of Q54, thereby reducing power consumption. Activation designation signal φA by RAS input
As a result, the current mirror circuits 52a, 52b and the differential amplifier circuit 56 have several m
A current of approximately A flows, and at this time the bipolar transistor T10.12 is prepared for operation. Therefore, even if the input of CAS is delayed, the access time t
RAC is not affected by this and is not affected.

Next, when the memory cell word line WL and the dummy cell word line DWL are selected (potential changes on the lines WL and DWL are shown in FIG. 2(a)), the memory cells of the bit line pair BLI, BLI' are selected. 20a and dummy cell 22a are transferred to the bit lines BLI, BLI'
will be transferred to each. Therefore, the bit lines BLI, BL
The potential at I' changes depending on the memory cell data and dummy cell data. Since the dRAM is intended to be an ultra-high density memory of 4 megabytes or more, the memory cell capacitor Cs is reduced to about 151'F. Therefore, the potential difference Δv1 between the bit lines BLI and BLI' is extremely small, about 50 mV at most. See Figure 2(b). However, “VBLL”, “VBLI”
``V out''+''V out''' indicates the potential change V at the output lines OLI and OL2, respectively. ) This minute potential difference is amplified by the BIQQO;S differential amplifier circuit 56. This data signal amplification circuit operation is also fast. This is because the amplified output voltage of the differential amplifier circuit 56 constituting the driver section is increased to about 5 QOmV.

When the BICMO3 differential amplifier circuit 56 amplifies the read voltage, the input terminal of the differential amplifier circuit 56, that is, the driver bipolar transistor T10. A CMOS current mirror circuit 52a connected to the base of T12 functions as an impedance conversion element of the differential amplifier circuit 56.

The amplified output voltage of the BICMO8 differential amplifier circuit 56 is applied to the output line OL via the output transistors 066 and Q68, which are turned on in response to the signal φYα.
l, transferred to OL2.

On the other hand, the output voltage of the differential amplifier circuit 56 is applied to the transfer gate FET Q54. The signal is input to the second CMOS flip-flop circuit 54a via Q56. That is, the common gate terminal 8 of the transfer gate FET Q54゜Q56 of the second flip-flop circuit 54a
The potential φT1 at 8 becomes the logic "H° level" as shown in FIG. 2(a) with a slight delay from the selection of the word line WL and dummy word line DWL shown in FIG. 2(a). (At this time, the transfer gate FET Q54' of the second flip-flop circuit 54b of the unselected bit line pair BL2°BL2'.

The potential φT2 at the common gate terminal 90 of Q56' is
In response, FETQ54. Q56 becomes conductive. Therefore, the output voltage of the differential amplifier circuit 56 is applied to the conductive transfer gate FET.
Q54. It is fed back to the second CMOS flip-flop circuit 54a via Q56.

The input voltage of the CMOS flip-flop circuit 54a is 50
It is also amplified to 0 mV. Therefore, FET Q44
．． The potential φSBI at the common source terminal 92 of Q4g (solid line) and FET Q42° (broken line) change as shown in FIG.
is activated, the bit line pair BLI, BLI'
The potential above can be amplified rapidly. Therefore,
The storage operation of the memory cell 20a can be performed at high speed and effectively. Since the above voltage cannot be increased to about the dRAM power supply voltage Vcc, in order to ensure the restore operation of the memory cell, the potential difference ΔV2 (Fig. 2 (b)) on the bit line must be increased to about 2V. When this occurs, the second CMOS flip-flop circuit 54a is turned off, and the first CMOS flip-flop circuit 54a of the conventional configuration is turned off.
The S flip-flop circuit 50a is operated to perform voltage amplification, thereby increasing the potential difference Δv2 to a voltage ΔV3 (FIG. 2(b)) approximately equal to the power supply voltage vCC. first commercial
When operating the OS flip-flop circuit 50a, the FET common electrode terminal of the circuit 50a is connected as shown in FIG.
The solid line represents φSAI, and the broken line represents φSAI.

The data read and data restore operations in the memory cell 20a provided on the bit line pair BL1°BLI' described above are the "first access cycle".
This period is indicated as "Tal" in FIG. 2(a). Subsequently, the adjacent bit line pair BL2
．． The data restore operation in the memory cell 20b provided in BL2' is performed in the 'second access cycle' Ta.
2 (FIG. 2(a)). Before entering the second access, the signal φYl used in the previous first access is used to prevent interference between bit lines BL and reset each circuit.

φYA, φYα, and φT1 are set to logic "L" level (FIG. 2(a)). Even in this state, the cell data of the bit line pair BL, 1 to %QItl BLI' continues to be stably held by the latch circuit 58. The data read in this way is output on the output line OL1.
．． It is output as a data output signal Dout from an output circuit (not shown) connected to OL2.

In the second access mode, bit line pair BL2. The CMOS current mirror circuit 52b provided in BL2' is activated by the logic "H#" level of the gate 86' of MOSFET Q36' and φY2. Also, φY2 is connected to the transfer FE
T Q70', Q72' gates 114 and 116 are manually operated. At this time, since the potential at the terminal 82 of the BICMO8 differential amplifier circuit 56 also becomes the logic "H" level again, the differential amplifier circuit 56 also becomes operational again. This causes the bit line pair BL2. The potential difference between BL2' is B I C
It is amplified by a MOS differential amplifier circuit 56. Next, at the transfer gate terminal 90 provided between the second flip-flop circuit 54b and the differential amplifier circuit 56,
As shown in FIG. 2(a), a gate open signal φT2 which changes to logic "H" level is supplied. The solid line in FIG.
A signal φSB2 having a waveform shown in FIG.

After that, the terminal 10 of the first flip-flop circuit 50b
6 (This is the signal φSA supplied to the terminal electric flux of the flip-flop circuit 50a and the flip-flop circuit 50b.
A signal φSA2 having a waveform represented by 2) is supplied. As a result, a restore operation is performed on the memory cell 20b of the bit line pair BL2°BL2' according to the same method as described above. On the other hand, the data of the memory cell 20b read in this way changes φyl to logic “H#”.
By changing the level, it is also possible to output from the output lines OL1 and OL2.

When the row address strobe RAS and the column address strobe CAS are set to logic "H" level as shown in FIG. 2(a) for precharging, all of the access operations are completed and then the word line WL
, the dummy word line DWL becomes 'L', and then,
Switch to precharge mode. In the precharge mode, preferably terminals 118, 118' of each second flip-flop circuit and terminal 1 of the gate FET Q73
19. Q75. A reset signal φEQL (the waveform of which is shown in FIG. 2(a)) is supplied to each terminal 121.degree. 121' of Q75'. Additionally, the bit line BL2. in the second access mode. The potential differences ΔVI, ΔV2. which are sequentially amplified in BL2'. AV3 is
This is shown in FIG. 2(b). In Figure 2(b),
“VBL2”.

"V BL2°" is bit line BL2. It represents the potential change at BL2'.

In the precharge cycle, the precharge circuit 7
4 FET Q74. Q76 and Q78 are control line 7
6 becomes conductive by applying a logic state "H" to it, and a predetermined precharge voltage is supplied from the precharge line 78 to all bit lines. The precharge level is, for example, 2Vcc. 1a, IJc, I$ +
'fka, Denchu, Vs5 +a, -t4ze$iiq''a
+2° Dummy cells 12a and 12b are memory cells 2
0a.

The intermediate level between "1" and "0" degrees of 20b is stored.

This is done at an appropriate timing after the access period ends. For example, when the write level of the dummy cell is at the Vcc level, the capacitance of the dummy cell is made the same as that of the memory cell. The FET added for writing into the dummy cell may be omitted, and the dummy word line DWL may be closed after precharging of each bit line is completed. Alternatively, if the precharge level of each bit line is a highly accurate -Vcc level, the dummy cells can be omitted.

BICM of the first embodiment of the present invention configured as described above
By using the sense amplifier circuit section having the OS differential amplifier circuit 56, memory cell data can be read out satisfactorily and at a sufficiently high speed even in a miniaturized dRAM having submicron cells in which the cell capacitor Cs is miniaturized to more than ten rF. and restore. This is because even if the cell capacitor Cs is extremely reduced and the cell data is reduced, the BICMO3 differential amplifier circuit 56. This is because the sense amplifier circuit section including the two-stage flip-flop circuit 5%dL54 can effectively amplify the signal.

According to the above circuit configuration, although the amplification capability of the CMOS flip-flop circuit itself is unchanged from that of the conventional circuit, bit line data can be effectively restored. This is because the input signal of the twelfth flip-flop circuit 5Y/& is amplified at high speed by the differential amplifier circuit 56 and transferred by the transfer gate FET Q54. This is because it is a data signal supplied via Q56. In this case, even if the potential difference between the bit line and the in data is as low as, for example, about 50 mV due to the cell miniaturization in a highly integrated dRAM of 4 megabits or more, the two-stage amplification can still achieve the desired level. It becomes possible to amplify the potential difference to a certain extent in a short time. As a result, the speed of data storage operation can be significantly improved.

According to the present invention, in order to obtain the same bit line potential difference, the cell capacitance, which conventionally required at least 30 fP, can be halved at once. Therefore, a highly reliable and ultra-highly integrated dRAM can be obtained.

FIG. 3 shows a dRAM which is a second embodiment of the invention. According to this embodiment, a differential amplifier circuit included in the sense amplifier circuit section is provided for each bit line pair. In FIG. 3, similar parts shown in FIG. 1 are given the same reference numerals, and detailed explanation thereof is omitted.

1 and BLI', and BL2 and BL2'. The current mirror circuit 200 includes the first
Like the embodiment shown in the figure, it functions as an impedance conversion element of the differential amplifier circuit 202.

First bit line pair BL1. In sL1', the current mirror circuit 200a includes MOSFETQ30. Q
32 common connection source electrodes are MOSFET Q84
It is connected to the. MOSFETQ30. The drain electrode of Q32 is further connected via signal lines 204.206 to bipolar transistors T14. T16 respectively connected to the base of the CMOS current mirror circuit 200.
The output of is input to the differential amplifier circuit 202.

The BICMOS differential amplifier circuit 202 includes a second CMOS flip-flop circuit 54 and a pair of output lines OLI,
It is provided between the OL2 and the OL2.

Bipolar transistor T14. The T16 collector is
MOSFET Q92. Q94 and a MOSFET Q54.Q94 similar to that shown in FIG.
G, which is composed of Q56.

It is connected to a flip-flop circuit 54a via a transfer gate section. Bipolar transistor T1
4. The emitters of T16 are commonly connected to each other and the MOS
Connected to FET Q96. MOSFET
Q100 is connected in series between the collector of bipolar transistor T14 and the output line OLI.

MOSFETQ102 is a bipolar transistor T1
6 and the output line OL2. Therefore, the bipolar transistor T14 of the differential amplifier circuit 202a. T16 causes the current to rise, returns to the flip-flop circuit 54a, and supplies it to the output line 6OL. FET Q other bit line pair BL2. The configuration of the sense amplifier circuit section including the flip-flop circuit 54 and the differential amplifier circuit 202 provided in BL2' (and each of the remaining bit line bares not shown) is also the same as described above. In FIG. 3, bit line pair BL2. The circuitry provided in BL2' is simply depicted by blocks, with the corresponding reference numbers appended with the suffix "b" (eg 200b). The corresponding signal line is marked with a dash “”.

dR having a sense amplifier circuit section configured in this way
The data read/restore operation of AM is basically similar to the dRAM of FIG. 1, except that the store operation of all bit line pairs BL, BL' is performed simultaneously.

The differential amplifier circuit 202 can more effectively amplify the cell data appearing on the bit line pair. This can further improve the read/restore performance of dRAM cell data.

Q84 respectively. Q96 There was one each. However, as in the example of FIG. 1, each of them can be a parallel FET.

The F E Ti added at this time is made conductive to the selected bit line pair according to the column address.

FIG. 4 is an operational timing diagram of the dRAM of the embodiment shown in FIG.

When the row address strobe rτ1 signal is input, φA goes to the logic state “H” and BLI and BL are applied to each bit line pair.
CMOS current mirror circuit provided in I', BL2 and BL2'%13. BICMOS differential amplifier circuit 20
2 FET Q84. Gates 84 and 80 of Q96 are set to logic state "H".

Next, when the column address strobe CAS signal is input, φ
When YB is in the logic state 'H' and the memory cell 20a is selected, the transfer F that connects the BICMO3 differential amplifier circuit 202a and the output lines OLI and OL2.
ET Q100° puts the gate 208 of Q102 into the logic state "H". On the other hand, dummy word line DWL
And the word line WL selected by the RAS input becomes a logic state "H", and the bit line pair BL.

The potential difference between BL' is amplified at high speed by the BICMOS differential amplifier circuit 202.
The output of a is output to output lines OL1°OL2.

In parallel with this, the terminals 88 and 90 are set to the logic state "H" by φT, and the second CMOS flip-flop circuit 54a.

54b(7) terminal 92,941. : activation signal φSB,
<68B is input. and each second CMOS
The outputs of the flip-flop circuits 54a and 54b are the first CMOS flip-flop circuits 50a and 50.
By inputting activation signals φSA, d) 9A to terminals 96 and 98 of b, the signal is further amplified to the restore level.

After this, RAS and CAS become the logic state "H" level. The subsequent operation is the same as that of the first embodiment, and will therefore be omitted.

FIG. 5 shows a modification of the invention. That is, in the first and second embodiments, the first and second flip-flop circuits are provided for each bit line pair as flip-flop circuits for storing read data. FIG. 5(a) shows a CMOS flip-flop circuit in which the above-mentioned first and second flip-flop circuits are realized by switching. That is, P-channel MO3FET
QIIO, Q112 and N-channel MO3FET Q114
, 116. Q118. Q120. Q122 and Q124
have. Q118. Equalize signal φELQ is input to Q120. A switching pulse φR is input to Q122 and Q124. Therefore, as shown in FIG. 5(b), the BICM in FIGS.
After amplifying the outputs of the O3 differential amplifier circuits 56 and 202 to Δv2 by applying the logic state "H" level of the signal φT to the gates of the transfer FETs Q54 and 55, respectively, the "H" level of φR is applied to the gates of the transfer FETs Q54 and Q55, respectively. It is used to input to each gate of Q124 and amplify it to the restore level.

A third embodiment of the present invention will be described with reference to FIGS. 6 and 7. In both FIGS. 6 and 7, a pair of bit lines BL,
BL' and its associated CMOS flip-flop circuit 50. A MOS differential amplifier circuit 210 and a BICMO3 differential amplifier circuit 212 are shown. Descriptions of parts similar to the first and second embodiments will be omitted.

The MOS type differential amplifier circuit 210 has a P-channel load MO3.
FET Q130 and an N-channel drive MO3FET Q1 connected in series with it to form a current bus.
It has 32. Also, one more thing (7) is the P-channel load MOSFET Q134 and the N-channel drive MOSFET connected in series to form a current path.
It has Q136.

PET Q132. The sources of Q136 are connected in common, and are connected to the reference potential VSS via an activating N-channel MOSFET Q138.

The gate of Q132 is connected to bit line BL, while the gate of Q136 is connected to bit line BL'. In the example of FIG. 6, Q130. The gates of Q134 are commonly connected and one output is fed back.

′! In the example shown in Figure J7, the gates of Q130 and Q134 are commonly connected and connected to the reference potential VSS.

The B I CMOS differential amplifier circuit 212 includes bipolar transistors T18. T2O, MOSFET Q140.
It consists of two resistors R. Each resistor R is a P-channel MOSF
Each can be replaced with ET.

FIG. 8 briefly shows an example of the operation of the L-type dRAM circuits shown in FIGS. 6 and 7, respectively.

When the row address strobe RAS signal is input to the chip, the FET of the MOS type differential amplifier circuit 210 is
The gate 214 of Q138 is also connected to BIMO by φB.
The gate 80 of the FET Q140 of the 5-differential amplifier circuit becomes the logic state "H".

Next, when the column address strobe CAS signal is input, the terminal 208 is set to the logic state "H" level by φY. After this, word line WL.

Dummy word line DWL becomes “H” level and BIM
The data amplified by the O3 differential amplifier circuit 212 is transferred to the output lines OLI and OL2.The activation signal φSA and <6SA are transferred to the terminals 96 and 98 of the OS flip-flop.
, and then the word line WL is closed and restored. FET Q73 is for equalization.

It is also possible to provide a MOS type differential amplifier circuit 210 and a BIMOS differential amplifier circuit and connect a desired bit line pair to the BIMO6 differential amplifier circuit 212 using a column address.

Based on FIG. 6 and FIG. 7, the MOS type differential amplifier circuit 210
The study was conducted by classifying them into the following four types.

Type: A current mirror circuit of the type shown in Figure 6, with F
ET Q138 gate input φA is 1y8V type ■; Current mirror circuit of the type shown in Figure 6, F
ET 013g gate force φA is 5. Ov type ■; MOS type differential amplifier circuit of the type shown in Figure 7,
Gate input φA of FET Q138 is 1.8V type ■; MOS type differential amplifier circuit of the type shown in Figure 7,
The gate force φA of FET 013g is 5. Ov In addition, P channel FET Q130. Threshold value VT of Q134, , h −Q , gV, N channel tL,
FE TQ132. Q136. Q138 (7) Threshold vTH was set to +○ and 8V, respectively.

Types I and II where φA is 1.6V [FET Q1
38 is operated in the saturation region. For types ■ and ■ where φA is 5.0”■, FET Q138 will be operated in the linear region.

Figure 9 shows each area, and FETQ138
The region where the drain current Id monotonically increases with respect to the drain-source potential pvds is the linear region, and the region where it is saturated is the saturated region. Expressed as a relational expression, vds<vGS
-vTH, it becomes a linear region, and when vdS>vo8-vlH, it becomes a saturated region.

As a process variation, we considered the case where the β ratio changed. Figure 10 shows P-channel FETs Q130 and Q13.
4 shows changes in DC amplification with respect to variations in gate width. Wo is the design value of the gate width, and W is its actual value. Bitline BL.

The potential difference between BL' is ΔV BIMOS amplifier circuit IN
' If the potential difference between the outputs of ' is ΔV, it is a tie.

For UT ■, the operating point changes little even if the β ratio shifts, and the amplification degree of the BIMOS amplifier circuit does not change even with a variation of about 30%, but for types ■ and ■, the operating point changes significantly when the β ratio changes. It can be seen that the degree of amplification decreases. From this result, it can be seen that types I and (2) of the current mirror configuration, in which the output is fed back to the gates of the load FETs Q130 and Q134, are excellent in maintaining the amplification degree against variations in process parameters.

゛Figure 11 shows the center potential VM of the bit lines BL and BL'.
This shows the change in DC amplification when .

In this case, it can be seen that the method (2) using FET Q138 as a constant current wind is superior. Ri Eve ■ also 1
For input potential deviations of about ±0.4 V from -vcc, the amplification degree changes by about 10%. 1. if desired.
A type H type that does not require a 6V generation circuit can be used. Furthermore, from the results shown in Figure 10, Mo5pE for activation
% Current mirror type MO without Q138
5 type differential will increase. In this simulation, the bipolar transistors 71g and T of the BIMO3 differential amplifier circuit 212
Set the emitter size of 2O to 2X5μ, hPE and Vc.
c-5V% precharge level of each bit line"-
y cc, potential difference ΔV between pit lines BL and BL',
N" 50 mV. However, other embodiments may be used.

Although nine embodiments of the present invention have been described above, various other modifications can be made.

[Effects of the Invention] As explained above, according to the present invention, an excellent dRAM device can be provided.

[Brief explanation of drawings]

Figures 1 and 2 are diagrams of the first embodiment of the present invention, Figure 3,
FIG. 4 is a diagram of the second embodiment, FIG. 5 is a diagram showing a modification,
Figures 6, 7, 8, and 9. FIG. 10 and FIG. 11 are diagrams explaining other embodiments, and FIG.
The figure shows a conventional example.

Claims (7)

[Claims] (1) A plurality of pairs of bit lines provided on the substrate, a plurality of word lines intersecting the bit lines, and an MO provided at the intersection between the bit lines and the word lines.
a memory cell consisting of an S transistor and a capacitor;
a MOS flip-flop circuit connected to the bit line pair for rewriting read data; a MOS differential amplifier circuit connected to the bit line pair in parallel with the MOS flip-flop circuit; 1. A dynamic semiconductor memory device comprising: a BIMOS differential amplifier circuit connected to an amplifier circuit, which amplifies a potential difference between bit lines, outputs the amplified potential difference to an output line, and inputs the BIMOS type differential amplifier circuit to the MOS flip-flop circuit. (2) A plurality of pairs of bit lines provided on the substrate, a plurality of word lines intersecting the bit lines, and an MO provided at the intersection between the bit lines and the word lines.
a memory cell consisting of an S transistor and a capacitor;
a MOS flip-flop circuit connected to the bit line pair for rewriting read data; a MOS differential amplifier circuit connected to the bit line pair in parallel with the MOS flip-flop circuit; It is connected to the amplifier circuit, is pre-activated by the row address strobe signal, and is activated by the column address strobe signal, and amplifies the potential difference between the bit lines and outputs it to the output line, and is also connected to the MOS flip-flop circuit. A dynamic semiconductor memory device comprising a BIMOS differential amplifier circuit for input. (3) The dynamic type semiconductor according to claim 2, wherein the MOS differential amplifier circuit is pre-activated by a row address strobe signal, and activation is promoted by a column address strobe signal. Storage device. (4) A plurality of pairs of bit lines provided on the substrate, a plurality of word lines intersecting the bit lines, and an M provided at the intersection between the bit lines and the word lines.
a memory cell consisting of an OS transistor and a capacitor; a MOS flip-flop circuit connected to the bit line pair for rewriting read data; and a load MOS connected to the bit line pair in parallel with the MOS flip-flop circuit. A MOS differential amplifier circuit has a configuration in which the output is fed back to the gate of a transistor, and a BIMOS differential amplifier circuit is connected to this MOS differential amplifier circuit and amplifies the potential difference between bit lines and outputs the amplified potential difference to an output line. A dynamic semiconductor memory device characterized by comprising: (5) A plurality of pairs of bit lines provided on the substrate, a plurality of word lines intersecting the bit lines, and an M provided at the intersection between the bit lines and the word lines.
a memory cell consisting of an OS transistor and a capacitor; a MOS flip-flop circuit connected to the bit line pair for rewriting read data; and an activation circuit connected to the bit line pair in parallel with the MOS flip-flop circuit. A MOS differential amplifier circuit configured such that the MOS transistors are operated in the saturation region, and a BIMOS differential amplifier circuit that is connected to this MOS differential amplifier circuit and amplifies the potential difference between bit lines and outputs the amplified potential difference to the output line. A dynamic semiconductor memory device comprising: (6) A plurality of pairs of bit lines provided on the substrate, a plurality of word lines intersecting the bit lines, and an M provided at the intersection between the bit lines and the word lines.
A memory cell consisting of an OS transistor and a capacitor, a MOS flip-flop circuit connected to the bit line pair and rewriting read data, and a MOS type difference connected to the bit line pair in parallel with the MOS flip-flop circuit. The present invention includes a dynamic amplification circuit and a BIMOS differential amplification circuit connected to the MOS differential amplification circuit and activated by a row address strobe signal that amplifies the potential difference between the bit lines and outputs the amplified potential difference to the output line. Dynamic semiconductor memory device with special features. (7) A plurality of pairs of bit lines provided on the substrate, a plurality of word lines intersecting the bit lines, and an M provided at the intersection between the bit lines and the word lines.
a memory cell consisting of an OS transistor and a capacitor; a MOS flip-flop circuit connected to the bit line pair for rewriting read data; and a load MOS transistor connected to the bit line pair in parallel with the MOS flip-flop circuit. The output is fed back to the gate of the MOS differential amplifier circuit, and the activation MOS transistor is operated in a linear region. A dynamic semiconductor memory device characterized by comprising a BIMOS type differential amplifier circuit that outputs to a line.