KR100316521B1 - Over drive circuit for semiconductor memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overdrive circuit of a semiconductor memory. In the related art, in order to apply a power supply voltage VDD and a drive voltage VDL to a sense amplifier, a power supply voltage level driver 4a and a drive voltage level driver 4b are provided. The driving units are located at the intersection of the sense amplifier array 2 and the subword driver 3, and the size of the driving unit is limited due to the small area of the crossing region. However, if the size of the driver is small, the time required to read the data of the cell is long, and thus there is a problem that adversely affects the performance of the memory. If the size of the power voltage level driver is too small, the bit line voltage is the driving voltage. It may take longer to write data to the cell because it takes longer to overdrive (VDL) and fall back to the driving voltage (VDL) level. On the contrary, if the size is too small, the bit line voltage goes to the VDL level. As the time taken to climb is longer than the cell data read time specification, it was difficult to determine the proper size ratio between the two driving units. Accordingly, the present invention integrates the power supply voltage level driver and the driving voltage level driver of the voltage applying unit of the memory array into one and drives the sense amplifiers to the power supply voltage level and the driving voltage level by one of the driving units, thereby maximizing the area in the narrow crossing area. It can overdrive while increasing the efficiency, combining two wires for the conventional power supply voltage (VDD) and the driving voltage (VDL) into one, reducing the resistance of the power supply wiring and increasing the size of the high voltage driver of the voltage applying unit. There is an effect that the speed of the amplifier amplification becomes easy.

Description

OVER DRIVE CIRCUIT FOR SEMICONDUCTOR MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overdrive circuit of a semiconductor memory, and in particular, when amplifying a sense amplifier, an overdrive can be performed by one MOS transistor without separately using an MOS transistor for an overdrive and a MOS transistor for a normal drive. The present invention relates to an overdrive circuit of a semiconductor memory that enables overdrive while increasing the maximum area efficiency in a narrow crossing area.

FIG. 1 is a schematic internal configuration diagram of a conventional semiconductor memory, and as shown therein, a memory cell array 1 for storing data; A sense amplifier array 2 for amplifying and outputting information of the memory cell 1; A subword driver 3 for driving the sub word line; And a voltage applying unit 4 for applying a voltage for driving the sense amplifier array 2 in a region where the sense amplifier array 2 and the subword driver 3 intersect.

The voltage applying unit 4 includes: a power supply voltage level driver 4a for amplifying the difference between the minute voltage levels of the bit line on which the data of the sense amplifier and the bit line on which the sense amplifier data is not loaded, i.e., overdrives the power supply voltage VDD level; A driving voltage level driver 4b for driving the bit line voltage of the sense amplifier to the driving voltage VDL level; And a ground level driver 4c for driving the bit line voltage of the sense amplifier to the ground (VSS) level.

In this case, each NMOS transistor of the sense amplifier array 2 is connected to a low voltage node CSN, and each PMOS transistor is connected to a high voltage node CSP to provide voltages of the low voltage node CSN and the high voltage node CSP. The signal of the sense amplifier is amplified by changing from the precharge voltage VDL / 2 to the ground VSS level and the driving voltage VDL level, respectively.

Generally, 3.3 volts is used as an external power supply voltage for the memory (64MDRAM), and a lower voltage than the power supply voltage (VDD) is used as the driving voltage (VDL) used for the memory array. In circuits that require high voltage (VPP), such as word lines, voltages higher than the supply voltage (VDD) (between 3.6 and 3.8 volts) are commonly used.

In addition, the NMOS transistor NM1 not described above prevents the power supply voltage VDD from being directly connected to the memory array and sets the voltage connected to the memory array (the threshold of the high voltage VPP-NMOS transistor NM1). The clamp is for clamping to the voltage VT level, and the driving voltage VDL is generated by a driving voltage generator (not shown) and applied to the memory array.

On the other hand, in the process of reading the data of the bit line in the sense amplifier, first, the word line to which the cell to be read is enabled is enabled so that the data stored in the cell is stored in the bit line (bit line capacitive load (CB) / cell capacity). After a sufficient time, the high voltage level driving signal (SAP) and ground level driving signal (SAN) are enabled and the bit line signal is driven to the driving voltage (VDL) and ground voltage (VSS). ) Overdrive to reduce the time it takes to change to level.

This will be described in more detail with reference to the waveform diagram of FIG. 2 as follows.

As shown in FIG. 2, the signal waveform at the time of overdrive is first enabled by the power voltage level driving signal SAPOV, so that the power voltage VDD is applied to the high voltage node CSP for the first time through the power voltage level driver 4a. By driving to the level, the bit line voltage is quickly 'high'. When disabled, the high voltage level driving signal SAP is enabled to stabilize the bit line voltage to the driving voltage VDL level.

In this case, the ground level driving signal SAN is always enabled, so that the low voltage node CSN of the sense amplifier is turned low so that the minute signal of the sense amplifier is amplified to the driving voltage VDL level and the ground VSS level.

However, in the related art, in order to apply the power supply voltage VDD and the driving voltage VDL to the sense amplifier, the power supply voltage level driver 4a and the driving voltage level driver 4b should be provided separately. It is located in the intersection area of the sense amplifier array 2 and the subword driver 3, but the area of this intersection area is small, thereby limiting the size of the driver.

However, the time taken for the amplification of the bit line signal is much more influenced by the size of the driver in the cross region than the size of the sense amplifier's NMOS and PMOS transistors. Since the time is long, there is a problem that adversely affects the performance of the memory, and if the size of the power supply voltage level driver is too small, the bit line voltage is overdriven above the driving voltage (VDL) and then again the driving voltage (VDL). The long time it takes to fall to the level can cause problems when writing data to the cell. On the contrary, if the size is too small, the time required for the bit line voltage to rise to the driving voltage (VDL) level becomes long, which leads to the reading of the cell data. As the time becomes longer than the specification, it is difficult to determine the proper size ratio between the two driving parts. It was.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and integrates the power supply voltage level driver and the driving voltage level driver of the voltage applying unit into one, and the sense amplifier is connected to the power supply voltage level and the driving voltage by the one driver. The purpose is to provide an overdrive circuit of a semiconductor memory that can be overdriven while increasing the maximum area efficiency at a narrow crossing area by driving at a level.

1 is a schematic internal configuration diagram of a conventional semiconductor memory.

2 is a timing diagram for explaining a conventional overdrive process.

3 is a schematic configuration diagram of an overdrive circuit of a semiconductor memory according to the present invention;

4 is a timing diagram for explaining an overdrive process according to the present invention;

*** Description of the symbols for the main parts of the drawings ***

10: high voltage drive unit 11: ground level drive unit

100: applied voltage selector

The present invention for achieving the above object, the memory cell array for storing data; A sense amplifier array for amplifying and outputting information of the memory cells; A subword driver for driving the sub word line; A semiconductor memory comprising a voltage applying unit for applying a voltage for driving the sense amplifier array in an area where the sense amplifier array and a subword driver cross each other, wherein the voltage applying unit is a power supply voltage VDD or a driving voltage VDL. A high voltage driver for applying the voltage to the sense amplifier array; A ground level driver configured to drive the bit line voltage of the sense amplifier to a ground (VSS) level, and an applied voltage selector configured to selectively apply a power supply voltage VDD and a driving voltage VDL to the voltage applying unit. It is achieved by further comprising, when described in detail with reference to the accompanying drawings an embodiment according to the present invention.

FIG. 3 is a schematic internal configuration diagram of a semiconductor memory according to the present invention, and as shown therein, a memory cell array 1 for storing data; A sense amplifier array 2 for amplifying and outputting information of the memory cell 1; A subword driver 3 for driving the sub word line; A semiconductor memory comprising a voltage applying unit (4) for applying a voltage for driving the sense amplifier array (2) in a region where the sense amplifier array (2) and the subword driver (3) intersect. The applying unit 4 includes a high voltage driving unit 10 for applying a power supply voltage VDD or a driving voltage VDL to the sense amplifier array 2; And a ground level driver 11 which drives the bit line voltage of the sense amplifier to the ground (VSS) level, and selectively applies the power voltage VDD and the driving voltage VDL to the voltage applying unit 4. It is configured to further include an applied voltage selection unit 100 to be.

In addition, the applied voltage selector 100 may include a PMOS transistor PM1 receiving a high voltage VPP to a source; An NMOS transistor NM3 connected in series with the PMOS transistor PM1, receiving a driving voltage VDL to a source, and receiving an overdrive signal OVPB in common to its gate; An NMOS transistor NM1 connected to a common connection point of the two transistors NM3 and PM1 with a source voltage VDD applied to a drain thereof and whose source connected to the voltage applying unit 4; The driving voltage VDL is applied to the drain, the overdrive signal OVPB is applied to the gate, and the source is composed of the NMOS transistor NM2 connected to the source of the NMOS transistor NM1. The operation and operation of the present invention configured as described will be described.

First, the operation of reading the sense amplifier by the overdrive according to the present invention will be described with reference to FIG.

First, when a row active command and a row address enter the memory array, it is decoded to enable which word line to enable, so that the word line is enabled. In this case, as shown in FIG. 4, the overdrive signal OVPB is also 'low' to apply the high voltage VPP level to the gate of the NMOS transistor NM1 so that the power supply voltage VDD is transferred into the memory array. .

In this case, since the high voltage level driving signal SAP is 'low', the amplification of the sense amplifier does not occur. In addition, since the NMOS transistor NM2 connected to the driving voltage VDL is turned off, the driving voltage VDL is not transferred into the memory array.

Meanwhile, since the NMOS transistor NM1 to which the power supply voltage VDD is connected has a large size, a large amount of high voltage VPP current is required to turn on the NMOS transistor NM1, and the turn-on time of the NMOS transistor NM1 to which the power supply voltage VDD is connected is turned on. Since it only needs to occur for several tens of nanoseconds (nsec) from the low active command to the point where the actual sense amplifier amplification occurs, by dispersing and turning on the NMOS transistor NM1 outside the power supply unit 4 of the memory array. It can prevent the sudden high voltage (VPP) current from flowing at a moment.

On the other hand, when the overdrive signal (OVPB) transitions to 'low', the preparation of the overdrive operation of the sense amplifier is finished, and the high voltage level driving signal (SAP) is generated after the cell signal fully charges / discharges the bit line. When the high voltage driver 10 of the voltage applying unit 4 of the array is turned on to make the high voltage node CSP 'high', and the ground level driver 20 is turned on to make the low voltage node CSN to the ground VSS level. The amplification of the sense amplifier due to the overdrive occurs.

Next, when the amplification of the sense amplifier sufficiently occurs at the driving voltage VDL and the ground VSS level, the overdrive signal OVPB is transitioned to 'high' to turn off the PMOS transistor PM1 and the NMOS transistor ( The NM2 is turned on to allow the bit line voltage to stabilize to the driving voltage VDL and ground VSS levels.

At this time, the source of the NMOS of the inverter to which the overdrive signal OVPB is connected to the VDL power source is to reduce power consumption of the high voltage VPP.

Since the gate voltage of the NMOS transistor NM1 swings from the high voltage VPP to the driving voltage VDL level, power consumption of the high voltage VPP can be reduced by about half.

By reducing the two driving units in the voltage applying unit 4 as described above, the size of the power supply voltage level driving unit 10 can be increased by that amount, making it easier to satisfy the timing margin of the memory cell read operation and the bit line. Even if it is overdriven beyond the drive voltage VDL level, it is much easier to return to the drive voltage VDL level again.

As described above, the overdrive circuit of the semiconductor memory according to the present invention integrates the power supply voltage level driver and the driving voltage level driver of the voltage applying unit of the memory array into one, and the driver drives the sense amplifier to the power supply voltage level and the driving voltage level. By driving, it is possible to overdrive while increasing the maximum area efficiency in a narrow crossing area, reducing the resistance of the power supply wiring by combining two wires for the conventional power supply voltage (VDD) and the driving voltage (VDL) into one, and the high voltage of the voltage application unit. Since the size of the driving unit can be increased, the amplification of the sense amplifier can be easily increased.

Claims (2)

A memory cell array for storing data; A sense amplifier array for amplifying and outputting information of the memory cells; A subword driver for driving the sub word line; A semiconductor memory comprising a voltage applying unit for applying a voltage for driving the sense amplifier array in an area where the sense amplifier array and a subword driver cross each other, wherein the voltage applying unit is a power supply voltage VDD or a driving voltage VDL. A high voltage driver for applying the voltage to the sense amplifier array; A ground level driver configured to drive the bit line voltage of the sense amplifier to a ground (VSS) level, and an applied voltage selector configured to selectively apply a power supply voltage VDD and a driving voltage VDL to the voltage applying unit. The overdrive circuit of the semiconductor memory further comprises. The PMOS transistor of claim 1, further comprising: a PMOS transistor (PM1) configured to receive a high voltage (VPP) from a source; An NMOS transistor NM3 connected in series with the PMOS transistor PM1, receiving a driving voltage VDL to a source, and receiving an overdrive signal OVPB in common to its gate; An NMOS transistor NM1 connected to a common connection point of the two transistors NM3 and PM1 with a source voltage VDD applied to a drain thereof and whose source connected to a voltage applying unit; The driving voltage VDL is applied to the drain, the overdrive signal OVPB is applied to the gate, and the source is configured by the NMOS transistor NM2 commonly connected to the source of the NMOS transistor NM1. An overdrive circuit for a semiconductor memory.