KR100834390B1 - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor design technology, and according to an aspect of the present invention, a plurality of bit line sensing amplifiers disposed in the bit line sensing amplifier array region and sharing a pull-up power line and a pull-down power line; A normal driver disposed in a sub-hole region for driving the pull-up power line with a normal driving voltage; And a plurality of overdrivers disposed in the bit line sensing amplifier array area corresponding to each bit line sensing amplifier and configured to drive the pull-up power supply line with an overdriving voltage.

Bitline Sense Amplifiers, Overdrivers, Normal Drivers, PMOS Transistors, NMOS Transistors

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

1 is a plan view showing a semiconductor memory device according to the prior art.

FIG. 2 is a circuit diagram illustrating the bit line sense amplifier array of FIG. 1. FIG.

3 illustrates the concept of a bit line sense amplifier array in accordance with an embodiment of the present invention.

4 is a circuit diagram illustrating the bit line detection amplifier array of FIG.

FIG. 5A is a diagram illustrating a case in which over drivers 411a and 411b and a normal driver 413 implemented as PMOS transistors in FIG. 4 are implemented as NMOS transistors.

FIG. 5B is a diagram illustrating a case in which a normal driver 413 implemented as a PMOS transistor in FIG. 4 is implemented as an NMOS transistor.

FIG. 5C is a diagram illustrating a case where the overdrivers 411a and 411b implemented as PMOS transistors in FIG. 4 are implemented as NMOS transistors.

Explanation of symbols on the main parts of the drawings

301: bit line detection amplifier array 303: sub-hole area

305, 307: Overdriver 309, 311: Unit bit line detection amplifier

313: normal driver 315: pull-down driver

317: Power line precharge section

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a bit line sensing amplifier array of a semiconductor memory device.

As the scaling and down of the line width and the cell size continue to progress in the current semiconductor memory device, the voltage reduction of the power supply voltage is accelerated, and accordingly, a design technique for satisfying the performance required in a low voltage environment is required.

Most semiconductor memory devices are provided with an internal voltage generator circuit for generating an internal voltage by applying an external voltage (power supply voltage) to supply a voltage necessary for the operation of the chip internal circuit. In particular, in the case of a memory device using a bit line sensing amplifier such as DRAM, a core voltage VCORE is used to detect cell data.

However, if only the core voltage VCORE is used in a DRAM where the operating voltage decreases, it is difficult to amplify the data of many cells in a short time.

To solve this problem, the pull-up power line of the bit line sense amplifier is initially connected to a voltage higher than the core voltage (VCORE) for a certain period of time at the beginning of operation of the bit line sense amplifier immediately after the charge sharing between the memory cell and the bit line. It adopts a bit line sense amplifier overdriving method which is driven by voltage (VDD).

A semiconductor memory device employing such an overdriving method will now be described.

1 is a plan view illustrating a semiconductor memory device according to the prior art.

Referring to FIG. 1, a semiconductor memory device may be divided into a cell region and a sub-hole region among various regions, wherein the cell region includes a cell array including a word line (WL) and a bit line (BL). A typical cell array includes a sub word line driver SWD for driving a word line WL, and a plurality of unit bit line detection amplifiers for sensing and amplifying data carried on the bit line BL. Typical bit line sense amplifier arrays are the bit line sense amplifier drivers that drive the pull-up and pull-down power lines of the bit line sense amplifier array.

Here, the bit line detection amplifier array will be described.

FIG. 2 is a circuit diagram illustrating the bit line detection amplifier array of FIG. 1.

Referring to FIG. 2, the bit line detection amplifier array includes a plurality of unit bit line detection amplifiers 201 and 203, wherein a plurality of unit bit line detection amplifiers are prepared, but for convenience of description, the singular description will be given below. The device may further include bit line precharge units 205 and 207 that correspond to the unit bit line detection amplifiers 201 and 203 and precharge the bit line.

This shows a bit line detection amplifier array. To control this, the power lines RTO and SB of the unit bit line detection amplifiers 201 and 203 are connected to a core voltage (VCORE, = normal driving voltage) and a power supply in the sub-hole area. A normal driver 213, an overdriver 211, and a pull-down driver 215 for driving with the voltage VDD (= overdriving voltage) and the ground voltage VSS are provided. Here, reference numeral 209 denotes a unit bit line sensing amplifier power line precharge unit 209 for precharging the power lines RTO and SB of the unit bit line sensing amplifiers 201 and 203.

In this case, the normal driver 213 is driven by the normal driving signal SAP2, the overdriver 211 is driven by the overdriving signal SAP1, and the pull-down driver 215 is driven by the pull-down driving signal SAN. Driven.

Here, the unit bit line detection amplifiers 201 and 203 perform a sensing operation by using the pull-up power line RTO in common. That is, the overdriving operation is performed during the initial predetermined period of the sensing operation period, and then the normal driving operation is performed thereafter to improve the sensing efficiency.

However, since the apparatus for controlling the overdriving operation is provided in the sub-hole area and shares the output (normal driving voltage or overdriving voltage), the sub driver including the over driver 211 and the normal driver 213 is provided. The unit bit line detection amplifier relatively far from the hall region performs an overdriving operation with a potential reduced by the loading of the power line of the unit bit line detection amplifier. Therefore, a difference in sensing speed and sensing efficiency occurs.

In addition, since a common node called a pull-up power line (RTO) is a shared node between a plurality of unit bit line sensing amplifiers 201 and 203, the PMOS transistor is generally vulnerable to a mesh shape so that low power is generally used. When the pull-up power supply line (RTO) and the power supply voltage (VDD) are connected to the over-driver 211 using the vulnerable to the voltage drop due to power consumption.

The present invention is proposed to solve the problems of the prior art as described above, while receiving a bit line sensing amplifier driving voltage supplied from one side, a semiconductor memory device for solving the problem that the operation efficiency difference caused by the loading difference of the supply line To provide a first object.

Another object of the present invention is to provide a semiconductor memory device in which a plurality of bit line detection amplifiers have the same overdriving operation efficiency.

A third object of the present invention is to provide a semiconductor memory device that solves a voltage drop problem due to a pull-up power line vulnerable to a mesh shape.

According to an aspect of the present invention for achieving the above technical problem, a plurality of bit line sensing amplifiers disposed in the bit line detection amplifier array region, and sharing the pull-up power line and the pull-down power line; A normal driver disposed in a sub-hole region for driving the pull-up power line with a normal driving voltage; And a plurality of overdrivers disposed in the bit line sensing amplifier array area corresponding to each bit line sensing amplifier and configured to drive the pull-up power supply line with an overdriving voltage.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 illustrates a concept of a bit line detection amplifier array according to an embodiment of the present invention.

Referring to FIG. 3, the bit line sensing amplifier array 301 is provided with a number and positions corresponding to the plurality of unit bit line sensing amplifiers 309 and 311 and the plurality of unit bit line sensing amplifiers 309 and 311. n units (where n units are only numbers for convenience of explanation, which are ranges that do not reduce the operation efficiency due to the loading difference of the bit line sensing amplifier power lines in which the unit bit line sensing amplifiers are connected in parallel). And over-drivers 305 and 307 provided in positions and numbers corresponding to the unit bit line detection amplifier blocks.

As a sub-hole region 303 for controlling the bit line detection amplifier array 301, a normal driver for driving a pull-up power supply line and a pull-down power supply line, which are common power lines of the bit line detection amplifier array 301, are used. 313 and a pull-down driver 315 are provided.

3, the concept of the present invention can be grasped. That is, a plurality of overdrivers provided to partially correspond to the first unit bit line detection amplifier 311 and the last unit bit line detection amplifier 309 or to correspond to the respective unit bit line detection amplifiers 311 and 309. 305 and 307 match the operating efficiency of the plurality of unit bit line detection amplifiers 311 and 309.

When explaining such a conceptual diagram in more detail as follows.

4 is a circuit diagram illustrating a bit line detection amplifier array of FIG. 3.

Referring to FIG. 4, the bit line detection amplifier array includes a plurality of unit bit line detection amplifiers 401 and 403, in which a plurality of unit bit line detection amplifiers are provided, but for convenience of description, the singular description will be given below. It consists of over-drivers 411a, 411b provided in a position and a number corresponding to the unit bit line detection amplifiers 401, 403. The device is further provided to correspond to the unit bit line detection amplifiers 401, 403. Bit line precharge units 405 and 407 are provided to precharge the bit lines. In this case, the overdrivers 411a and 411b are provided in positions and numbers corresponding to the respective unit bit line detection amplifiers 401 and 403, but are partially provided on the common power lines of the unit bit line detection amplifiers 401 and 403. (Partially within a range in which an overdriving efficiency difference of each of the unit bit line detection amplifiers 401 and 403 does not occur).

Up to this point, the bit line detection amplifier array is shown. To control this, the power lines RTO and SB of the unit bit line detection amplifiers 401 and 403 are connected to the core voltage (VCORE, = normal driving voltage) and ground in the subhole area. A normal driver 413 and a pull-down driver 415 for driving with the voltage VSS are provided. Here, reference numeral 409 denotes a unit bit line sense amplifier power line precharge unit 409 for precharging the power lines RTO and SB of the unit bit line sense amplifiers 401 and 403.

At this time, the normal driver 413 is driven by the normal driving signal SAP2, the overdrivers 411a and 411b are driven by the overdriving signal SAP1, and the pull-down driver 415 is the pull-down driving signal SAN. Driven by).

Here, the unit bit line detection amplifiers 401 and 403 perform a sensing operation by using the pull-up power line RTO in common. That is, the overdriving operation is performed during the initial predetermined period of the sensing operation period, and then the normal driving operation is performed thereafter to improve the sensing efficiency.

In addition, the overdrivers 411a and 411b, the normal driver 413, and the pull-down driver 415 may be implemented as PMOS transistors.

The structural features of the present invention are conventionally provided with an overdriver on the one side of the unit bit line detection amplifiers 401 and 403, but the position corresponding to the unit bit line detection amplifiers 401 and 403 in the present invention. And an overdriver in part within a range in which the number of overdriving efficiencies of the number or unit bit line detection amplifiers 401 and 403 does not occur.

Subsequently, the operation of the bit line detection amplifier array will be described.

Since the bit lines and the memory cells share charges, data is loaded on the bit lines, and the unit bit line detection amplifiers 401 and 403 operate to amplify them. At this time, in the amplification operation of the unit bit line detection amplifiers 401 and 403, the overdrive signal SAP1 is activated for the overdriving operation in the initial operation section, and the overdrivers 411a and 411b are driven. The normal driving signal SAP2 is activated for the driver operation so that the normal driver 413 is driven to perform an amplification operation.

As a result, in terms of structure, the position and number corresponding to the plurality of unit bit line detection amplifiers 401 and 403 or the amount of overdriving efficiency difference between the unit bit line detection amplifiers 401 and 403 do not occur. The overdrivers 411a and 411b are provided so that an overdriving efficiency difference between the unit bit line detection amplifiers 401 and 403 does not occur.

In addition, when a problem occurs in the overdrivers 411a or 411b separately, a plurality of overdrivers may be provided to prevent malfunctions of the unit bit line detection amplifiers 401 and 403.

In addition, the pull-up power supply line (RTO) driven by a conventional voltage supply source (meaning the power supply voltage (VDD)) is vulnerable to the mesh (mesh) form a problem that the voltage drop occurs in the present invention, pull-up power supply The line RTO is provided with a plurality of voltage sources (meaning a power supply voltage VDD) by a plurality of overdrivers 411a and 411b to solve the above problem.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, since the type and arrangement of the logic used in the above-described embodiment is implemented as an example in which both the input signal and the output signal are high active signals, the implementation of the logic may also change when the active polarity of the signal is changed. There is no such embodiment, because the number of cases is too large, and the change in the embodiment is a matter that can be easily technically inferred by those skilled in the art of the present invention belongs directly to each case I will not mention it.

In addition, in the above-described embodiment, the overdrivers and the normal driver have been described as an example of implementing a plurality of logic circuits, but this is also merely one implementation.

5A is a diagram illustrating a case in which the over drivers 411a and 411b and the normal driver 413 implemented as PMOS transistors in FIG. 4 are implemented as NMOS transistors.

As such, when the over drivers 511a and 513b and the normal driver 413 are implemented as the NMOS transistor, it is necessary to turn on the voltage at least as high as the threshold voltage than the power supply voltage VDD.

When the NMOS transistor is applied as described above, power consumption increases, but in general, since the PMOS transistor is an electron carrier, the number of electrons per unit area is smaller than that of the NMOS transistor. Therefore, under the assumption that the same driving current is obtained, since the NMOS transistor is implemented with a smaller area than the PMOS transistor, the size of the semiconductor memory device can be reduced.

FIG. 5B is a diagram illustrating a case in which the normal driver 413 implemented as a PMOS transistor in FIG. 4 is implemented as an NMOS transistor.

Compared to the normal driver 613, the overdrivers 611a and 611b which have relatively more loadings reduce power consumption using PMOS transistors, and implement the sub-holes by implementing the normal driver 613 as an NMOS transistor. Reduce the area of the area

FIG. 5C is a diagram illustrating a case where the over drivers 411a and 411b implemented as PMOS transistors in FIG. 4 are implemented as NMOS transistors.

This is to reduce the area of the bit line detection amplifier array and to reduce power consumption with the normal driver 713 implemented with PMOS transistors.

As described above, the present invention does not generate an over-driving efficiency difference between the unit bit line sensing amplifiers, thereby achieving an effect of stable overdriving operation of the unit bit line sensing amplifier and speed improvement of the semiconductor memory device.

In addition, when a problem occurs in the overdriver and does not operate individually, since a plurality of overdrivers are provided, malfunctions of the unit bit line detection amplifiers can be prevented.

In addition, it is possible to solve the voltage drop problem due to the pull-up power line vulnerable to the mesh shape, it is possible to obtain a power saving effect.

Finally, the over driver and the normal driver may be implemented as PMOS or NMOS transistors to obtain the area reduction and power consumption reduction effect of the semiconductor memory device.

Claims (6)

delete A plurality of bit line sensing amplifiers disposed in the bit line sensing amplifier array area and sharing a pull up power line and a pull down power line; A normal driver disposed in a sub-hole region for driving the pull-up power line with a normal driving voltage; And A plurality of overdrivers disposed in the bit line sense amplifier array area corresponding to each bit line sense amplifier to drive the pull-up power line with an overdriving voltage; A semiconductor memory device having a. The method of claim 2, The plurality of over drivers are each an NMOS transistor or a PMOS transistor. The method of claim 2, And the normal driver is an NMOS transistor or a PMOS transistor. The method of claim 3, And the driving voltage is a boost voltage when the plurality of over drivers are NMOS transistors. The method of claim 4, wherein And the driving voltage is a boost voltage when the normal driver is an NMOS transistor.

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