JPH0787035B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a structure of a semiconductor memory device capable of significantly shortening access time and realizing a high-speed read operation.

[Prior Art] In a highly integrated memory device such as a dynamic MOSRAM (random access memory using a MOS transistor) in recent years, the access time (the time required for data reading) is significantly shortened with the high integration. By doing so, it is desired to speed up the read operation.

FIG. 4 is a diagram conceptually showing an example of a memory cell and sense amplifier structure in a pair of bit lines in a conventional dynamic random access memory (hereinafter referred to as DRAM) in a simplified manner. In FIG. 4, bit lines
BL and ▲ ▼ form a pair to form a folded bit line pair. That is, mutually complementary signals appear on the bit line BL, ▲ ▼. A plurality of word lines are provided in the direction orthogonal to the bit lines BL, ▲ ▼. However, in FIG. 4, only one word line WL is representatively shown. Memory cells are provided at the intersections of the word lines and the bit lines, and the memory cells are arranged in rows and columns. Further, in the figure, only one memory cell 1 provided at the intersection of the bit line BL and the word line WL is representatively shown. The memory cell 1 has a one-transistor / one-capacitor type configuration, and is turned on in response to a memory capacity C0 for storing information and a signal provided on the word line WL, and the memory cell capacity C0 is transferred to the bit line BL. N channel MIS (metal-
(Insulating film-semiconductor) transistor Q0.

Flip-flop type sense amplifiers 2 and 3 are provided in order to amplify the signal potential difference on the bit line pair BL and ▲ ▼. The sense amplifier 2 is an N-channel MIS transistor Q1, Q2
And discharges the bit line potential on the low potential side to the ground potential. The MIS transistor Q1 has a gate connected to the bit line BL and a drain connected to the bit line ▲ ▼. MI
The gate of the S transistor Q2 is connected to the bit line ▲ ▼, and the drain is connected to the bit line BL. The sources of the MIS transistors Q1 and Q2 are connected to the node N1. Node N1
A sense amplifier activating means 4 for activating the sense amplifier 2 in response to the sense amplifier activating signal S0 is connected to. The sense amplifier activating means 4 is turned on in response to the sense amplifier activating signal S0 and comprises an n-channel MIS transistor Q5 connecting the node N1 to the ground potential.

The sense amplifier 3 is composed of p-channel MIS transistors Q3 and Q4, is activated in response to a signal from the sense amplifier activating means 5, and charges the bit line potential on the high potential side to the power supply potential Vcc. The gate of MIS transistor Q3 is connected to bit line BL, and the gate of MIS transistor Q4 is connected to bit line ▲ ▼. One of the conduction terminals of the MIS transistors Q3 and Q4 is connected to the bit lines ▲ ▼ and BL, respectively.
On the other hand, the conduction terminals are commonly connected to the node N2. Node N2
The output of the sense amplifier activating means 5 is transmitted. The sense amplifier activation means 5 has a sense amplifier activation signal ▲
In response to ▼, it is turned on and the power supply potential Vcc is applied to node N2.
Is formed of a p-channel MIS transistor Q6 for transmitting the signal.

Precharge / equalize means 6 is provided for precharging and equalizing the potentials on the bit line pair BL, {circle around (1)} in response to the equalize signal EQ. The equalizing / precharging means 6 is turned on in response to the equalizing signal EQ and electrically shorts the bit line pair BL, ▲ ▼, and an equalizing N-channel MIS transistor Q7.
The precharge N-channel MIS transistor Q8 which transmits the precharge potential V _BL onto the bit line BL in response to the equalize signal EQ, and the ON state in response to the equalize signal EQ, and the precharge potential V _{BL changes} to the bit line ▲ ▼ N9 MIS transistor for precharge to be transmitted to the top MIS transistor Q9
Composed of and. Normally, precharge potential V _BL is generated by an internal voltage generating circuit and set to a predetermined potential (for example, half of power supply voltage Vcc, that is, Vcc / 2 potential).

Further, each bit line BL, ▲ ▼ is turned on in response to a bit line pair selection signal (column decode signal) Y from a column decoder (not shown), and the bit line BL, ▲
N channel MIS transistors Q10 and Q11 are provided for connecting ▼ to the data input / output bus I / O and ▲ ▼, respectively. Data input / output bus pair I / O, ▲ ▼ are normally N-channel MIS that are turned on in response to the clock signal CLK.
The transistors Q22, Q23 are precharged to a predetermined potential V _'BL. The data input / output bus pair I / O, ▲ ▼ exchanges data via the input / output buffer.

FIG. 5 is a signal waveform diagram showing the operation of the semiconductor memory device shown in FIG. 4, and the same symbols as the signals shown in FIG. 4 show the waveforms of the respective signals. The operation of the conventional semiconductor memory device will be described below with reference to FIGS. 4 and 5.

At time T1, when the equalizing signal EQ falls from high level to low level, the MIS transistors Q7, Q8, Q9 are turned off, the precharge and equalizing operations of the bit line BL, ▲ ▼ are completed, and the bit line BL, ▲
▼ is in a floating state.

At time T2, when one word line WL is selected in response to the external address, the potential of the selected word line WL starts to rise. In response, the selected word line WL
The transistor Q0 of the memory cell 1 connected to is turned on, and a signal potential change occurs on the bit line BL, {circle around (▼)} according to the information of the memory cell 1. Here, in FIG. 5, the signal potential change on the bit line when the memory cell 1 stores the information “1” is shown by a solid line, and on the bit line when the memory cell 1 has the information “0”. The change in signal potential is indicated by the broken line.

When the read signal potential on the bit line pair BL, ▲ ▼ is fixed, at time T3, the sense amplifier activation signal S0, ▲
▼ starts to rise and fall respectively. As a result, the MIS transistors Q5 and Q6 are turned on, the node N1 is charged and discharged to the ground potential, and the node N2 is charged and discharged to the power supply potential Vcc.
As a result, the flip-flop type sense amplifiers 2 and 3 are both activated and the potential of the bit line BL on the higher potential side of the bit lines BL and ▲ ▼ is supplied to the power source potential Vcc via the sense amplifier 3.
, While the bit line (1) on the low potential side is discharged to the ground potential via the sense amplifier 2. That is, the sense amplifiers 2 and 3 are activated, so that the minute signal potential difference generated on the bit line pair BL, (3) is amplified.

After the amplifying operation of the sense amplifier, at time T4, when the bit line pair selection signal (column decode signal) Y from the column decoder becomes high level, the MIS transistors Q10, Q11
Is turned on, and the potential on the bit line BL, ▲ ▼ is transmitted to the data input / output bus I / O, ▲ ▼, respectively. The potential transmitted on this data input / output bus I / O, ▲ ▼ is then amplified by amplification means such as a preamplifier (not shown) and then transmitted to the outside through a data output buffer and an external output terminal (not shown). To be done.

When the transmission of the data to the external terminal is completed, the potential of the word line WL drops from the high level to the low level at time T5, and the level of the bit line pair selection signal Y also drops from the high level to the low level. This allows data I / O bus pair I /
The potential above O, ▲ ▼ returns to the precharge potential.

Next, at time T6, the sense amplifier activation signal S0, ▲
▼ changes from high level to low level and from low level to high level, respectively, and the sense amplifiers 2 and 3 are both inactivated. At this time, the equalize signal EQ becomes high level again, the precharge / equalize means 6 is activated, and the potential on the bit lines BL, ▲ ▼ is set to the predetermined potential V _BL.
Is precharged, and each bit line pair BL, ▲ ▼ potential is equalized.

The above operation is an outline of the operation at the time of reading data.
On the other hand, in the data write operation, the timing of the signal waveform is the same as that shown in FIG. 5, the data flow is in the opposite direction to that in the read, and the data input buffer → data input / output bus pair → selected. It becomes a memory cell. That is,
Write data externally supplied by a data write buffer (not shown) has a complementary form (for example, D _IN , ▲ ▼)
Is transmitted on the data input / output bus I / O, ▲ ▼. When the bit line selection signal Y changes from low level to high level at time T4 after the operation sequence from time T1 to T3, the MIS transistors Q10 and Q11 are turned on,
The signal potential on the data input / output bus pair I / O, ▲ ▼ is transmitted to the selected memory cell, which means that writing is performed. At this time, the sense amplifier
2 and 3 are also activated at time T3, and the signal potential on the bit line BL, ▲ ▼ is amplified by the transition of the word line WL to the high level. Since the write data is transmitted on the output bus I / O, ▲ ▼, even if the signal level amplified by the sense amplifiers 2 and 3 and the signal potential level of the write data are opposite, Signal potential appears on the bit line BL, ▲ ▼ in response to this, and this causes the write data to be written to the selected memory cell in the ON state of the MIS.
This will be done through transistor Q0.

[Problems to be Solved by the Invention] As described above, in the configuration of the conventional semiconductor memory device, the data input / output bus pair in which data reading and data writing are the same.
Since it is done via I / O, ▲ ▼, the bit line pair BL, ▲ ▼ and the data input / output bus pair I / O, ▲ ▼ also pass through the MIS transistors Q10, Q11 when reading data. Connected. For high-speed reading, it is preferable to connect the bit line pair and the data input / output bus pair as soon as possible. However, if the bit line pair and the data input / output bus pair are connected between the rise time T2 of the word line WL and the sense start time T3 when the sense amplifiers 2 and 3 are activated, the data input / output bus Since the load capacitance included in the bit line is added to the bit line, the read signal level on the bit line is lowered, and the sense amplifier cannot perform a reliable sensing operation, which may cause malfunction. Therefore, for the connection between the bit line pair and the data input / output bus pair, the sense amplifiers 2 and 3 are activated,
This must be done after the signal potential on the bit line pair BL, ▲ ▼ has been determined, and the connection between the selected bit line pair and the data input / output bus pair during data reading cannot be done before time T3. Therefore, there is a limit in increasing the speed of the read operation, and it is difficult to further shorten the access time. That is, in the case of a configuration in which the same data input / output bus pair is used for data reading and writing, there is a problem that it is difficult to shorten the access time during data reading.

Therefore, an object of the present invention is to eliminate the problems of the conventional semiconductor memory device as described above, to significantly shorten the access time, and to provide a semiconductor memory device capable of achieving high-speed reading. Is.

[Means for Solving the Problem] In the semiconductor memory device according to the present invention, a read-only data line pair and a write-only data line pair are separately provided, and each read-only data line pair has a predetermined number. Each of the bit line pairs and a plurality of sub data line pairs and a pair of main data line pairs commonly provided to the plurality of sub data line pairs. A read amplifier using the sub-data line pair as an output node and the bit line pair potential as its input signal is provided between the two. This read amplifier is activated by the column data output. The differential amplification type amplifier includes drive circuit means arranged for each bit line pair,
And a current load circuit means which is arranged corresponding to each sub-read data line pair and supplies a current to the corresponding sub-read data line pair, preferably a current mirror circuit. The drive circuit means is connected in series with each of the pair of variable conductance elements whose conductance changes according to the potential of the bit line on each bit line pair, and is connected in series with each of the pair of variable conductance elements. A variable conductance element and a pair of activation elements forming a current path between the first potential and the corresponding sub-read data line pair via the variable conductance element.

[Operation] The read amplifier amplifies a minute signal potential difference on the selected bit line at high speed without adversely affecting the bit line potential, and transmits it to the main data line pair via the output node (sub data line pair). Therefore, the information of the selected memory cell can be surely read onto the main data line before the sense amplifier is activated, and the access time at the time of data reading can be significantly shortened. Further, by providing each sub-read data line pair with a current supply means, which is preferably formed of a current mirror circuit, the load of the current supply means can be reduced and the data of the sub-read data line pair can be amplified at high speed. can do.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. In the following description, the same or corresponding parts as those of the conventional semiconductor memory device shown in FIG. 4 are designated by the same reference numerals.

FIG. 1 is a diagram schematically showing a configuration of a main part of a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1, bit line pair BL, ▲ ▼ is connected to flip-flop type sense amplifiers 2 and 3, precharge / equalize circuit means 1 and one transistor / one capacitor type memory cell 1 as in the conventional case. To be done. The bit line pair BL, ▲ ▼ is provided with MIS transistors Q10, Q11 which are turned on in response to a bit line pair selection signal (column decode signal) Y from a column decoder (not shown). .

Further, as in the conventional case, a sense amplifier activating transistor Q5 for generating a signal for activating the sense amplifier 2,
A sense amplifier activating transistor Q6 for generating a signal for activating the sense amplifier 3 is provided. Referring further to FIG. 1, in order to shorten the access time of the semiconductor memory device, a data line pair for transmitting only write data and a data line pair for transmitting only read data are separately provided. Has become. That is, data writing is performed from the data writing circuit through the write-only data line pair IL, ▲ ▼ and MIS transistors Q12 and Q13, while data reading is performed at the read data-only sub data line pair OLs, ▲ ▼. And read data only main data line pair OL
It is configured through m, ▲ ▼.

The write-only data line pair IL, ▲ ▼ is connected to the selected bit line pair via the MIS transistors Q12 and Q13 which are turned on in response to the write instruction signal W. That is, it is turned on in response to the column decoder output Y.
Between Q10 and Q11 and the write-only data line pair IL, ▲ ▼, the transistor Q12, which is turned on only during the write operation,
Q13 is provided for each.

As a data read path, a current mirror type amplifier is provided for detecting and amplifying the signal potential on the bit line pair BL, ▲ ▼. This amplifier is composed of transistors Q14 to QQ19, the bit line pair BL, ▲ ▼ is connected to its input gate, and the output node is a read-only sub data line pair OLs, ▲.
▼ is configured.

More specifically, the current mirror type amplifier has, for example, a P-channel M whose power supply potential Vcc is connected to one conduction terminal and the other conduction terminal to the sub data line OLs.
An IS transistor Q14, a P-channel MIS transistor Q15 having one conduction terminal connected to the power supply potential Vcc, the other conduction terminal connected to its gate and to the gate of the transistor Q14, and to the sub data line ▲ ▼, An N-channel MIS transistor Q16 having its one conduction terminal connected to the sub data line ▲ ▼ and its gate connected to the bit line BL, and one conduction terminal connected to the sub data line OLs, having its gate connected to the bit line ▲. The N-channel MIS transistor Q17 connected to ▼ and the ON state in response to the bit line pair selection signal Y from the column decoder (not shown) are turned on, and the other conduction terminals of the transistors Q16 and Q17 are both connected via the node N3. N channel MIS transistor Q for connecting to ground potential and activating this amplifier
It consists of 18, Q19.

Since the input impedance of the gates of the transistors Q16, Q17 is extremely large, the signal potential difference on the bit line pair BL, ▲ ▼ is amplified at high speed when activated without any adverse effect on the signal potential difference on the bit line pair BL, ▲ ▼. Output node,
That is, it is transmitted to the sub data line pair OLs, ▲ ▼. The reason why the current mirror type circuit is used here is due to low power loss, high speed operation thereof, and electric isolation between the bit line and the sub data line.

Moreover, as seen from FIG. 1, the sub data line pair OLs, ▲
A predetermined number of bit line pairs 7 are connected to ▼ to form one block 8. In the memory cell array structure, a plurality of blocks 8 are provided, and the output from each block 8 is common read-only main data OLm, ▲ ▼.
It is configured to be transmitted to. With this configuration, the sub data line pairs OLs, ▲
The load capacity of ▼ can be reduced, and the reliability and high speed of the amplification operation can be secured.

FIG. 2 is a signal waveform diagram showing the operation of the semiconductor memory device according to one embodiment of the present invention, and the same reference numerals as those shown in FIG. 1 show the signal potential changes in the corresponding portions.
The operation of the semiconductor memory device according to the embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

First, the read operation will be described. First, the write instruction signal W
Is at a low level, and the write-only data line pair is separated from the bit line pair. Before time T1, the equalizing signal EQ is at the high level, so that the MIS transistors Q7 to Q
All 9 are in the ON state, and the bit line pair BL, ▲ ▼ are precharged to a predetermined precharge potential V _BL . On the other hand, at this time, the read-only main data line pair OLm, ▲ ▼ and the read-only sub data line pair OLs, ▲
Each ▼ is also precharged to the power supply potential Vcc, for example.

At time T1, when the equalize signal EQ is lowered from the high level to the low level, all the transistors Q7 to Q9 of the equalize precharge circuit section 6 are turned off, whereby both bit line pairs BL, ▲ ▼ are brought into a floating state. .

At time T2, one word line WL is selected in response to an externally applied address signal, and the potential of the word line WL shifts from low level to high level.
The transistor Q0 of is turned on. Memory cell 1
When the information "1" is stored in the bit line, the potential slightly rises on the bit line BL as shown by the solid line in FIG. At this time, when the bit line pair selection signal Y from the column decoder (not shown) is shifted from the low level to the high level at time T1 in response to the external address signal, the transistors Q18 and Q19 are turned on and the transistors Q18 and Q19 are turned on. The current mirror type amplifier consisting of Q14 to Q19 is activated. Therefore, at time T2, the word line WL potential changes from low level to high level, the signal potential on the bit line BL slightly rises, while the potential of the bit line ▲ ▼ holds the precharge level. The current mirror type amplifier immediately amplifies the potential difference and discharges the sub-data line () potential from the precharge potential to the ground potential. The signal potential appearing on the sub data line pair OLs, ▲ ▼ is transmitted to the main data line pair OLm, ▲ ▼. This allows
Data can be read before activating the sense amplifiers 2 and 3, and high-speed access can be realized.
At this time, the bit line pair BL, ▲ ▼ is connected to the read-only sub-data line pair OLs, ▲ ▼ via the high impedance of the transistors Q16, Q17, so that the read-only sub-data line pair OLs, ▲ ▼ has The load capacitance and its signal potential do not adversely affect the signal potential on the bit line pair BL, ▲ ▼. Also, sub data line pair OLs, ▲
▼ is only provided in common for a predetermined number of bit line pair blocks 7, its load capacitance is small, and an output signal corresponding to the signal potential on the bit line pair BL, ▲ ▼ is output at high speed. Can be communicated to OLs, ▲ ▼.

After this, at time T3, the sense amplifier activation signal S0, ▲
▼ to the active state, and the transistor Q
5, Q6 is turned on to activate the sense amplifiers 2, 3. As a result, the signal potential difference on the bit line pair BL, ▲ ▼ is further amplified. The amplification operation by the sense amplifiers 2 and 3 is performed for the restore operation of rewriting the read information in the memory cell 1.

At time T5, when the potential of the selected word line WL and the column data output Y shifts from the high level to the low level, the current mirror type amplifier also becomes inactive, and the sub data line pair OLs, ▲ ▼ and the main data line pair OLm. , ▲
▼ returns to a predetermined precharge potential.

Next, at time T6, the sense amplifier activation signal S0, ▲
When ▼ transitions to the inactive state and equalize signal EQ rises to a high level, each bit line pair BL, ▲ ▼ is precharged and equalized, and one memory cycle is completed.

At time T2, when the bit line pair selection signal Y from the column decoder becomes high level, the transfer gate transistors Q10 and Q11 are simultaneously turned on. However, at the time of data reading, the write instruction signal W is at the low level, so that the transistors Q12 and Q13 are
Is in the off state, and the write-only data line pair IL, ▲ ▼ does not affect the data read operation.

In addition, although the case where the selected memory cell 1 has the information “1” has been described in the above embodiment, when the selected memory cell 1 has the information “0”, A signal waveform diagram shown by a broken line in FIG. 2 appears.

Further, in the above embodiment, the data line pair OLs, ▲
Although the precharge potentials of ▼ and OLm, ▲ ▼ are set to the power supply potential level, the precharge level of the main data line pair is not set to the power supply potential level but is set to the intermediate potential, for example, V ′ _BL , as in the conventional case. Even if it is set, the same effect as that of the above embodiment can be obtained.

Further, in the above configuration, one set of sub data line pairs OLs, ▲
On the other hand, since a plurality of sets of block 7 including a bit line pair and a part of the current mirror amplifier are connected in parallel, a plurality of sets of N channel MIS transistors Q16 and Q17 form one set of sub data line pair OLs, ▲ ▼. Will be connected in parallel, and many gate capacitors will be connected, and the load capacitance of the current mirror type amplifier will become large. However, only a predetermined number of bit line pair blocks 7 are connected to each read-only sub-data line pair, and each sub-data line pair is provided with a current mirror type amplifier.
The load capacity of one set of read-only sub-data line pairs can be reduced, and high-speed operation is realized.

Next, the data write operation will be schematically described. At this time,
External write data is transmitted from the data write circuit (not explicitly shown) to the write-only data line pair IL, ▲ ▼ in a complementary form (for example, D _IN , ▲ ▼). During this writing operation, the write instruction signal W is at a high level, so that the transistors Q12 and Q13 are in the ON state. Therefore, at time T4, the bit line pair selected by the column decoder output Y is the data write-only data line pair IL, ▲.
By connecting with ▼, it becomes possible to write data to the selected memory cell. Here, in the waveform diagram of FIG. 2, the column decoder output Y is shown to shift to the high level at time T4 during data writing. The intentional shift of the column decoder output Y to the active state at the time of writing and data reading is performed by the write instruction signal W and the column address strobe signal ▲ ▼.
It can be easily realized based on

Further, in the above-described embodiment, the column decoder output Y is described to shift to the high level at the same time as the shift of the equalize signal EQ to the low level at the time of data reading. The transition to the level is not limited to the operation timing shown in FIG. 2, and the column decoder output may be transited to the high level at the same time as the transition of the word line WL to the high level. In any configuration, the transition of the column decoder output Y, which gives the activation timing of the current mirror type amplifier, to the high level is an operation which is appropriately determined in consideration of the operating characteristics of the semiconductor memory device for practical use. It is a parameter.

Further, in the operation waveform diagram shown in FIG. 2, the column decoder output Y is in the active state at the time T4 at the time of data writing, that is, it shifts to the high level as shown by the alternate long and short dash line in FIG. The timing of transition to the high level is not limited to time T4, and the write operation can be reliably performed even at time T2.

Further, in the above-mentioned embodiment, the current mirror type amplifier has a configuration in which the transistors Q14 and Q15 are connected to the power supply potential Vcc and the transistors Q18 and Q19 are connected to the ground potential. The polarity of the transistor is not limited to the illustrated structure, and should be appropriately selected according to the structure of the applied semiconductor memory device. Further, in the above-mentioned configuration, the Kaleto-mirror type amplifier is also activated during data writing. However, from the viewpoint of power consumption, the current mirror type amplifier can be activated only at the time of reading. This can be easily realized by a configuration in which the write instruction signal W which becomes "H" in the data read mode instruction and the column decode signal Y are ANDed.

FIG. 3 is a diagram showing an overall schematic configuration of a semiconductor memory device having the structure shown in FIG. Referring to FIG. 3, a semiconductor memory device according to the present invention decodes an internal row address signal from a memory cell array 100 having a folded bit line structure and an address buffer 101 receiving an external address, and outputs one row from the memory cell array. X decoder for selecting a memory cell (that is, selecting one word line)
102, and a Y decoder (column decoder) that outputs a bit line pair selection signal Y for selecting a pair of bit lines in response to the internal column address signal from the address buffer 101.
103, a read-only sub-data line pair provided for each bit line block consisting of a predetermined number of bit line pairs, a read-only sub-data line pair commonly provided for each sub-data line pair, and provided for each bit line pair Block 104 consisting of current mirror type amplifier (current mirror amplifier + output line)
A preamplifier 105 for further amplifying the read data from the block 104, a read buffer 106 for outputting the read information from the preamplifier 105 to an external terminal, and an internal write data from the write data D _IN. Input block 107
And a write buffer 108 for transmitting to the data input line pair IL, included in. Write instruction signal W
Is transmitted to each required circuit portion via the terminal 109. This configuration is merely an example, and other configurations can of course be applied.

As described above, according to the present invention, a read-only data line pair and a write-only data line pair are separately provided, and the read-only data line pair corresponds to a predetermined number of bit line pairs. Read-only sub-data line pairs and a pair of read-only main data line pairs commonly provided for each sub-data line pair, and each read-only sub-data line pair is an output node of a read amplifier. Since the bit line pair is connected to the input gate of this read amplifier, the minute signal potential difference on the bit line pair can be amplified and read even immediately after the rise of the word line. Therefore, the access time at the time of data reading can be significantly shortened, and high-speed reading can be realized.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a configuration of a main part in a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a signal waveform diagram showing an operation of the semiconductor memory device according to the embodiment of the present invention. FIG. 3 is a diagram illustrating the overall schematic configuration of a semiconductor memory device according to an embodiment of the present invention. FIG. 4 is a diagram schematically showing a configuration of a pair of bit lines and a circuit portion related thereto in a conventional semiconductor memory device. FIG. 5 is a signal waveform diagram showing an operation in the conventional semiconductor memory device. In the figure, 1 is a memory cell, 2 and 3 are flip-flop type sense amplifiers, 4 and 5 are sense amplifier activation signal generating circuit sections, 6 is an equalize / precharge circuit section, 7 is a bit line pair block, and 8 is a predetermined block. Block consisting of several read-only sub-data line pairs of several bit line pairs and current mirror type amplifier, IL, ▲ ▼ are write-only data line pairs, OLs, ▲
▼ is a read-only sub data line, OLm, ▲ ▼ is a read-only main data line, BL, ▲ ▼ is a bit line, Q14, Q15, Q16, Q
Reference numerals 17, Q18 and Q19 are MIS transistors forming a current mirror type amplifier. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiro Konishi 4-1-1 Mizuhara, Itami-shi, Hyogo Prefecture LS Electric Co., Ltd. LSE Research Laboratory (72) Inventor Takahiro Komatsu 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Co., Ltd. LSI Research Laboratory (72) Inventor Yama-saki Hiroyuki 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. LSI Research Laboratory (56) Reference JP 63 -311690 (JP, A) JP 60-74197 (JP, A) JP 60-43294 (JP, A) JP 57-117178 (JP, A)

Claims (10)

[Claims] 1. A plurality of memory cells arranged in a matrix of rows and columns, corresponding to the rows of the plurality of memory cells, each of which has a corresponding row of memory cells. Connected to each of the columns of the plurality of memory cells, each connected to a memory cell arranged in a corresponding column of the plurality of memory cells, and each A plurality of bit line pairs for transmitting mutually complementary data; when writing data to a selected memory cell of the plurality of memory cells, the selected memory cell of the plurality of bit line pairs is connected A pair of write data transmission lines electrically connected to the selected bit line pair for transmitting write data to the selected memory cell, each of which is a predetermined number of the plurality of bit line pairs. Bit line A plurality of read data line pairs provided for the pair, each provided corresponding to each of the bit line pairs, and the potentials appearing on both bit lines of the corresponding bit line pair are respectively inputted and inputted. A pair of variable conductance elements whose conductances change according to potentials, and a pair of activation elements connected in series with each of the pair of variable conductance elements and conducting in response to a bit line pair selection signal. A current path between a corresponding sub-read data line pair and a first potential via the pair of variable conductance elements and the pair of activation elements in response to the bit line pair selection signal. A plurality of drive circuit means to be formed, a plurality of drive circuit means commonly connected to the sub-read data line pair corresponding to the predetermined number of bit line pairs, and supplying a current to both sub-read data lines of the corresponding sub-read data line pair. Negative current Circuit means and a potential of the sub-read data line pair which is commonly connected to the plurality of sub-read data line pairs and is driven by the drive circuit means which forms a current path in response to the bit line pair selection signal. 1 provided separately from the write data line pair for transmitting
A semiconductor memory device comprising a pair of main read data line pairs. 2. The potential appearing on both bit lines of the bit line pair corresponding to the selected memory cell based on the potential read from the selected memory cell is provided to the bit line pair separately from the drive circuit means. 2. The semiconductor memory device according to claim 1, wherein the sense means is differentially amplified and the amplified potential is latched. 3. When reading data, the activation timing at which the pair of activation elements of the drive circuit means are turned on is set earlier than the activation timing of the sense means. The semiconductor memory device according to claim 2. 4. The bit line pair selection signal input to the drive circuit means in response to a column selection signal from a column decoding means for selecting a column of the plurality of memory cells and a read mode instruction signal. The semiconductor memory device according to any one of claims 1 to 3, which is generated. 5. A plurality of memory cells arranged in a matrix of rows and columns, corresponding to each row of the plurality of memory cells,
A plurality of word lines to which the memory cells of the corresponding rows are connected, respectively, memory cells arranged corresponding to each of the columns of the plurality of memory cells, and connected to columns corresponding to the respective memory cells are connected. A plurality of bit line pair groups in which a plurality of bit line pairs are divided into a plurality of groups, and a bit line pair selecting means for selecting any one of the plurality of bit line pairs of the plurality of bit line pair groups When electrically writing data to a selected memory cell of the plurality of memory cells, the bit line pair is electrically connected to the bit line pair selected by the bit line pair selection means, A write data transmission line pair for transmitting write data to a selected bit line pair, corresponding to each group of the plurality of bit line pair groups and commonly arranged to the bit line pair of the corresponding group. A plurality of sub-read data line pairs and a bit line pair selected by the bit line pair selecting means when reading read data from a selected memory cell provided corresponding to each of the bit line pair groups. A plurality of current mirror type amplifier circuit means for amplifying the potential difference appearing on both bit lines, each of the current mirror type amplifier circuit means: (a) a sub-read data line pair corresponding to a corresponding bit line pair group; Means provided so as to correspond to each other to operate so as to equalize the current values of the currents flowing through both sub-read data lines of the corresponding sub-read data line pair; and (b) each bit of the corresponding bit line pair group. A pair of variable resistors provided corresponding to the pair of lines, each of which receives the potential appearing on both bit lines of the corresponding pair of bit lines, and whose conductance changes according to the input potential. (C) a pair of variable conductance elements and a pair of variable conductance elements that form a current path between the corresponding sub-read data line pair and a first potential during data reading. A pair of activation elements connected in series with each of the variable conductance elements, and further provided separately from the write data transmission line pair and commonly connected to the plurality of sub read data line pairs, A semiconductor memory device comprising: a main read data line pair for receiving and transmitting data of a sub read data line pair to which data of the selected memory cell is transmitted. 6. One of the pair of variable conductance elements in each of the current mirror type amplification circuit means is a field effect transistor having a gate electrode connected to one bit line of a corresponding bit line pair. 6. The method according to claim 5, further comprising: a field effect transistor having a gate electrode connected to the other bit line of the corresponding bit line pair, the other variable conductance element of the pair of variable conductance elements. Semiconductor memory device. 7. The potential appearing on both bit lines of the bit line pair corresponding to the selected memory cell based on the potential read from the selected memory cell is different from that of the current mirror type amplifier circuit means. 7. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is amplified by a dynamic amplification means and rewritten in the selected memory cell. 8. A data reading method according to claim 7, wherein the activation timing of said current mirror type amplifier circuit means is set earlier than the activation timing of said differential amplifier means. The semiconductor memory device described. 9. A pair of activation elements in said current mirror type amplifier circuit means are activated based on a signal generated in response to a selection signal from said bit line pair selection means and a read mode instruction signal. The semiconductor memory device according to claim 5 or claim 6. 10. A pair of variable conductance elements in the current mirror type amplifier circuit means are provided with corresponding sub-reads based on a signal obtained by logically processing a selection signal from the bit line pair selection means and a read mode instruction signal. 7. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is electrically connected between the data line pair and the first potential.