JPS62287498A - Semiconductor memory unit - Google Patents

Abstract

PURPOSE:To obtain a complete 2-port DRAM by accessing a cell array by a first word decoder and a column decoder, latching and outputting the read data to a latch circuit, and accessing the cell array by a second word decoder and column decoder and terminating one access cycle. CONSTITUTION:When addresses A0-Am are changed at a time t1, and a chip enable bar signal; the inverse of CE drops at a time t2, a control circuit 26 leads a chip enable signal CEI at a time t3. When CEI is led, an address buffer 22 takes in addresses A0-Am, and outputs address bit of MOS level and its inversional bits A, the inverse of A. On receiving them, a word decoder 12 selects designated word lines and connects memory cells strung out to it with bit lines all at once. Then, potential difference DELTAV is generated between bit lines BL, the inverse of BL. A transfer gate 34 is placed between a latch circuit 20 and bit lines BL, the inverse of BL and when clock phi1 is raised and the bit lines are connected to the latch circuit, at a time t5 it is amplified by a sense amplifier.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] A dual port memory using a one-transistor, one-capacitor type dynamic memory cell.

[Industrial application field]

The present invention relates to a semiconductor memory device, particularly a dual-port DRA capable of simultaneous and independent random access from two locations.
Regarding M.

[Conventional technology]

A memory has been developed in which the cell array is accessed independently from two locations. This is suitable for writing common information such as a database in the cell array and allowing each CPU to access this independently.

This method of using memory is possible even with a single-port memory if it is used in a time-sharing manner, but with a dual-port memory, it is literally possible to access the memory independently from two locations at the same time. This memory access includes not only reading but also writing. This writing is equivalent to updating data in the database mentioned above, and once this is done, each C
The PU will access the database updated by itself or by another CPU.

[Problem that the invention seeks to solve]

Dual-port RAM is realized in S (static) RAM, in which word lines and bit lines are arranged twice in an array of memory cells consisting of flip-flops, and each set is equipped with a word decoder, a column decoder, etc. It has been established. However, this makes the word lines and bit lines considerably more complex, making it more difficult to manufacture and reducing the degree of integration.

D using one transistor, one capacitor type memory cell
Some (dynamic) RAMs are equipped with a shift register and each stage of the register is connected to a bit line so that memory cell data for one word line can be read/written simultaneously.

This DRAM is also designed to operate as a normal DRAM, so if you add the input/output terminals of the shift register, it has two ports. However, the 110 port on the shift register side only operates serially.

The present invention provides a complete two-port DRAM that has a simple structure and can increase the degree of integration.

[Means for solving problems]

The present invention includes a cell array (10) having a plurality of dynamic memory cells (MC), word lines (WL) and bit lines (BL, BL) arranged in a single layer among these,
a first word decoder (12) and a column decoder (16) for the word line and bit line; a second word decoder (16) for the word line and bit line;
14) and a column decoder (18), and first and second address buffers (22, 2) that supply address bits and their inverted bits to these decoders.
4), the first column decoder (16) and the bit line are connected via the first transfer gate (34) and the latch circuit (20), and the second column decoder (
18) and the bit line is the second transfer gate (
36), the cell array is accessed by a first word decoder and a column decoder, and the read data is latched and outputted to the latch circuit, and then the cell array is accessed by a second word decoder and a column decoder. , thus completing one access cycle.

(Function) According to this configuration, a highly integrated two-point terminal that can be accessed simultaneously and independently of each other by using a DRAM cell and providing only one bit line and one word line. ToR
AM can be provided.

〔Example〕

To explain with reference to FIG. 1, 10 is a cell array, in which one transistor, one capacitor type memory cell is connected to a large number of word lines WL.
and the bit line BL. There are two types of DRAMs: open bit line type and folded focus line type. In this example, the latter type is used, and BL and BL indicate a pair of bit lines extending in the same direction from the sense amplifier (located at column decoders 16 and 18). For this cell array 10, a word decoder 12, 14 and a column decoder 16 are provided.
゜18 is provided. The word line and bit line are single. A latch circuit 20 is provided on the column decoder 16 side.

The memory chip is provided with two sets of input terminals for external addresses Ao to Am, allowing mutually independent access from two locations. Therefore, although these two sets of addresses AoxAm are indicated by the same symbol, their contents are usually different. 22.
24 is an address buffer that takes in address Ao-Am and produces the same bit and inverted bit (denoted by A, A); 30 is an output circuit; 32 is an input/output circuit; 26.2
8 is a control circuit for these.

To explain the operation with reference to FIG. 2, addresses Ao-Am are switched at time t1 (a new address is entered), and when the chip enable bar signal CE drops at time t2, the control circuit 26 activates the chip enable signal at time t3. CEI
launch. Address buffer 22 takes in addresses Ao to Am when CEI rises, and outputs MOS level address bits and their inverted bits A and A. In response to this, the word decoder 12 selects the designated word line, WLO in this example, and connects each memory cell connected to WLO to each bit line all at once.

As a result, a potential difference ΔV as shown, for example, is generated between the bit lines BL and BL. Latch circuit 20 and bit lines BL, B
A transfer gate 34 is inserted between L and L, and at time t5, the clock φ! When the bit line is connected to the latch circuit by increasing the bit line, it is amplified by the sense amplifier, and in this example, the BL
rises to Vcc, and 1T falls to Vss. The latch circuit 20 takes in this amplified bit line potential and holds it.

Thereafter, the clock φr falls, and the connection between the bit line and the latch circuit is cut off. After that, the word decoder 12 outputs the word line W.
Return LO to unselected.

After that (time ts), the control circuit 28 raises the chip select signal CEn, and as a result, the address buffer 24 takes in the external address AamAm and outputs the MOS level A, A.
Output. On the other hand, in the cell array, although not shown, a bit line pair charging/discharging circuit operates, shorting BL and BL to set each to Vcc/2. The control circuit 26 also lowers the signal CEI.

The word decoder 14 receives the addresses A and A from the address buffer 24 at time t7, and the word line WLI in this example.
is selected, and memory cells connected to the word line are connected to each bit line. Therefore, a potential difference as shown in the figure is applied to the bit lines BL, BL, and at time point to, the clock φ is input, and the transfer gate 36 transfers the bit line to the column decoder 18.
When connected to , the potential difference is amplified by the sense amplifier, and in this example, BL becomes Vcc and BL becomes SS.

Since the address buffers 22 and 24 also provide addresses A and A to the column decoders 16 and 18, the latch circuit 20
One of the bit line potentials taken in from time t5 onward selected by the address (column address) is outputted through the column decoder 16, data bus DB, and output circuit 20, and the bit line potential from time t8 onwards is output. It is output through the column decoder 18, data bus DB, and I10 circuit 32.

The column decoder 16 side is for reading only in this memory, whereas the column decoder 1B side is for reading and writing. Writing is performed after time te after reading. At the time of writing, the write enable signal WE switches the I10 circuit 32 to an input circuit, prohibits the output of read data from the I10 terminal, and instead determines H and L of the data bus DB according to the write data from the terminal. Through the decoder 18, the potential of the bit line selected by the address AoxAm is made to follow the above H and L, and the data is written into the selected memory cell. Clock φ when writing is completed
, the word line WLI is lowered, and (1) the signal GE is raised, completing one access cycle. The next cycle starts with bit line charging/discharging and CE falling.

DR of the type that charges and discharges the bit line BL and Hyakko to Vcc/2
A? In No. 1, a dummy cell is not required, and when the real cell is on the BL side, BL provides the reference potential, and when the real cell is on the BL side, BL provides the reference potential. Since the real cell is charged and discharged to Vcc or Vss according to data 1°O, the bit line potential is raised above Vcc/2 when the voltage is Vcc, and lowered when the voltage is Vss. ΔV is the potential difference caused by this.

The output circuit 30 latches the read data and holds the data at Dout until the rising edge of 31.

〔Effect of the invention〕

As explained above, according to the present invention, a highly integrated two-point RAM that can be accessed simultaneously and independently of each other can be created by using DRAM cells and by simply providing a single bit line and word line. can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation. In FIG. 1, 10 is a cell array, 12.16 is a first word decoder and a column decoder, 14.18 is a second word decoder and column decoder, 20 is a latch circuit, and A o '' A m is an address bit.

Claims (1)

[Claims] A plurality of dynamic memory cells (MC), word lines (WL) and bit lines (BL
, BL), a first word decoder (12) and a column decoder (16) for the word line and bit line, and a second word decoder (14) for the word line and bit line.
and a column decoder (18), and first and second address buffers (22, 24) that supply address bits and their inverted bits to these decoders, and the first column decoder (16) and the bit line. is connected through the first transfer gate (34) and the latch circuit (20), and the second column decoder (18) and the bit line are connected through the second transfer gate (36). Then, the cell array is accessed by the first word decoder and column decoder and the read data is latched into the latch circuit and outputted, and then the cell array is accessed by the second word decoder and column decoder, thus completing one access cycle. A dual-port semiconductor storage device characterized in that the dual-port semiconductor storage device