JPH01138694A - Memory device - Google Patents

Abstract

PURPOSE:To shorten a copy time by using two FF circuits, a selector circuit, and row and column address strobe clocks to internally copy data as a word line as the unit. CONSTITUTION:First and second FFs 1 and 4 are provided, and row and column address strobe clocks are inputted to the first FF 1, and AND between the output of a logic circuit 2 of write-and output-enable clocks and the output of the FF 1 is inputted to the second FF 4 and the second FF 4 outputs a copy mode signal to a terminal 6. The selector circuit is provided which compares the signal of the terminal 6 and row and column address deciding signals with the signal from an address decoder. When levels of clocks other than said both clocks are combined as specified at the time of trailing edges of said both clocks, data of plural memory cells designated by addresses latched with said both clocks is copied on designated memory cells with a word line as the unit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device, and more particularly to a memory device that internally copies data.

[Conventional technology]

Conventionally, a memory device having a memory cell array section has only the functions of storing data applied from the outside and reading the stored data to the outside. This memory storage device uses rows to store and read data.
Address strobe clock and column address
When copying data stored in such a memory device, the data to be copied is first output to an external circuit connected to the memory device, and then Data is copied using data read and write functions.

[Problem that the invention seeks to solve]

In the conventional memory devices described above, when copying data, the data passes through an external circuit of the memory device, so the amount of data that can be stored or read at one time is limited to a memory device with a large storage capacity. Alternatively, in the case where all data is rewritten to initialize the stored data, there is a disadvantage that the number of operations required to copy the data increases, and therefore the entire copying time increases.

An object of the present invention is to provide a memory device that reduces the conventional copying time.

[Means for solving problems]

The memory device of the present invention is a multi-address type memory device that inputs a row address strobe clock and a column address strobe clock, and a first flip-flop that inputs the two clocks. a second flip-flop circuit, which receives as input the logic circuit output of the write enable clock and the output enable clock, and the logical product of the first flip-flop circuit output, and outputs a data copy cycle recognition signal as a copy mode; It has a flip-flop circuit and a selector circuit that compares the data copy cycle recognition signal and the row address 2 column address determination signal with a signal from an address decoder, When the levels reach a specific combination, the addresses latched by the row address strobe clock and the column address strobe clock are set as the first row address and second row address, respectively. The plurality of memory cell data specified by the row address are copied to the plurality of memory cells specified by the second row address in units of word lines.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a logic circuit diagram for determining the level of a specific clock for explaining an embodiment of the present invention.

As shown in FIG. 1, this level determination logic circuit is a logic circuit for outputting a data copy cycle recognition signal representing a copy mode as a specific clock, and is a logic circuit for outputting a data copy cycle recognition signal representing a copy mode as a specific clock, and is a logic circuit for outputting a data copy cycle recognition signal representing a copy mode as a specific clock. a first flip-flop 1 that latches the level of a column address strobe clock (hereinafter referred to as CAS clock) at the falling edge of a column address strobe clock (hereinafter referred to as CAS clock);
A logical NOR gate 2 outputs a logical sum of an output enable clock (hereinafter referred to as OE clock) and a write enable clock (hereinafter referred to as WE clock); and the output of the first flip-flop 1; a logical AND gate 3 that performs logical product with the output of the NOR gate 2;
a second flip-flop 4 that latches the output of AND3 on the falling edge of the CAS clock;
It has a logical OR gate 5 that outputs the logical sum of the clock and the CAS clock, and outputs a data copy cycle recognition signal to the copy mode output terminal 6.

Next, the operation of this level determination logic circuit will be explained.

This circuit generates a data copy cycle recognition signal, which is a copy mode signal, when the CAS clock is high at the falling edge of the RAS clock, and both the OE clock and the WE clock are low at the falling edge of the CAS clock. becomes high level. Also, R
When the AS and CAS clocks are high, the copy mode signal, the data copy cycle recognition signal, is low.

Next, FIG. 2 is an address processing circuit diagram of a memory cell array section using the output of the level determination logic circuit shown in FIG. 1.

As shown in FIG. 2, this address processing circuit is a circuit that processes an address latched by the CAS clock as a column address or a second row address for the memory cell array section.

In FIG. 2, in the memory cell array, a memory element consisting of a transfer gate 14 and a capacitor 15 is connected to each point where a word line 12 and a bit line 13 intersect. Further, a word line selection gate 16 is connected to each word line 12, and one bit line selection gate is connected to each bit line 13, although only one is shown here. Furthermore, the address decoder 9 is an address decoder that serves both as a row address and a column address, and a NOR gate 10
The selector circuit 11 is a selector for switching and inputting the address decoded output of the address decoder 9 to the selection gate 16 of the word line 12 or one selection gate of the bit line 13.

The sense amplifier 17 is connected to a plurality of bit lines 13 and is a sense amplifier that amplifies the charge information (voltage) on the bit line 13, and is supplied with a RAS clock by a delay circuit 18. On the other hand, the row address, column The logic of the Row/Column signal input to the address judgment signal terminal 7 and the signal input to the copy mode output terminal 6 is determined by the NOR gate 8; however, this Row/Column signal is input to the address decoder 9. is latched at the falling edge of the RAS clock (Ro
w ) or latched by the falling edge of the CAS clock (Column).

In short, in this embodiment, a logic NOR gate 8 is provided which controls the Row/Column signal by the copy mode signal shown in FIG.
The address decoder signal from the address decoder 9 is selected between the N0RIO and the address decoder signal from the address decoder 9. Note that the circuit operation of the above-mentioned memory device will be explained with reference to the following FIG. 3.

FIG. 3 is a diagram of main signal waveforms during data copying in the circuit shown in FIGS. 1 and 2.

As shown in FIG. 3, the first row address is latched at the falling edge of the RAS clock (time t1), and the word line (WL) corresponding to this first row address 20 is latched.
1> becomes high level at an appropriate time. Thereafter, at the time when the charge information of the transfer gate 14 constituting the memory cell reaches the pin 1 to line 13, the sense enable signal (SEN) is set to a low level, and the charge information (voltage) of the bit line is amplified. On the other hand, time 1. If the CAS clock at is high level and both the OE clock and WE clock at the falling edge of the CAS clock (time t2) are low level, the second row address 21 at time t2 is latched.

Therefore, inside the memory device, the copy mode signal becomes high level, and it can be recognized that it is a specific cycle for copying data. However, once the sense amplifier 17 shown in FIG. 2 starts the amplification operation, the amplified data will not be lost until the R and AS clocks reach a high level. When the word line WL2 corresponding to 21 becomes high level, the stored charge information is lost and the charge information amplified by the sense amplifier 17, that is, the first row address 2
The charge information stored in the 0 memory cell is replaced. Finally, the rising edge of the RAS clock (time t
3) After that, at an appropriate time, the word line WL corresponding to the first row address 20 and the word line WL2 corresponding to the second row address 21 both become low level, and the sense enable signal (SEN) becomes low level. The high level ends this newly established copy cycle.

As described above, in this embodiment, a specific clock timing in which both the OE clock and the WE clock are at a low level at the falling edge of the CAS clock, which is not used in conventional memory devices, is used to define the copy cycle. This new cycle does not impair the operation of the memory device.

〔Effect of the invention〕

As explained above, the memory device of the present invention uses two flip-flop circuits, a selector circuit, a row address strobe clock, and a column address strobe clock, and uses another clock at the falling edge of both clocks. By latching the second row address at the falling edge of the column address strobe clock when the levels of Since a large amount of data can be copied at one time, the copying time can be reduced.

[Brief explanation of the drawing]

1 is a level determination logic circuit diagram of a specific clock for explaining an embodiment of the present invention, FIG. 2 is an address processing circuit diagram of a memory cell array section using the output of the level determination logic circuit shown in FIG. 1, FIG. 3 is a diagram of main signal waveforms during data copying in the circuit shown in FIGS. 1 and 2. 1...first flip-flop, 2...N0R13
...AND, 4...second flip-flop, 5.
...0R16...Copy mode output terminal, 7...Row address, column address judgment signal terminal, 8...N0
R19...Address decoder, 10...N0R11
1... Selector circuit, 12... Word line, 13...
・Bit line, 14...Transfer gate, 15...
・Capacitor, 16... Word line selection gate, 17.
...Sense amplifier, 18...Delay circuit, one...Bit line selection gate, 20...First Row address,
21...Second Row address.

Claims (1)

[Claims] In a multi-address memory device that inputs a row address strobe clock and a column address strobe clock, a first flip-flop circuit that inputs the two clocks, a write enable clock, and an output enable clock. - a second flip-flop circuit which inputs the logical product of the logic circuit output with the clock and the output of the first flip-flop circuit and outputs a data copy cycle recognition signal as a copy mode, and the data copy cycle recognition signal; a selector circuit that compares the row address and column address determination signals with the signals from the address decoder, and when the levels of other clocks at the falling edges of both clocks reach a specific combination, the row・Address strobe clock and column address strobe・
The addresses latched by the clock are used as a first row address and a second row address, respectively, and a plurality of memory cells specified by the first row address are used.
A memory device characterized in that data is copied word line by word line to a plurality of memory cells specified by the second row address.