JPH0453040B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor memory device, particularly an EPROM,
This invention relates to a bit line data sense system suitable for use in non-volatile memory such as ^E2 PROM.

(Technical Background of the Invention) FIG. 5 shows a portion of a dynamic random access memory (RAM) employing a conventional open bit line format, in which one column out of each column in a memory cell array is representatively shown. BL and MC are a pair of bit lines connected to the synchronous sense amplifier SA located in the center, with each end extending in both directions, and MC is a pair of bit lines connected to one of the bit lines BL. One memory cell MD is representatively shown among the memory cells and one dummy cell, and MD is also representatively shown among the plurality of memory cells and one dummy cell connected to the other bit line. WL is a word line for selecting the memory cell MC, WD is a dummy word line for selecting the dummy cell MD, and C ₁ and C ₂ are load capacitances of each bit line BL.

FIG. 6 shows sequence operation waveforms in a cell data read operation in the memory. That is, first, during the precharge period, each word line and each dummy word line remain in an inactive state, and the bit line is
BL, is precharged and equalized. Next, during the free running period, if the illustrated memory cell MC is selected, its word line WL and sense amplifier
Dummy word line located on the opposite side via SA
WD is activated and memory cell MC and dummy cell MD are selected. As a result, a slight potential difference is generated between the bit line BL and the bit line BL depending on the charge storage state (data content) of the memory cell MC. Next, the sense amplifier SA operates during the sense latch period, the potential difference between the bit lines BL and BL is sense latched, and one of the bit lines BL is set to _VDD.
The power supply potential is amplified until the local potential reaches ground potential. As a result, data is read and rewritten to the selected cell.

In the above memory, the cell structure is passive, and assuming that a CMOS (complementary insulated gate) circuit is used as the sense amplifier SA, and there is no power consumption in this part, the pit line potential is set by the sense latch operation. There is no through current path after this is determined.

On the other hand, as memory capacity increases, parasitic capacitance of bit lines increases, and cell conductance decreases as cells become smaller. The adoption of the open bit line format is also promising for nonvolatile generation memories such as read-only memory (read-only memory) and E ² PROM (electrically erasable/rewritable read-only memory). This is because, according to this format, parasitic capacitance effects are canceled out between symmetrical bit lines, so it is possible to sense a minute potential difference between the bit lines determined by a relatively small conductance difference between the selected cell and the dummy cell.

Based on the above explanation, FIG. 7 shows a part of a case where an internally synchronized open bit line format is adopted for an E ² PROM having a two-transistor structure memory cell. The structures of the memory cell 1 and the dummy cell 2 are different, and the other parts are the same, so the same reference numerals as in FIG. 5 are given and the explanation thereof is omitted. The internal synchronization type is a system in which a change in address is detected at the time of address switching, a pulse is generated internally, and this is used as a trigger to perform precharge/equalization, free running, and data latch read cycles.

FIG. 8 shows sequence operation waveforms corresponding to the read operation of memory cell 1 data in the E ² PROM. This operation is almost the same as the operation described above with reference to FIG. It is located between the high impedance state) and the programmed state (low impedance state).

[Problems with background technology]

By the way, the above open bit line format
There are three problems with E ² PROM as described below. (1) When the bit line potential is stable after the sense latch operation, the selected cell and dummy cell have finite conductance, so as shown in FIG. A DC path is created and the current
As the current i ₁ flows, a DC path from the sense amplifier SA to the local bit line to the dummy cell 2 is created, and a current i ₂ flows. These currents i ₁ and i ₂ flow for the bit line or equivalent number of bit lines in the memory cell array, resulting in enormous current consumption. (2)
Alternatively, since the currents i ₁ and i ₂ flow, the highest bit line potential V _D1 in the latched state does not reach the V _DD power supply potential, that is, the amplification function of the sense amplifier SA is weak. In this way, the high level potential V _D1 of the bit line
When is low, the gate input level of the next stage buffer of the sense amplifier SA becomes low, so the read speed becomes slow and the latch speed (transition time) also becomes slow. This problem can be solved to some extent by increasing the conductance gm of the pull-up transistor of the sense amplifier SA, but this inevitably causes an increase in current consumption. (3) In addition, the memory cell group or dummy cell connected to one bit line which is at the high level potential V _D1 which is a relatively high potential has the above V _D1 long at the drain of its transfer gate transistor Q ₂ . This is not preferable because the application over a long period of time causes charge discharge from the floating gate transistor _Q1 .

The above-mentioned problems also occur when an open pit line format is adopted for EPROM.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and
The present invention provides a semiconductor memory device that can improve data read speed, suppress current consumption after sensing operation, and improve reliability of memory contents.

[Summary of the invention]

That is, the present invention provides a semiconductor memory device in which a sense amplifier senses and amplifies the potential difference between bit lines of a pair of bit lines to which a memory cell and a dummy cell are connected in each column of a memory cell array to read data. At least one of them is provided between both input ends of the bit line pair and each bit line of the corresponding bit line pair, and is controlled to be in an on state when the bit line pair is precharged, and the potential difference between the bit lines of the bit line pair is a transfer gate that is controlled to be in an off state after being sense-latched by the sense amplifier; a switch element that performs precharging provided between the bit line and the electrode; and a ground terminal between each bit line and the ground terminal of the bit line pair. The present invention is characterized in that it includes a transistor provided between each of the bit lines, which is controlled to be turned on after the transfer gate is turned off, thereby pulling down each bit line to the ground potential.

Therefore, since the sense amplifier and the bit line are electrically isolated after the sense latch, the transition time of the sense data of the sense amplifier is shortened, and moreover, the sense data is connected between the V _DD power supply potential and the ground potential. Full swing and faster data read speed. In addition, current consumption after sense latch is suppressed, and high potential is not applied to the drain of the cell.
Erroneous writing to cells is not performed, and the reliability of cell data is increased.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a part of an ^E.sup.2 PROM employing an open bit line format prior to the improvement leading to the present invention, and representatively shows one column out of each column in the memory cell array. S.A.
For example, 1 is a synchronous sense amplifier using a CMOS flip-flop circuit, BL and 1 are a pair of bit lines extending in both left and right directions of the sense amplifier SA, and 1 is a plurality of memory cells connected to one of the bit lines BL. and 1 memorial representatively shown among 1 dummy cells; 2 is a dummy cell representatively shown among a plurality of memory cells and 1 dummy cell similarly connected to the region and the bit line; WL; is the memory cell 1
WD is a dummy word line for selecting the dummy cell 2, C ₁ , C ₂
is the load capacity of each bit line BL. Each cell can be electrically erased and written, and is composed of a transfer gate MOS transistor _Q2 and a floating gate transistor _Q1 , each having a drain connected to a bit line.

Furthermore, in the present invention, the sense amplifier
It is controlled to be in the on state for a predetermined period (precharge, free running, and sense latch operation period) between SA and each bit line BL, and is controlled to be in the off state during the period from the sense latch operation until the precharge of the next cycle starts. Transfer gates 3 ₁ and 3 ₂ each consisting of at least one (one in this example) MOS transistor are provided.

Next, a cell data read operation in the memory will be explained with reference to FIGS. 2a and 2b. That is, first, during a precharge period, each word line and each dummy word line remain in an inactive state, and a pit line is set by a precharge/equalization circuit (not shown).
BL, is precharged and equalized (equalized potential). Next, if the illustrated memory cell 1 is selected during the free running period, the word line WL and the dummy word line WD located on the opposite side via the sense amplifier SA are activated. Memory cell 1 and dummy cell 2 are selected. As a result, a slight potential difference is generated between the bit lines BL and BL depending on the charge storage state (data content) of the memory cell 1.
Next, the sense amplifier SA operates during the sense latch period, and the potential difference between the bit lines BL and BL is sense latched. After this latch operation, the bit line
Transfer gates 3 ₁ and 3 ₂ connected in series to BL are turned off. This isolates the sense amplifier SA from the pit wire load, so
The respective potentials V _S and _S at both input terminals suddenly transition to the V _DD power supply side or the ground power supply side, as shown in FIG. 2a. Moreover, at this time, there is no current flowing into the cell from the sense amplifier SA through the bit line BL, so each of the potential transitions described above fully swings to the V _DD power supply potential or ground potential, and in this way, the potential of the sense data is fixed. Since there is no direct current path after this, no current consumption occurs.
On the other hand, as mentioned above, the transfer gate 3 ₁ ,
As soon as 3 ₂ turns off, each bit line BL,
Since the potential of BL no longer follows the potential transition of the sense amplifier SA, a phenomenon in which a high potential is applied to the drain of the transfer gate transistor _Q2 of each cell can be avoided. In this case, depending on whether the selected cell 1 is in a high impedance state (“1” state where data is erased) or a low impedance state (“0” state where data is written), The potential of the bit line BL changes as shown in FIG. 2b, and the potential of the bit line on the dummy cell side changes as shown.

That is, according to the E ² PROM of the above example, since the sense amplifier and the bit line are electrically isolated after the sense latch, the transition time of the sense data of the sense amplifier SA is short, and the sense data is
V _DD fully swings between the power supply potential and the ground potential, and the gate input level of the next stage buffer becomes high.
Data read speed becomes faster. Furthermore, no direct current flows between the sense amplifier and the bit line after the sense latch, and current consumption is suppressed. Further, a high potential is not applied to the drain of the cell after sense latch, and erroneous writing to the cell is not performed, resulting in high reliability of cell data.

FIG. 3 shows an embodiment of the invention. In order to further reduce the voltage burden on the cell drain after the sense latch as described above, one pull-down MOS transistor 4 ₁ is connected between each bit line BL and the ground terminal, as shown in FIG. 4 ₂
It is preferable that the transistors 4 ₁ and 4 ₂ are controlled to be in the on state after the transfer gates 3 ₁ and 3 ₂ are in the off state and until the start of the next precharge. In FIG. 3, the same parts as in FIG. 1 are given the same reference numerals, and 4 indicates a precharge/equalization circuit for bit line precharging and bit line potential equalization. By means of the transistors ₄₁ and ₄₂ described above, the bit line BL becomes the ground potential after the bit line BL is separated from the sense amplifier SA after the sense amplifier SA senses the sense latch, so that an erroneous write to the cell can be prevented. In addition, it is possible to avoid the problem of induced noise caused by the floating state of the drain end of the cell. Further, according to the circuit shown in FIG. 3, a secondary effect of further improving data sensing sensitivity can be obtained. That is, FIG. 4 shows the potential change of the bit line BL when, for example, inverted data is read twice consecutively in the circuit of FIG. Here, in the precharge cycle, when the precharge operation and the equalization operation are performed simultaneously, the smaller the potential difference between the bit lines, the more sensitive the data sensing becomes. According to t ₁ at the start of the precharge cycle,
Before _t2 , both bit lines BL are at ground potential, and no history of read data from the previous cycle remains, so data sensing can be performed with high sensitivity.

Note that the present invention is based on the open bit line format.
It is also effective when applied to EPROM. Also,
E ² PROM and EPROM have a nearly rectangular pattern for each memory cell, so it is advantageous to use an open bit line format in terms of ease of pattern layout and efficiency. The present invention can also be applied to the case where a folded bit line format in which the bit lines are arranged facing each other in parallel is adopted.

〔Effect of the invention〕

As described above, according to the semiconductor memory device of the present invention, a transfer gate is inserted between both input terminals of the sense amplifier and each corresponding bit line, and the transfer gate is controlled to be in an off state after the sense amplifier is sense-latched. As a result, it is possible to improve data read speed, suppress current consumption after sensing operation, and improve reliability of memory contents.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a part of the E ² PROM before the improvement leading to the present invention, and FIGS. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is a diagram showing the potential change of the bit line pair when the data read operation of the memory shown in FIG. 3 is performed twice in succession. FIG. 5 is a circuit diagram showing part of a conventional open bit line type dynamic RAM, and FIG. 6 is a diagram showing potential changes in bit line pairs during cell data read operation of the memory shown in FIG. , FIG. 7 is a circuit diagram showing part of an E ² PROM that employs the conventional open bit line format as is, and FIG. 8 is a diagram showing potential changes in the bit line pair during cell data read operation of the memory shown in FIG. It is. 1... Memory cell, 2... Dummy cell, 3 ₁ ,
3 ₂ ...transfer gate, 4 ₁ ,4 ₂ ...MOS
Transistor, BL,...Bit line, SA...
Sense amplifier, 4...Switch element for pre-charge.

Claims (1)

[Claims] 1. In an electrically data-writable nonvolatile semiconductor memory device in which data is read by sense-amplifying the potential difference between the bit lines of a pair of bit lines to which a memory cell and a dummy cell are respectively connected, the sense amplifier At least one circuit is provided between both input terminals and each bit line of the corresponding bit line pair, and is controlled to be in an on state when the bit line pair is precharged, and the potential difference between the bit lines of the bit line pair is determined by the sense voltage. A transfer gate is provided between a transfer gate that is controlled to be off after being sense latched by an amplifier, and both input terminals of the sense amplifier and the power supply, and is turned on at the time of precharging to precharge the bit line pair. A switch element is provided between each bit line of the bit line pair and a ground terminal, and is controlled to be on after the transfer gate is turned off to pull down each bit line to the ground potential. A non-volatile semiconductor memory device characterized by comprising a transistor.