JPS5817594A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To shorten a readout time by raising the level of a row line while a memory element is selected, and reading data while utilizing a different in the operation of the row line depending upon data to be written in the memory element. CONSTITUTION:The gate 43 of an N channel MOS transistor (TR)42 is held at a low level during reading operation and at a high level during other periods. A timing signal 39 is set at the low level once a row and a column decoder are set. Then, when a memory element 35 is turned off, a current for charging the parasitic capacity of a row line 57 and an output 44 flows to vary the potential of the output 44 like an increasing curve. When the memory element is written to a low threshold voltage, a short-circuit current between power sources flows through the memory element 35 in addition to a charging current, thereby obtaining a different potential increasing curve. A comparing circut 46 detects the potential difference between the output 44 and the output 45 of a circuit which generates an intermediate potential between said two curves, so that data written in the memory element appears at an output terminal 47.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a storage data read/write circuit Km for a memory element in a semiconductor memory device.

SUMMARY OF THE INVENTION An object of the present invention is to shorten the time required to read data and its repetition in a semiconductor memory device in which data is read under the control of a clock signal.

In general, a semiconductor memory device whose operation is controlled by a clock signal and reads data (hereinafter referred to as a synchronous semiconductor memory device) uses an address buffer circuit that amplifies or shapes a signal from an address input terminal, and uses an address signal to input a memory element into a memory device. a row decoder and a column decoder for selecting one memory element or a number of memory elements corresponding to the data output;
From the data detection circuit and the output circuit that outputs the data, the data readout circuit can be used, for example, as a memory element.
An example of a configuration using transistors (channel AMOB) is shown in Figure 1, where P channel 08) transistor IF
In the tying of the i-line 1, the row line 12 which is the output terminal of the N-channel MO8 transistor 3 which is a memory element
is a transistor whose gate 8 is connected to a low level at the first timing.

Summer channel Mo1l) Transistor 2 is a transistor that selects each element by the output 9 of the row decoder, and the gate 10 of the element is connected to the output line of the column decoder. Channel Mo1) transistor 4 and 1 channel M
08 transistor 7 This is a transistor for operating the P channel AM OB transistor 5 and the summer channel MOII) transistor which are data detection circuits at the time of reading. At the timing of building 1, the output line of the row decoder is activated by the address signal! If the level is high, line 112
is determined at a high level KWk. This time line 10 is set to a low level. At the second timing, P channel MO8
Gate 8#i of transistor 1 becomes high level.

Column #10 is set to selective lI- level by column decoder, and KV channel AMOE+) run raster 40 gate 1
5 is a low level, and the gate 14 of the y-channel MO8) is set to a high level AK to be in a read state. At this time, the memory element violet channel MO8) transistor 3
When the threshold voltage of the MOII transistor is high, the row line maintains the high level of the timing of wtl, and when the threshold voltage of the memory element 3 is written low, the row line maintains the high level of the timing of wtl. The N-channel MO8) output 11 is set to a low level through the transistor 2, and the data detection circuit R-channel MO8) Ranjis I5 and the mushroom channel MO
This is a circuit configuration in which the output 15 of the eight transistors 6 becomes high level and data is read out. In such a synchronous semiconductor memory device, after the ATSYS input signal is set, only the row decoder operates, setting its output 9 to a selective state of static and the row line 12 to a high level, and then turning the column decoder into a read/read state. Operate the control 10 to select the height Ilf k K
Therefore, it takes a very long time to extract the data after the address input signal is set (and the row line is set to high level regardless of the address input signal Kll). In the circuit configuration that sets the address input signal at the time of readout, the O row S% high level AK is set for the row lines of the urn, that is, the row line other than the row line to be read. The potentials of other row lines also change, and in some cases, the potentials of all rows IIO change, leading to an increase in current consumption.

The present invention eliminates this drawback, and by performing the timing operations 111 and 112 at the same time, the readout time is reduced to
It is an attempt to make it thinner. For more details ＊＊＋ゐ
The state in which the memory element is selected (f row) is raised to a high level, and at this time, the data stored in the memory element is used to determine whether the FFI & 1+MOS transistor is conductive or not. This method utilizes the fact that row lines operate differently than K, detects this, and reads data.

Based on the circuit configuration shown in Figure 1, the data written in the memory element can be extracted from Figure 2 and Figure 3.
FIG. 2 shows the case where the memory element is written to a low threshold voltage, and the memory element 511Fi enters a high threshold voltage, that is, a non-conducting state.

In FIGS. 2 and 3, P-channel MO8 transistors 16.24 are transistors for raising the row line and pull up the pair AK, and summer channel M08 transistors 17.25 are used to raise the row line by the output line 20.27 of the row decoder. Transistor for selection, N-channel MO8) The range nut 18 is a memory element, and 21 is a column line for selecting the memory element. Here, in the WtS library, the MO8 transistor is excluded because the memory element is non-conductive. Also, the state before reading data (row 1 @25, 29t) is set to a low level.

Figure 2, Figure 2! In III the output line 20 of the row decoder
27 is high level, and the output line 21 of the column decoder is high.
19.26f low v hair A K + b to, 111!
Figure 3K: Since the memory element is non-conductive, a current flows 28 to charge the parasitic capacitance of the row line 29 and the output terminal 2-8.
[The potential increases and becomes the 300 curve shown in Figure 4. l12
111, in addition to the charging current shown in FIG. ) Lanrith J
16.24 are the same, so chick 4II! 51, the potential rise curve is different. Here's the 411th! The axis is the potential of output terminal 22.24, ! The axis keeps time, 52F
The present invention detects the potential difference in the power supply 411 and reads out the data.#12+.

Figure 5 shows the first embodiment of the present invention.
Mo1) transistors 6 to s8 generate a potential for comparison! 1m11'1%allFigure 4KkFT2s50. ! 5
The y-channel M08 transistor 38 is set to output a potential between 10 and 10. P-channel kM-08 transistor 33 Transistor for pulling up the row line, N-channel MO1! l) transistor 54 is a transistor for selecting a row line by output line 40 of the row decoder;
Reference numeral 42 designates a low-level channel M08 transistor for setting the potential before the read state of row 1I57 to a low level, and its gate 45 is set to a low level during reading and to a high level at other times. 35 is a memory element, 41 is a column line, and 39 is a timing signal which is set to a low level after the row datar and column decoder are set. 46
is a comparison circuit that compares the output 44 of the memory element and the output 45 of the circuit made for potential comparison, detects the potential difference, and outputs the data written in one element to the output terminal 47. Deaaa.

According to this invention, as shown in Figure 5, it is possible to increase the capacity and speed without significantly increasing current consumption by simply creating one potential generation circuit for comparison in a 1-ton tube. An example of the comparison circuit 46 in the figure is shown in the sixth II K pit.
Reference numerals 53 and 54 are potential comparison input terminals, and 51 is the gate of an iris channel M0S transistor which provides a constant current source for the differential amplifier circuit and applies a constant voltage.

**In the example, we used a circuit in which one element is connected in parallel between the row line and the electric wire W11I, but the memory element is connected in series and in series/parallel K1! It is also possible to use a continuous circuit.

As described above, according to the present invention, the charging time of the row wire can be easily eliminated without increasing the current consumption, and a difference of 44t) between the reference signal and the output signal of the memory element can be obtained at the time of reading out. Since the data is output, it is possible to shorten the output time. .

[Brief explanation of the drawing]

Figure s11 is an example of a data readout circuit for a semiconductor storage device.
In the Sa memory element, the violet channel 01) range terminal, 9 is the output line of the row decoder. 10 is a column line, 8, 15.14 Fi tie power signal. 1121El, 3rd is the cape circuit when writing data to the memory element, 16.24 P channel MO transistor J, 17.25 HM channel AMOB transistor, 18 is the memory element y Channel hMO8 transistor, 20.27 is the row decoder output line, 21
The column line 19.26 is a timing signal. IIm Calculate 411 2 It, IIE S
1-. 22.28-t-tL tear potential operation diagram 31.3
0″t&. No. 511 is an embodiment of the present invention) 1 excerpt, 53 pages 55.42
is the actual reader output circuit of the memory element, 36 to 58 are the reference signal generation circuits, and 46-digit comparison a is 1h? ), 5856
FiP channel AMOB) transistor, 34. '37゜3
8.42 is the y-channel M08 transistor, 55 is the memory element y-channel AMOB) run riff 2,401
The output line of the row decoder, 41 is the column line. 59.45 is a timing signal. The circuit shown in the figure is an example of a comparator circuit, in which 48.50 is a transistor (AMOB), 53.54 is an input terminal, and 55 is a constant voltage input terminal. That's it 10 - 2nd ai 3rd! ! 1 1114m

Claims (1)

[Claims] A memory element consisting of MO transistors written in a matrix shape, a 0 row decoder and a column decoder for selecting the memory element, a detection circuit for reading data, and an input/output circuit. In a semiconductor memory device operated by a timing signal, the data detection lIl
The source terminal of the first Mo8) terminal constituting the main element is connected to the power supply terminal of Building 1. Connect the drain terminal to the row line 11! Then, connect it to the drain terminal of the Mo1) transistor of Proverb 2 through the selection circuit of the row line', and connect the source terminal of the Mo1 transistor of Proverb 2 to the second -111Kil.
ole) drain terminal of transistor or data detection gsi
* Compare the circuit configuration to connect awiK. Great! 21E) Mos) The gate of the transistor is connected to a tie-up signal, and a comparator circuit detects the temporal potential fluctuation of the drain terminal when the transistor is in a conductive state and reads the data. A semiconductor storage device.