CN101763887A - Reading device of storage unit and reading method thereof - Google Patents
Reading device of storage unit and reading method thereof Download PDFInfo
- Publication number
- CN101763887A CN101763887A CN200910198986A CN200910198986A CN101763887A CN 101763887 A CN101763887 A CN 101763887A CN 200910198986 A CN200910198986 A CN 200910198986A CN 200910198986 A CN200910198986 A CN 200910198986A CN 101763887 A CN101763887 A CN 101763887A
- Authority
- CN
- China
- Prior art keywords
- transistor
- current
- storage unit
- reading
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a reading device of a storage unit and a reading method thereof, which are used for reading the data stored in a selected storage unit in a storage. The storage unit outputs unit current as the input of the reading device of the storage unit according to the storage unit; the unit current finally appears as output current of a reading and amplifying circuit by a constant current source circuit under the feedback of a comparator; and compared with a reference current, the data stored in the storage unit can be judged and output. The unit current serves as the input/output comparison object of the reading device, thereby improving the reading speed and being more applicable for the storages such as a high-speed flash memory; meanwhile, the drain voltage of a transistor in the constant current source circuit can be clamped down to be a reference voltage by the comparator, so that the reading device can work in a normal state in a linear zone, thereby widening the voltage range of a working power supply of the reading device of the storage unit and greatly improving the data reading accuracy in the actual data reading process.
Description
Technical field
The invention belongs to the semiconductor memory field, relate to reading of semiconductor memory cell data, be specifically related to a kind of reading device and read method of memory cell.
Background technology
Semiconductor memory generally includes many word line (Word-line, WL), bit line (Bit-line, BL) and the storage unit (Memory-cell that is positioned at each intersection point configuration of word line and bit line, MC), each storage unit is in order to writing down the data of a byte, realizes output to data that storer is stored by reading data on the selected storage unit.Because memory array is classified the virtual earth array structure as, does not have real common source in this array, therefore, reads in the process in storage unit, will be positioned at the bit line ground connection that storage unit connected on next door, selected unit usually, be considered as ground wire.
U.S. Pat 6529412 B1 provide a provenance end read method, and Fig. 1 is the source voltage terminal memory cell data read method circuit diagram that this patent provides.As shown in Figure 1, sensing circuit 100 is the voltage sensing circuit, the electric current I that flows through on the selected then storage unit
Cell110 are converted to memory cell voltages V via current-voltage converter 130
CellAfter 150, be input to sensor amplifier (Sense Amplifier, S.A.) 170 end of oppisite phase, and after reference current Iref 120 is converted to reference voltage Vref 160 via current-voltage converter 140, be input to the in-phase end of sensor amplifier 170, the output of sensor amplifier 170 is the sense data 180 of this storage unit, and wherein, current-voltage converter 130,140 is integrated in the pre-amplification circuit 705.Yet, adopt the voltage reading access method will bring bigger time-delay, make the memory data reading speed slower, be not suitable for high speed storeies such as NOR flash memory system.
Be compared to the voltage reading access method, the method that directly reads selected memory cell current has higher speed, greatly reduces time for reading.
Fig. 2 is a drain terminal electric current read method circuit diagram commonly used in the prior art.As shown in Figure 2, memory array comprises many word line WL, bit line BL and is positioned at word line WL and the storage unit of bit line BL crossover location, wherein, the control gate that word line will be positioned at the storage unit MOS transistor of delegation links together, and the source electrode that bit line then will be positioned at the storage unit MOS transistor of same row links together.As shown in Figure 2, when selecting the data of reading cells A, gating control signal YA, YB are high level, gate transistor MC1, MC2 are in conducting state, storage unit A is selected, at this moment, word line WL＜m that storage unit A is expert at〉place noble potential, and other word lines WL places electronegative potential, and storage unit A is in conducting state.When initial, all bit line BL all place reference voltage Vref, and this reference voltage Vref value is about 1.2V, subsequently, bit line BL＜the k that source S connected of storage unit A〉ground connection, bit line BL＜k+1 that its drain D connected〉then connect reading device 200, other bit lines BL is all unsettled.At this moment, bit line BL＜k+1〉on electric current be the electric current I of storage unit A
A, under the retroactive effect of comparer I1, transistor Mi drain terminal D voltage is clamped down on is reference voltage Vref, cell current I
AAs the input current of reading amplifying circuit 201, be input in the constant-current source circuit of forming by transistor M3, M4 via transistor Mi, and on transistor M4, produce the equal image current I of current value with it
4, this electric current 210 compares with reference current Iref, when current value during greater than reference current Iref, reads " 1 ", if current value less than reference current Iref, is then read " 0 ".
Be higher than the voltage reading access method from the data reading speed of drain terminal electric current read method, then, in this method, data reading circuit connects the bit line of selected storage unit drain terminal, reads circuit and reads required reference voltage Vref of amplifying circuit and pre-charge voltage V
DDMagnitude of voltage is very approaching, but this makes that the operating voltage range of reading transistor M3, M4 in the amplifying circuit 201 is very little, causes the inaccurate of reading numerical values easily.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of memory cell reading device, quickening memory cell data reading speed, but and increase working power voltage scope.
For solving the problems of the technologies described above, memory cell reading device provided by the invention is in order to read the data of selected cell stores in the storer, this storage unit is according to the data output unit electric current of being stored, and the output current of this storage unit source end is as the input of memory cell reading device of the present invention, under the retroactive effect of first comparer and second comparer, show as the 3rd transistorized electric current, and compare with reference current, judge according to this and export the data that storage unit is stored.
Concretely, memory cell reading device provided by the invention comprises:
Reference unit is in order to provide reference voltage and reference current;
Read amplifying circuit, comprise first constant-current source circuit and the first transistor, wherein: first constant-current source circuit comprises transistor seconds and the 3rd transistor, and the source end of the first transistor is connected with the source end of transistor seconds;
Second constant-current source circuit comprises the 4th transistor and the 5th transistor;
First comparer in order to receiving reference voltage, and is all clamped down on the first transistor and the 5th transistorized drain voltage and to be reference voltage;
Second comparer in order to receiving reference voltage, and is clamped down on the 4th transistorized drain voltage and is reference voltage.
In the memory cell reading device provided by the invention, the first transistor, the 4th transistor, the 5th transistor are nmos pass transistor, transistor seconds, the 3rd transistor are the PMOS transistor, and four, the 5th transistorized source end and the equal ground connection of second, third transistorized drain terminal, in addition, in this memory cell reading device, it is shared that first comparer can be read amplifying circuit by multichannel.
The present invention also provides a kind of memory cell read method, the above-mentioned memory cell reading device that provides is provided this method, in order to read the data of a certain storage unit in the storer, this storage unit is exported a cell current according to the data of being stored, and this method comprises:
Receive this cell current;
Receive reference current;
This cell current is read amplifying circuit through the constant-current source circuit input;
This cell current shows as the output of sensor amplifier, and compares with reference current, judges the data that this storage unit of output is stored according to this.
In the memory cell read method provided by the invention, reference current is provided by a reference unit, this reference unit is also exported a reference voltage simultaneously, this reference voltage range is 0.10V～0.80V, and the interconnective two transistor drain voltage of grid of composition constant-current source circuit is all clamped down under the retroactive effect of comparer is this reference voltage.
Technique effect of the present invention is that the output unit electric current of employing storage unit has reduced the data read time greatly as the input and the output comparison other of reading device, improves reading speed, is more suitable for the application of memory devices such as high speed flash memory.Meanwhile, in memory cell reading device provided by the invention and the read method, adopt comparer that the 4th transistor and the 5th transistorized drain voltage are clamped down on and be reference voltage, make it can enter normal operating conditions at linear zone, but increased the working power voltage scope of memory cell reading device, read in the process in real data, improved the accuracy of data read greatly.
Description of drawings
Fig. 1 is a source voltage terminal memory cell data read method circuit diagram;
Fig. 2 is a drain terminal current storage device method for reading data circuit diagram;
Fig. 3 a is a source provided by the invention end current memory cell data reading device working circuit diagram;
Fig. 3 b is a memory cell reading device amplification circuit diagram provided by the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Fig. 3 a is the storage reading apparatus working circuit diagram according to source provided by the invention end current memory cell data reading device one better embodiment.
Memory cell reading device 300 is in order to read the data of selected cell stores in the storer.In this embodiment, selected storage unit A is according to the data output unit electric current I of being stored
A, and the output current I of this storage unit A source end S
AElectric current input as memory cell reading device 300 under the retroactive effect of the first comparer I1 and the second comparer I2, via the second constant current source electric current 320, shows as the electric current I of the 3rd transistor M3
3, and compare with reference current Iref, judge according to this and export the data DOUT that storage unit A is stored.
Shown in Fig. 3 a, memory construction comprises many word line WL and bit line BL, and is provided with storage unit at word line WL and bit line BL crossover location.Every word line WL connects the storage unit control gate that is positioned at delegation, and bit line BL connects the storage unit source/drain terminal that is positioned at same row.
Memory cell reading device 300 amplification circuit diagrams that Fig. 3 b provides for this embodiment.
Shown in Fig. 3 b, the memory cell reading device 300 that this embodiment provides comprises: reference unit 301, read amplifying circuit 302, the second constant-current source circuits, 320, the first comparer I1 and the second comparer I2.Wherein, reference unit 301 is in order to provide reference voltage Vref and reference current Iref; Second constant-current source circuit 320 comprises the 4th transistor M4 and the 5th transistor M5, in order to the electric current I with storage unit A
ABe converted to the image current I of the 5th transistor M5
5Read amplifying circuit 302 and comprise first constant-current source circuit 310 and the first transistor Mi, wherein: first constant-current source circuit 310 comprises transistor seconds M2 and the 3rd transistor M3, and the source end S of the first transistor Mi is connected with the source end S of transistor seconds M2; The first comparer I1 in-phase input end is in order to receive reference voltage Vref, inverting input is in order to connect the drain terminal D of the 5th transistor M5 and the first transistor Mi, the drain voltage of the 5th transistor M5 and the first transistor Mi all clamped down on be reference voltage Vref, its output terminal connects the control gate G of the first transistor Mi; The second comparer I2 in-phase input end is in order to receiving reference voltage Vref, and inverting input is in order to connect the drain terminal D of the 4th transistor M4, the drain voltage of the 4th transistor M4 clamped down on be that reference voltage Vref, its output terminal connect the control gate G of the 4th transistor M4.
As most preferred embodiment, the first transistor Mi, the 4th transistor M4, the 5th transistor M5 are nmos pass transistor, transistor seconds M2, the 3rd transistor M3 are the PMOS transistor, and the equal ground connection GND of drain terminal D of the source end S of the 4th transistor M4, the 5th transistor M5 and transistor seconds M2, the 3rd transistor M3.
As optional embodiment, it is shared that the first comparer I1 of memory cell reading device 300 is read amplifying circuit 302 by multichannel.
In the storage unit A data read process, word line WL＜m that storage unit A is expert at〉place noble potential, other word lines WL places electronegative potential, gating control signal YA, YB are noble potential, the gating circuit conducting that transistor MC1 and transistor MC2 form, at this moment, storage unit A is selected.Under the original state, all bit line BL all place reference voltage Vref, and reference voltage level Vref scope is 0.10V～0.80V; In the data read process, bit line BL＜k+1 that storage unit A drain terminal D is connected〉place pre-charge voltage V
DD, V
DDBe the normal working voltage of storage unit A, bit line BL＜k that storage unit A source end S is connected〉connect data fetch device 300, BL is unsettled for other bit lines.At this moment, the source-drain current I of storage unit A
ADirect input current I as storage unit reading device 300 second constant-current source circuits 320
4Flow into the 4th transistor M4, and on the 5th transistor M5, produce and storage unit A source-drain current I
AThe image current I that size is identical
5, the image current I of the 5th transistor M5
5Be input to as input current and read in the amplifying circuit 302, and via the input current I of the first transistor Mi as first constant-current source circuit 310
2Flow into transistor seconds M2, and show as the image current I of the 3rd transistor M3
3, as the output of reading amplifying circuit 302.Image current I on the 3rd transistor M3
3Iref compares with reference current, and judges the data DOUT that this storage unit A of output is stored according to this.
As another embodiment, the constant-current source circuit 310/320 of memory cell reading device 300 also comprises the impedance device of connecting with transistor M2/M3/M4/M5, the image current value and the cell current I of constant-current source circuit 310/320 output
AEqual or proportional, cell current I
AShow as finally that current value equates with it or proportional the 3rd transistor M3 on image current I
3, as the output of reading amplifying circuit 302.Image current I on the 3rd transistor M3
3Iref compares with reference current, and judges the data DOUT that this storage unit A of output is stored according to this.
This embodiment also provides a memory cell read method, and this method is a storage unit source end electric current read method.
The source end current storage method for reading data that this embodiment provides is in order to read the data of a certain storage unit in the storer, with reference to the circuit diagram of memory cell reading device shown in Fig. 3 a/3b, storage unit A is exported a cell current I according to the data of being stored
A, this cell current I
AReading object and comparison other as method for reading data that this embodiment provides.
Concrete must saying, the memory cell read method that this embodiment provides comprises:
Receive this cell current I
A
Receive reference current Iref;
This cell current I
ARead amplifying circuit 302 through constant-current source circuit 320 inputs;
This cell current I
AShow as the output I that reads amplifying circuit 302
3, and compare with reference current Iref, judge the data that this storage unit A of output is stored according to this.
In this embodiment, reference current Iref is provided by reference unit 301, and this reference unit 301 is also exported a reference voltage Vref simultaneously, and this reference voltage Vref scope is 0.10V～0.80V.
As most preferred embodiment, second constant-current source circuit 320 comprises the 4th transistor M4 and the 5th transistor M5, four, the grid G of the 5th transistor M4, M5 links to each other, under the retroactive effect of the second comparer I2 and the first comparer I1, the drain voltage of the 4th transistor M4 and the 5th transistor M5 is clamped down on respectively is reference voltage Vref.Cell current I
AOn the 5th transistor M5, produce the equal image current I of current value with it via the 4th transistor M4
5, image current I
5Be input to first constant-current source circuit 310 via the first transistor Mi that reads in the amplifying circuit 302, and on the 3rd transistor M3, produce image current I via transistor seconds M2
3, this image current I
3Current value still with cell current I
AIdentical, as the output of reading amplifying circuit 302, and compare with reference current Iref, export the data DOUT that this storage unit A is stored according to this.
As optional embodiment, constant-current source circuit 310/320 also comprises the impedance device of connecting with transistor M2/M3/M4/M5, cell current I
ABehind constant-current source circuit 310/320, outgoing mirror image current value that is showed and cell current I
AEquate or proportional, finally show as the image current I of the 3rd transistor M3 in the output amplifier 302
3, as the output of reading amplifying circuit 302, and compare with reference current Iref, export the data DOUT that this storage unit A is stored according to this.
Data read that this memory cell read method is related and data comparison other are electric current, and its reading speed is better than with the voltage source of object/drain terminal voltage reading access method as a comparison.In addition, because this method adopts source end electric current as reading object, involved reference voltage Vref value is 0.10V～0.80V in reading process, much smaller than transistorized operating voltage V
DDAnd in the method, the the 4th, the 5th transistor M4 in second constant-current source circuit 320, M5 drain voltage are all clamped down on is reference voltage Vref, four, the 5th transistor M4, M5 can enter duty at linear zone, but increased the working power voltage scope significantly, made sense data more accurate.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the instructions.
Claims (10)
1. memory cell reading device comprises:
Reference unit is in order to provide reference voltage and reference current;
Read amplifying circuit, comprise first constant-current source circuit and the first transistor, wherein, first constant-current source circuit comprises transistor seconds and the 3rd transistor, and the source end of the first transistor is connected with the source end of transistor seconds;
It is characterized in that, also comprise:
Second constant-current source circuit comprises the 4th transistor and the 5th transistor;
First comparer in order to receiving described reference voltage, and is clamped down on described the first transistor and the described the 5th transistorized drain voltage and is described reference voltage;
Second comparer in order to receiving described reference voltage, and is clamped down on the described the 4th transistorized drain voltage and is described reference voltage.
2. memory cell reading device according to claim 1, it is characterized in that, the in-phase input end of described first comparer is in order to receive reference voltage, inverting input connects described the first transistor and the described the 5th transistorized drain terminal, and its output terminal connects the control gate of described the first transistor.
3. memory cell reading device according to claim 1, it is characterized in that, the in-phase input end of described second comparer is in order to receive reference voltage, inverting input connects the described the 4th transistorized drain terminal, and its output terminal connects described the 4th transistor and the described the 5th transistorized control gate.
4. according to claim 1 or 2 or 3 described memory cell reading devices, it is characterized in that described the first transistor, the 4th transistor, the 5th transistor are nmos pass transistor, described transistor seconds, the 3rd transistor are the PMOS transistor.
5. memory cell reading device according to claim 4 is characterized in that, described the 4th transistor and the described the 5th transistorized source end and described transistor seconds and the equal ground connection of the described the 3rd transistorized drain terminal.
6. memory cell reading device according to claim 5, it is characterized in that described device also comprises gating circuit, described gating circuit comprises the transistor of one or more series connection, its input signal is the gating control signal, in order to the storage unit of the selected reading of data of wanting.
7. memory cell read method, in order to read the data of a storage unit in the storer, described storage unit is exported a cell current according to the data of being stored, this method adopts the described reading device of claim 1 to finish reading of cell data, it is characterized in that, this method is from storage unit source end reading unit electric current, and itself and reference current are compared, and judges the data that this storage unit of output is stored according to this.
8. memory cell read method according to claim 7 is characterized in that, this method comprises:
The receiving element electric current;
Receive reference current;
Described cell current is read amplifying circuit through the constant-current source circuit input;
Described cell current shows as the output of reading amplifying circuit, and compares with described reference current, judges the data that this storage unit of output is stored according to this.
9. memory cell read method according to claim 8 is characterized in that, described reference current provides by a reference unit is defeated, and described reference unit also provides a reference voltage.
10. memory cell read method according to claim 9, it is characterized in that, described constant-current source circuit is made up of the transistor that two grids link together, the equal ground connection of described two transistor source end, and drain voltage is all clamped down under the retroactive effect of comparer is reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910198986 CN101763887B (en) | 2009-11-18 | 2009-11-18 | Reading device of storage unit and reading method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910198986 CN101763887B (en) | 2009-11-18 | 2009-11-18 | Reading device of storage unit and reading method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101763887A true CN101763887A (en) | 2010-06-30 |
| CN101763887B CN101763887B (en) | 2013-06-05 |
Family
ID=42494998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910198986 Active CN101763887B (en) | 2009-11-18 | 2009-11-18 | Reading device of storage unit and reading method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101763887B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103106916A (en) * | 2012-12-21 | 2013-05-15 | 上海宏力半导体制造有限公司 | Storage and read circuit and comparison circuit thereof |
| CN103177749A (en) * | 2013-02-01 | 2013-06-26 | 上海宏力半导体制造有限公司 | Read voltage generation circuit |
| CN103559904A (en) * | 2013-11-05 | 2014-02-05 | 苏州贝克微电子有限公司 | Real amplifier of single-end data sensing |
| CN104505123A (en) * | 2014-12-05 | 2015-04-08 | 深圳市国微电子有限公司 | Read application circuit of anti-fuse storage |
| CN106024063A (en) * | 2016-07-19 | 2016-10-12 | 北京兆易创新科技股份有限公司 | Data reading device and method of nonvolatile memory |
| CN106024062A (en) * | 2016-07-19 | 2016-10-12 | 北京兆易创新科技股份有限公司 | Data reading device and method of nonvolatile memory |
| WO2020211468A1 (en) * | 2019-04-15 | 2020-10-22 | 浙江驰拓科技有限公司 | Read circuit of memory, and memory |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6246621B1 (en) * | 1999-04-23 | 2001-06-12 | Oki Electric Industry Co., Ltd. | Semiconductor memory device generating accurate internal reference voltage |
| CN1479315A (en) * | 2002-08-27 | 2004-03-03 | 力旺电子股份有限公司 | Non volatibility storage |
| CN1866389A (en) * | 2005-05-19 | 2006-11-22 | 上海宏力半导体制造有限公司 | Electric current type sensing apparatus and method for high-density multi-port cache |
| US20080273394A1 (en) * | 2007-05-02 | 2008-11-06 | Infineon Technologies Ag | Symmetric differential current sense amplifier |
-
2009
- 2009-11-18 CN CN 200910198986 patent/CN101763887B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6246621B1 (en) * | 1999-04-23 | 2001-06-12 | Oki Electric Industry Co., Ltd. | Semiconductor memory device generating accurate internal reference voltage |
| CN1479315A (en) * | 2002-08-27 | 2004-03-03 | 力旺电子股份有限公司 | Non volatibility storage |
| CN1866389A (en) * | 2005-05-19 | 2006-11-22 | 上海宏力半导体制造有限公司 | Electric current type sensing apparatus and method for high-density multi-port cache |
| US20080273394A1 (en) * | 2007-05-02 | 2008-11-06 | Infineon Technologies Ag | Symmetric differential current sense amplifier |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103106916A (en) * | 2012-12-21 | 2013-05-15 | 上海宏力半导体制造有限公司 | Storage and read circuit and comparison circuit thereof |
| CN103106916B (en) * | 2012-12-21 | 2016-09-28 | 上海华虹宏力半导体制造有限公司 | Memorizer and reading circuit, a kind of comparison circuit |
| CN103177749A (en) * | 2013-02-01 | 2013-06-26 | 上海宏力半导体制造有限公司 | Read voltage generation circuit |
| CN103177749B (en) * | 2013-02-01 | 2017-02-08 | 上海华虹宏力半导体制造有限公司 | Read voltage generation circuit |
| CN103559904A (en) * | 2013-11-05 | 2014-02-05 | 苏州贝克微电子有限公司 | Real amplifier of single-end data sensing |
| CN104505123A (en) * | 2014-12-05 | 2015-04-08 | 深圳市国微电子有限公司 | Read application circuit of anti-fuse storage |
| CN104505123B (en) * | 2014-12-05 | 2018-04-20 | 深圳市国微电子有限公司 | A kind of reading application circuit of antifuse memory |
| CN106024063A (en) * | 2016-07-19 | 2016-10-12 | 北京兆易创新科技股份有限公司 | Data reading device and method of nonvolatile memory |
| CN106024062A (en) * | 2016-07-19 | 2016-10-12 | 北京兆易创新科技股份有限公司 | Data reading device and method of nonvolatile memory |
| CN106024062B (en) * | 2016-07-19 | 2023-12-05 | 兆易创新科技集团股份有限公司 | Data reading device and method of nonvolatile memory |
| WO2020211468A1 (en) * | 2019-04-15 | 2020-10-22 | 浙江驰拓科技有限公司 | Read circuit of memory, and memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101763887B (en) | 2013-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101763887B (en) | Reading device of storage unit and reading method thereof | |
| CN102354529B (en) | Semiconductor memory device | |
| KR100226597B1 (en) | A circuit and method for detecting distribution of threshold value in cell | |
| US5608676A (en) | Current limited current reference for non-volatile memory sensing | |
| US8325536B2 (en) | Current sink system for source-side sensing | |
| CN105518798B (en) | Semiconductor storage and storage system | |
| US10475510B2 (en) | Leakage compensation read method for memory device | |
| US8213234B2 (en) | Current sink system for source-side sensing | |
| US8773934B2 (en) | Power line compensation for flash memory sense amplifiers | |
| CN110610730B (en) | Sensitive amplifier | |
| US20140003129A1 (en) | Semiconductor memory apparatus and method of operating using the same | |
| CN101241763B (en) | Semiconductor memory device | |
| US9514788B1 (en) | Differential amplifier circuit, voltage regulator, and semiconductor memory device including the same | |
| CN102394109A (en) | Flash memory | |
| US20110026346A1 (en) | Self-timed low power sense amplifier | |
| CN104937718A (en) | High speed sensing for advanced nanometer flash memory device | |
| US20150194193A1 (en) | Memory and reading method thereof, and circuit for reading memory | |
| CN104900261A (en) | Variable resistor storage device and input method | |
| CN105185404B (en) | charge transfer type sense amplifier | |
| CN101276638A (en) | Semiconductor memory device using ferroelectric device and method for refresh thereof | |
| KR101105434B1 (en) | Apparatus and method for evaluating a current sensing characteristic for a semicondoctor memory device | |
| US20120257457A1 (en) | Method and apparatus for pre-charging data lines in a memory cell array | |
| US5253210A (en) | Paritioned bit line structure of EEPROM and method of reading data therefrom | |
| JP2002008386A (en) | Semiconductor integrated circuit device | |
| CN101872642A (en) | Storing and reading method for random access memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140509 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20140509 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |