JP2002008386A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which the capacitance of the main body side and the capacitance o a reference side can be adjusted more accurately and which has a strong noise-proof characteristics, and increase of area is suppressed. SOLUTION: This device is provided with a first column tree including wiring groups (Bi:BL0, MBL0-01, IDL01) by which information in a first memory cell is transmitted, a second column tree including wiring groups (Bi:BL2, MBL0-23, IDL23) by which information in a second memory cell is transmitted, and a differential amplifier amplifying potential difference between the potential of a data line(DL) and the potential of a reference data line(RDL). And, further, the device is provided with a column switching gate (0101) wherein, when the first memory cell is selected, the first column tree is coupled to the data line(DL), and the second column tree is coupled to the reference data line (RDL), otherwise when the second memory cell is selected, the second column tree s coupled to the data line(DL), and the first column tree is coupled to the reference data line(RDL).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a balance between a main body capacitance and a reference capacitance in a sense circuit and an improvement in read speed.

[0002]

2. Description of the Related Art A nonvolatile semiconductor memory (EEPROM) will be described as an example of a semiconductor memory device.

Some nonvolatile semiconductor memories are capable of simultaneously erasing data from a plurality of memory cells, and this type of nonvolatile semiconductor memory is generally called a flash memory.

(Structure of Memory Cell) FIG. 32 is a sectional view showing a storage element (hereinafter, memory cell) which is a basic unit of a nonvolatile semiconductor memory. FIG. 32 shows a memory cell called a stack gate type, out of several types of memory cells.

As shown in FIG. 32, an N-type well 3102 is formed in, for example, a P-type silicon substrate 3101. N
In the mold well 3102, a P-type well 3103 is formed. In the P-type well 3103, an N-type source region 3104 and an N-type drain region 3105 are formed separately from each other. A gate insulating film 3106 is formed on the P-type well 3103 between the N-type source region 3104 and the N-type drain region 3105. On the gate insulating film 3106, a floating gate 3107
Are formed. On the floating gate 3107, an insulating film 3108 on the floating gate is formed. Insulating film on floating gate 31
On 08, a control gate 3109 is formed.

(Operation of Memory Cell) Next, the operation of the memory cell shown in FIG. 32 will be described.

When writing data, an N-type drain region
For example, 6V is applied to 3105, and N-type source region 3104, P
For example, 0 V (ground potential) is applied to each of the mold well 3103, the N-well 3102, and the P-type substrate 3101. Further, for example, 10 V is applied to the control gate 3109. The floating gate 3107 is not connected to an external power supply. Therefore, the potential VF of the floating gate 3107 depends on the capacitance C1 between the control gate 3109 and the floating gate 3107 and the floating gate 3107.
Coupling ratio C1 / (C1 + C2) with the capacitance C2 between the P-type well 3103, the potential of the control gate 3109,
It is uniquely determined from the potential of the N-type source region 3104, the potential of the N-type drain region 3105, and the potential of the P-type well 3103.

[0008] By biasing the memory cell in this way, a strong electric field is generated between the N-type source region 3104 and the N-type drain region 3105, and hot electrons having high energy are generated. Some of the generated hot electrons are
Over the barrier of the gate insulating film 3106, it is injected into the floating gate 3107. As a result, data is written to the memory cell.

When erasing data, electrons are extracted from the floating gate 3107 of the memory cell in which data has been written. The following method may be used for this erasure.

For example, 10 V is applied to each of the N-type well 3102, the P-type well 3103, and the N-type source region 3104. Further, for example, −7 V is applied to the control gate 3109.

By biasing the memory cell in this manner, a portion of the gate insulating film 3106 between the P-type well 3103 and the floating gate 3107 and a portion between the N-type source region 3104 and the floating gate 3107 A strong electric field (10 MV / c
m or more). Under such a strong electric field, a quantum mechanical Fowler-Nordheim tunnel current (FN tunnel current) flows through the gate insulating film 3106, and electrons in the floating gate 3107 are transferred to the P-type well 3103 and N It is withdrawn into the mold well 3104. As a result, data is erased from the memory cell.

When data is read, the fact that the potential of the floating gate of a memory cell in which data is written is different from the potential of the floating gate of a memory cell in which data is erased is used.

Specifically, when an N-type channel is to be formed in a P-type well 3103 immediately below a floating gate 3107,
Since a memory cell in a written state stores electrons in the floating gate 3107, forming a channel in a memory cell in a written state means forming a channel in a memory cell in an erased state (that is, storing no electrons). You need to be more positively charged than you do. At this time, the potential VF of the floating gate is equal to the coupling ratio C1 as described above.
/ (C1 + C2), the potential of the control gate 3109, the potential of the N-type source region 3104, the potential of the N-type drain region 3105, and the potential of the P-type well 3103. For this reason,
The potential of the control gate 3109 can be controlled to such a potential that “a channel is not formed in a memory cell in a written state, but a channel is formed in a memory cell in an erased state”. Such a potential is called a reading potential. Therefore, a read potential is applied to the control gate 3109 while giving an appropriate potential difference between the N-type source region 3104 and the N-type drain region 3105.

By biasing the memory cell in this way, if the memory cell is in a write state, no channel is formed and almost no current flows between the N-type source region 3104 and the N-type drain region 3105. Can be

Conversely, if the memory cell is in the erased state, a channel is formed, and a state in which a current determined by the potential difference between these and the potential of the floating gate 3107 flows between the N-type source region 3104 and the N-type drain region 3105 is obtained. Can be

As described above, when a read potential is applied to the control gate 3109, it is determined whether a current larger than the reference current flows between the N-type source region 3104 and the N-type drain region 3105 by a read circuit described later. The information stored in the memory cell is read by the determination by the unit.

(Internal system of nonvolatile semiconductor memory)
FIG. 33 is a block diagram showing an internal system of the nonvolatile semiconductor memory.

As shown in FIG. 33, the nonvolatile semiconductor memory includes an input circuit section 3201, a control circuit section 3202, a memory cell array 3203, a booster circuit section 3204, and a row decoder 320.
5, column decoder 3206, source / well decoder 320
7. It has a write circuit section 3208, a read circuit section 3209, and an output circuit section 3210.

The control signal and the address signal are input to the control circuit section 3202 via the input circuit section 3201.

The control circuit 3202 generates an internal control signal based on the input control signal,
4, row decoder 3205, column decoder 3206, source
The signal is output to the well decoder 3207, the readout circuit unit 3209, and the like.

The control circuit section 3202 converts the input address signal into a row selection internal address signal,
And an internal address signal for column selection, and outputs it to a row decoder 3205, a column decoder 3206, and the like.

The memory cell array 3203 includes, for example, FIG.
The memory cell shown in FIG. 3 has m rows (X coordinate) and n columns (Y coordinate)
Are arranged in a matrix.

The booster circuit section 3204 generates a boosted voltage (high voltage) used in a write operation, an erase operation, and a read operation.

The row decoder 3205 decodes a row selection internal address signal (row address signal) and outputs a signal indicating the coordinates (X coordinate) of the word line specified by the row address signal.

The column decoder 3206 decodes the column selection internal address signal (column address signal) and outputs a signal indicating the coordinate (Y coordinate) of the bit line specified by the column address.

The source / well decoder 3207 outputs a potential applied to the P-type well 3103 and a potential applied to the source line according to each of the “read mode”, “write mode”, and “erase mode”. I do.

The write circuit unit 3208 performs a write operation and a verify operation.

The read circuit unit 3209 performs a read operation during
The data read from the memory cell is determined.

The output circuit section 3210 outputs the read data determined by the read circuit section 3209 during a read operation.

(Memory Cell Array) FIG. 34 is a circuit diagram showing a memory cell array. FIG. 34 shows a circuit of a memory cell array of a NOR type EEPROM as an example of the memory cell array.

As shown in FIG. 34, a plurality of memory cells are arranged in a matrix of m rows and n columns, and a memory cell array 3203 including m × n memory cells is formed (m and n are 2 respectively). Is a natural number above).

In FIG. 34, for simplicity, m = 3,
A memory cell array including 3 × 4 memory cells where n = 4 is shown). These m × n memory cells are formed in the same P-type well 3103, respectively.
An erase unit including × n memory cells is configured.

Control gates G of m memory cells belonging to the same row are commonly connected to word lines WL (WL0 to WL2). Also, the drain regions (D) of the n memory cells belonging to the same column are
L (BL0 to BL3) are commonly connected. Further, the sources S of the mxn memory cells formed in the same P-type well 3103 are commonly connected to a source line SL.

At the time of the write operation and the read operation, one specific memory cell is selected. At this time, one of the m word lines WL is selected by the row decoder 3205, and one of the n in-array bit lines BL is selected by the column decoder 3206. As a result, one specific memory cell is selected, and writing or reading is performed on the selected memory cell.

The erase operation is performed simultaneously on all the m × n memory cells formed in the same P-type well 3103.

(Column Decoder) FIG. 35 is a circuit diagram showing a first example of the column decoder 3206. In this specification, the column decoder shown in FIG. 35 is referred to as “type A”. FIG. 36 shows a block configuration of a nonvolatile semiconductor memory having a “type A” column decoder.

As shown in FIGS. 35 and 36, the "type A" column decoder includes a first column selection decoder 34.
01 is provided in a unit in which a plurality of blocks are put together. Therefore, the first column selection signal Hi (H0 to H3) is
The above units are common.

On the other hand, the second column selection decoder 3403
Is provided for each block. For this reason,
Second column selection signal Di (Bi: D0 to Bi: D1, Bj: D0 to Bj: D1)
Are individualized in the above block.

The column selection internal address signal is supplied to a first column selection decoder 3401 and a second column selection decoder.
Entered in 3403.

The first column selection decoder 3401 decodes a column selection internal address signal and selects and activates one of a plurality of first column selection signals H0 to H3. As a result, one of the first column gates 3402-0 is turned on, and one of the bit lines Bi: BL0 to Bi: BL3 is connected to the main bit line Bi: MBL0. Similarly, the first column gate 3402-
One of the gates is turned on, and the bit lines Bi: BL4 to Bi:
One of BL7 is connected to the main bit line Bi: MBL1,..., One of the first column gates 3402-3 is turned on,
One of the bit lines Bj: BL4 to Bj: BL7 is the main bit line Bj: MBL
Connected to 1.

The second column selection decoder 3403 decodes the column selection internal address signal and selects one of a plurality of second column selection signals Bi: D0, Bi: D1, Bj: D0, Bj: D1. Activate. As a result, the second column gates 3404-Bi, 3
One of the gates in 404-Bj is turned “on” and the main bit line
One of Bi: MBL0, Bi: MBL1, Bj: MBL0, and Bj: MBL1 is connected to the data line DL.

In this way, one of the plurality of bit lines is alternatively connected to one of the main bit lines,
One of the plurality of main bit lines is alternatively connected to one of the data lines.

FIG. 37 is a circuit diagram showing a second example of the column decoder 3206. In this specification, the column decoder shown in FIG. 37 is referred to as “type B”. FIG. 38 shows a block configuration of a nonvolatile semiconductor memory having a "type B" column decoder.

As shown in FIGS. 37 and 38, the "type B" column decoder includes a first column selection decoder 36.
01 is provided for each block. Therefore, the first column selection signal Hi (Bi: H0 to Bi: H3, Bj: H0 to Bj:
H3) is individual in the above block.

On the other hand, the second column selection decoder 3603
Are provided in a unit in which a plurality of blocks are put together. In this example, one set is provided for a unit in which two blocks of blocks Bi and Bj are put together. Therefore, the second column selection signal Di (D0, D1) is common in the above units.

The column selection internal address signal is supplied to a first column selection decoder 3601 and a second column selection decoder.
Entered in 3603.

The first column selection decoder 3601 decodes the column selection internal address signal and selects one of a plurality of first column selection signals Bi: H0 to Bi: H3 and Bj: H0 to Bj: H3. Activate. Thereby, the first column gate 3602-Bi:
0, 3602-Bj: One of the gates turns on, and the bit line
One of Bi: BL0 to Bi: BL3 and Bj: BL0 to Bj: BL3 is connected to main bit line MBL0. At the same time, the first column gate 3602-Bi:
1, 3602-Bj: One of the gates turns “on” and the bit line
One of Bi: BL4 to Bi: BL7 and Bj: BL4 to Bj: BL7 is connected to main bit line MBL1.

The second column selection decoder 3603 decodes the column selection internal address signal and selects and activates one of the plurality of second column selection signals D0 and D1. As a result, one of the second column gates 3604 is turned on.
Then, one of the main bit lines MBL0 and MBL1 is connected to the data line DL.

As described above, similarly to "type A", one of the plurality of bit lines is alternatively connected to one of the main bit lines, and one of the plurality of main bit lines is connected to one of the data lines. Alternatively connected.

(Read Circuit Unit) FIG. 39 is a block diagram showing a schematic configuration of the read circuit unit 3209.

As shown in FIG. 39, the read circuit unit 3209
Is a sense circuit 3801 and an equalize pulse generation circuit 3802
It is composed of

The sense circuit 3801 enlarges the potential amplitude of the data line DL, which is the output of the column decoder 3206, determines the data read from the memory cell, and outputs it as an output SAOUT.

The equalizing pulse generating circuit 3802 generates an equalizing pulse signal based on the pulse start signal EQLSTART.
Output EQL. The equalizing pulse signal EQL is input to the sense circuit 3801.

The pulse start signal EQLSTART is generated by the control circuit section 3202. The control circuit unit 3202 generates a pulse start signal EQLSTART in response to switching of an address signal or the like.

(Sense Circuit) FIG. 40 shows a sense circuit 3801.
FIG. 2 is a block diagram showing a schematic configuration of the embodiment.

As shown in FIG. 40, the sense circuit 3801
It comprises an amplifier 3901, a load circuit 3902, a separation circuit 3903, and a reference potential generation circuit 3904.

In addition to the circuit shown in FIG. 40, in addition to the circuit shown in FIG.
An equalizing circuit for equalizing the potential of the sense line SA and the potential of the reference sense line RSA is provided, but is omitted in FIG. A specific example of this equalizing circuit will be described later.

(Amplifier) FIG. 41 is a circuit diagram showing the amplifier 3901.

The role of the amplifier 3901 is to amplify a small potential difference between the sense line SA and the reference sense line RSA, and to determine data read from the memory cell. Therefore, the amplifier 3901 includes a differential amplifier.

As the differential amplifier, besides the general differential amplifier shown in FIG. 41A, a two-stage type shown in FIG. 41B and a parallel type shown in FIG. 41C are known. I have.

(Load Circuit) FIG. 42 is a circuit diagram showing the load circuit 3902.

The load circuit 3902 serves as a load for the sense line SA and the data line DL, and is a resistance type shown in FIG. 42 (A), an active load type shown in FIG. 42 (B) and FIG. 42 (C). The diode type shown is known.

(Separation Circuit) FIG. 43 is a circuit diagram showing the separation circuit 3903.

The role of the separation circuit 3903 is to set the drain of the memory cell to an optimum potential for a read operation.

The read bias for the memory cell is
VG = 5V, VD = positive voltage, VS = VSUB = 0V, and VG = 10V and VD = 6V which are write biases
It has the same positive / negative relationship. For this reason, it has been found that when a high voltage is applied to the drain of the memory cell at the time of reading, a slight writing phenomenon occurs regardless of the reading operation. This is the so-called "soft light". In order to suppress this "soft write", the drain of the memory cell must be lowered during the read operation such that the memory cell does not operate as a pentode. For example, about 1V.

Therefore, the separation circuit 3903 controls the potential of the wiring group connected to the drain of the memory cell, such as the data line and the bit line, so as not to exceed a predetermined potential, for example, １1 V.

As the separation circuit 3903, a feedback type shown in FIG. 43A and a constant bias type shown in FIG. 43B are known.

The feedback type separation circuit includes a sense line
It comprises a constant bias transistor 4201 connected between SA and the data line DL, and a feedback inverter 4202 whose input is connected to the data line DL and whose output is connected to the gate of the constant bias transistor 4201.

In the feedback type separation circuit, when the potential of the data line DL becomes higher than a predetermined level, the output of the feedback inverter 4202 changes, so that the constant bias transistor 4201 is turned off. As a result, the potential of the data line DL is controlled so as not to exceed a predetermined level.

The constant bias type separation circuit also has a constant bias transistor 4203 connected between the sense line SA and the data line DL, similarly to the feedback type. The difference is that the bias voltage BIAS generated from the bias generation circuit 4204 is supplied to the gate of the constant bias transistor 4203.

When the potential of the data line DL is controlled so as not to exceed, for example, １1 V, the bias voltage BIAS is “BIAS
= DL voltage (= 1V) + constant bias transistor 4203
Threshold value (= Vth).

The current bias circuit 4204 can output a substantially constant voltage BIAS regardless of a change in the power supply voltage.

(Reference Potential Generating Circuit) FIG. 44 is a circuit diagram showing the reference potential generating circuit 3904.

The configuration of the reference potential generating circuit 3904 must be basically symmetric with the configuration of the main unit (input side).
The difference is that a reference current source 4301 is connected to the reference data line RDL as a current source for flowing a reference current.

Since the configuration on the reference side must be basically symmetrical with the configuration on the main body side, it is preferable that only the reference current source 4301 is different. Therefore, the reference side has a dummy capacitance 4302 that is the same as the parasitic capacitance and resistance on the main unit side.
Must be added.

(How to Balance Resistance and Capacitance) FIG.
3 is a layout diagram showing a circuit layout. FIG. In addition,
In FIG. 45, a “type B” column decoder is assumed.

As shown in FIG. 45, the read circuit section 3209
Is locally located at a portion of the chip 4501, for example, approximately at the center. On the other hand, the memory cell array 3203 is generally arranged globally over most of the chip 4501. Therefore, the distance between the actually selected memory cell and the sense circuit 3801 in the read circuit portion 3209 is very long.

In particular, in a nonvolatile semiconductor memory having a “type B” column decoder, the main bit line MBL becomes very long, and a huge wiring capacity is added thereto.

Further, a PN junction capacitance of the second column gate 3604 connected to the data line DL is added. Therefore, the parasitic capacitance on the main body side of the sense circuit 3801 is very large.

Since it is very important to balance the capacitance between the main body and the reference side, especially in the read operation, the capacitance of the dummy capacitance 4302 is very large, almost equal to the parasitic capacitance on the main body. It is necessary to

FIG. 46 is a circuit diagram showing a specific example of the sense circuit. In FIG. 46, a “type B” column decoder is assumed.

As shown in FIG. 46, a sense line SA is connected to the main body side (input side) of the amplifier 3901. A power supply is connected to the sense line SA via a load circuit 3902. The sense line SA is connected to a data line DL via a separation circuit 3903. The data line DL is connected to a main bit line MBL via a first column gate 3604. The main bit line MBL is connected to a bit line BL via a second column gate 3602, and the bit line BL is connected to a memory cell.

The reference sense line RSA is connected to the reference side of the amplifier 3901. A power supply is connected to the reference sense line RSA via a load circuit 3902. Further, the reference sense line RSA is connected to the reference data line R via the separation circuit 3903.
Connected to DL. A dummy capacitor 4302 and a reference current source 4301 are connected to the reference data line RDL. The amount of current flowing from the reference current source 4301 is about half of the amount of current that can flow through a normal on-cell (“1” cell).

When the selected memory cell is turned on ("1")
In this case, the amount of current flowing through the memory cell is larger than the amount of current flowing through the reference current source 4301. Therefore, the potential of the data line DL is lower than the potential of the reference data line RDL. The potential of the data line DL and the potential of the reference data line RDL are respectively set to the constant bias transistor 42 of the separation circuit 3903.
The signal is amplified through the signal line 03 and transmitted to the sense line SA and the reference sense line RSA. The potential difference between the sense line SA at the “LOW” level and the reference sense line RSA at the “HIGH” level is amplified by the amplifier 3901 and read as an output SAOUT (data “1”).

On the other hand, when the selected memory cell is an off cell (“0” cell), almost no current flows through this memory cell. Therefore, the potential of the data line DL becomes higher than the potential of the reference data line RDL. The potential of the data line DL and the potential of the reference data line RDL are the same as those at the time of “1” read, and the constant bias transistor 42
The signal is amplified through the signal line 03 and transmitted to the sense line SA and the reference sense line RSA. "HIGH" sense line SA
The level and the potential difference with the reference sense line RSA set to the “LOW” level are amplified by the amplifier 3901 and read as the output SAOUT (data “0”).

A concern with the sense circuit of the type shown in FIG. 46 is the balance between the capacitance on the main body side and the capacitance on the reference side. For example, if the capacity of the main body and the capacity of the reference side are unbalanced, the following situations (1) and (2) occur.

(1) The reading speed is determined by the larger capacity of the main unit and the reference side, and the improvement of the reading speed is hindered.

(2) When noise is applied, the potential on the main body side and the potential on the reference side fluctuate unbalanced. The unbalanced potential fluctuation affects the data detection of the sense circuit.

In order to solve such a situation, a dummy capacitor is provided on the reference side so that the reference side capacity is equal to the main body side capacity.

However, since the capacitance on the main body side is a combination of the wiring capacitance and the PN junction capacitance as described above, it is difficult to exactly match the capacitance of the dummy capacitance with the capacitance on the main body side.

The dummy capacitance is generally arranged in a read circuit section, for example, near a sense circuit, unlike the memory cell array. That is, the locations where the capacitors are arranged are different between the reference side and the main body side. Such a difference in location causes imbalanced noise application when local noise occurs, for example, noise is applied to the reference side, but no noise is applied to the main body side. obtain. If noise is imbalanced, the potential on the reference side and the potential on the main body fluctuate unbalanced, which affects the data detection of the sense circuit.

In order to solve these circumstances, it is conceivable that the dummy capacitor is constituted by the same group as a wiring group such as a bit line and a memory cell on the main body side. However, since a dummy bit line that does not function as a bit line or a dummy memory cell that does not function as a memory cell is formed in a memory cell array, the area disadvantage such as an increase in chip area increases. I will.

Further, this area disadvantage is a problem that naturally occurs even when the dummy capacitance is arranged near the sense circuit.

[0094]

As described above,
In the sense circuit, it is an important technique to accurately adjust the capacitance on the reference side to the capacitance on the main body side, for example, to improve the reading speed and the noise resistance.

However, the capacity on the reference side is replaced by the capacity on the main body side.
If it is attempted to match only the dummy capacitance, (1) it is difficult to exactly match the capacitance, (2) it is susceptible to noise because the location where the capacitance is arranged is different, and (3) there are disadvantages in area. There are circumstances.

The present invention has been made in view of the above circumstances, and a first object of the present invention is to make it possible to accurately match the input-side capacitance and the reference-side capacitance while suppressing an increase in area. Another object of the present invention is to provide a semiconductor integrated circuit device resistant to noise.

A second object of the present invention is to provide a semiconductor integrated circuit device capable of suppressing the influence of switching noise generated at the end of equalization and achieving high-speed operation.

A third object of the present invention is to provide a semiconductor integrated circuit device provided with a pulse generating circuit having a small dependence on an external power supply.

A fourth object of the present invention is to provide a semiconductor integrated circuit device having a delay circuit capable of setting a finer delay time.

[0100]

In order to achieve the first object, according to the present invention, a memory cell array in which first and second memory cells for storing information are arranged, and information of the first memory cell is stored. Amplifies the difference between the input-side potential and the reference-side potential of the first column tree including the wiring group to which the information is transmitted, and the second column tree including the wiring group to which the information of the second memory cell is transmitted. A sense circuit. And
When the first memory cell is selected, the first column tree is connected to the input side, and the second column tree is connected to the reference side. When the second memory cell is selected, the second column tree is connected to the input side. A column switching gate for coupling a two-column tree to the input side and coupling the first column tree to the reference side is further provided.

In the semiconductor integrated circuit device having the above configuration,
When the first memory cell is selected, the capacity of the second column tree is added as a reference-side capacity. Conversely, when the second memory cell is selected, the capacity of the first column tree is added as a reference-side capacity. Is done. Therefore, compared to the case where a dummy capacitor is provided, the input-side capacitance and the reference-side capacitance are
It is possible to adjust more accurately.

Further, since both the first and second column trees can be arranged as a main body in the memory cell array, it is possible to reduce the area disadvantage as compared with the case where a dummy capacitor is provided. is there.

Moreover, since the first and second column trees can be arranged close to each other, the noise resistance, particularly the resistance to noise generated locally, is enhanced as compared with the case where a dummy capacitor is provided. It is also possible.

In order to achieve the second object, according to the present invention, there is provided a memory cell array in which memory cells for storing information are arranged, a column tree including a wiring group to which information of the memory cells is transmitted, and A data line coupled to the column tree, a reference data line, a data line equalizing circuit for equalizing a potential of the data line and a potential of the reference data line in response to a first equalizing pulse signal; A first separation circuit having one end connected to the sense line and the other end connected to the data line, one end connected to the reference sense line, and the other end connected to the reference data line. A second separating circuit, a differential amplifier having the sense line as a first input and the reference sense line as a second input, and a potential of the sense line in response to a second equalizing pulse signal. ; And a sense line equalizing circuit for equalizing the potentials of the irradiation sense line. Then, after canceling the equalizing operation of the sense line equalizing circuit, the equalizing operation of the data line equalizing circuit is canceled.
It is characterized by being released.

In the semiconductor integrated circuit device having the above configuration,
The equalizing operation of the sense line equalizing circuit is canceled after canceling the equalizing operation of the data line equalizing circuit. That is, even when the potential of the data line is disturbed by the switching noise at the time of canceling the equalizing operation of the data line equalizing circuit, the sense line equalizing circuit continues the equalizing operation. For this reason, disturbance of the potential of the data line is less likely to be transmitted to the differential amplifier, and the differential amplifier can determine data with little influence of switching noise.

As described above, by suppressing the influence of the switching noise generated at the end of the equalization, the operation can be speeded up.

To achieve the third object, the present invention includes a control circuit for generating a pulse start signal and a delay circuit for defining a pulse length of the pulse signal. A pulse generation circuit for generating the pulse signal. Then, the delay circuit outputs the pulse start signal having a logic level including a first level and a second level lower than the first level to a third level different from the first level and the second level. A level shifter for level-shifting a signal having a logical level consisting of a level and a delay element for supplying the third level to a first power supply terminal and supplying the second level to a second power supply terminal; And a gate circuit for supplying the third level to a first power supply terminal and supplying the second level to a second power supply terminal, and delaying the output in response to the output of the delay stage. And an output stage for outputting a signal.

In the semiconductor integrated circuit device having the above configuration,
The power supply of the delay element included in the delay stage is the first level to the third level. Therefore, even if the first level-the second level fluctuates, the delay stage is hardly affected by the fluctuation. Here, when the first level-the second level is an external power supply, in the pulse generation circuit including the delay stage,
It is possible to reduce the dependence on the external power supply.

To achieve the fourth object, according to the present invention, a control circuit for generating a pulse start signal, a pulse length control circuit for generating a pulse length adjustment signal in accordance with pulse length setting information, A pulse generation circuit that defines a pulse length of the signal, includes a delay circuit capable of adjusting a pulse length according to the pulse length adjustment signal, and generates the pulse signal in response to the pulse start signal. I do. The delay circuit includes a first delay stage for delaying the pulse start signal, a second delay stage for delaying the pulse start signal, and an output of the first delay stage in response to the pulse length adjustment signal. , And a switching circuit that outputs one of the outputs of the second delay stage, and an output stage that outputs a delay signal in response to the output of the switching circuit.

In the semiconductor integrated circuit device having the above configuration,
A switching circuit that outputs one of the output of the first delay stage and the output of the second delay stage in response to the pulse length adjustment signal; By switching and outputting the outputs of different delay stages in this way, a circuit such as a transfer gate is unnecessary as compared with the conventional case where the delay time is adjusted depending on how many stages of the delay element are passed. Become. For this reason, unnecessary increase of the parasitic capacitance is suppressed, and a finer delay time can be set.

[0111]

Embodiments of the present invention will be described below with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

In the following embodiments, a non-volatile semiconductor memory is assumed as an example of the semiconductor memory device. However, for example, the shape of the memory cell or the configuration of the memory cell may be changed as appropriate in addition to those exemplified in the embodiment. It is possible.

Further, the present invention can be appropriately applied to a semiconductor memory device other than the nonvolatile semiconductor memory.

(First Embodiment) The basic idea of the first embodiment is that the main bit line (selected main bit line) connected to the memory cell selected for reading is
The next main bit line (unselected main bit line) is used as it is as a dummy capacitance for reference.
If a non-selected main bit line can be connected to the reference data line during the read operation, the capacitance on the reference data line side can be made substantially the same as the capacitance on the data line side.

Hereinafter, an example of a nonvolatile semiconductor memory based on this concept will be described as a first embodiment.

FIG. 1 is a circuit diagram showing a column decoder provided in the nonvolatile semiconductor memory according to the first embodiment of the present invention.

As shown in FIG. 1, in the column decoder according to the first embodiment, a first column tree including a wiring group to which information of one memory cell is transmitted, and information of another memory cell are transmitted. A second column tree including a wiring group and a column switching gate 0101 are included.

The first column tree of the present example includes a first intermediate data line as a group of wires for transmitting information of one memory cell.
IDL01, main bit line MBL-01 (in this example, MBL0-01, MBL1
-01 is shown), and the bit line BL (Bi: BL0, Bi:
BL1, Bi: BL4, Bi: BL5, Bj: BL0, Bj: BL1, Bj: BL4, Bj: BL
5 shown). Memory cells (not shown) are connected to these bit lines BL. In FIG. 1, reference numeral "B
"i" and "Bj" each represent a block.

The second column tree is a group of wires through which information of another memory cell is transmitted.
IDL23, main bit line MBL-23 (in this example, MBL0-23, MBL1
-23), and a bit line BL (Bi: BL2, Bi:
BL3, Bi: BL6, Bi: BL7, Bj: BL2, Bj: BL3, Bj: BL6, Bj: BL
7 is shown). Memory cells (not shown) are connected to these bit lines BL.

When a memory cell in the first column tree is read and selected, the column switching gate 0101 is turned on.
In response to the column switching signal SW01, the first column tree is coupled to the data line DL, and the second column tree is coupled to the reference data line RDL.

When a memory cell in the second column tree is read and selected, the second column switching signal SW23
, The second column tree is coupled to the data line DL, and the first column tree is coupled to the reference data line RDL.

Data line DL is coupled to the input side of a differential amplifier in the sense circuit, and reference data line RDL is coupled to its reference side.

In such a device, of the first and second column trees, the column tree containing the memory cell selected and read is connected to the data line DL, and the other unselected column tree is connected to the reference data line. Combined with RDL. First,
Since the configuration of the second column tree is the same,
The capacity of these first and second column trees is almost equal. Therefore, at the time of reading, the capacitance added to the reference data line RDL can be made substantially equal to the capacitance of the data line DL.

Subsequently, the column decoder shown in FIG.
This will be described in more detail.

The column selection internal address signal is supplied to the first column selection decoder 0102, the second column selection decoder 0104,
And a column switching selection decoder 0106.

The first column selection decoder 0102 decodes the column selection internal address signal and selects one of the plurality of first column selection signals Bi: H0 to Bi: H3 and Bj: H0 to Bj: H3. Activate. Thereby, the first column gate 0103-Bi:
0, 0103-Bj: One of the gates turns “on” and the bit line
One of Bi: BL0 to Bi: BL3 and Bj: BL0 to Bj: BL3 is connected to main bit line MBL0-01 or MBL0-23. At the same time, one of the first column gates 0103-Bi: 1 and 0103-Bj: 1 is turned on, and the bit lines Bi: BL4 to Bi: BL7, Bj: BL4 to Bj: BL7.
Is connected to the main bit line MBL1-01 or MBL1-23.

The second column selection decoder 0104 decodes the column selection internal address signal and selects and activates one of the plurality of second column selection signals D0 and D1. As a result, two gates of the second column gate 0105 are simultaneously turned on, one of the main bit lines MBL0-01 and MBL1-01 is connected to the first intermediate data line IDL01, and at the same time, the main bit lines MBL0-23 , One of MBL1-23 is the second intermediate data line IDL23
Connected to.

The column switching selection decoder 0106 decodes the column selection internal address signal and selects one of the first column switching signals SW01 and SW23.

As for the switching signals SW01 and SW23 of this example, when a memory cell in the first column tree is selected, the switching signal SW01 becomes “HIGH” and the switching signal SW23 becomes “LOW”. As a result, the first intermediate data line IDL01 becomes the data line DL.
And the second intermediate data line IDL23 is connected to the reference data line RDL.

When a memory cell in the second column tree is selected, on the other hand, the switching signal SW01 becomes “LOW”,
The switching signal SW23 becomes “HIGH”. Thereby, the second
The intermediate data line IDL23 is connected to the data line DL, and the first intermediate data line IDL01 is connected to the reference data line RDL.

As described above, the switching signals SW01 and SW23 are switched between each other depending on whether a memory cell in the first column tree is selected or a memory cell in the second column tree. Therefore, the column switching selection decoder
The column selection internal address signal input to the column selection internal address signal input to the first column selection decoder 0102 is linked to each other. An example of this link is shown in Table 1.

[0132]

[Table 1]

As shown in Table 1, the first column selection signal H
When O or H1 is selected (that is, when a memory cell in the first column tree is selected), the first column switching signal SW01 is set to "HIGH" and the second column switching signal SW23 is set to "LOW". . Thereby, the first intermediate data line IDL01 in the same first column tree is connected to the data line DL,
The second intermediate data line IDL23 in the unselected second column tree
Are automatically connected to the reference data line RDL.

When the first column selection signal H2 or H3 is selected (ie, when a memory cell in the second column tree is selected), the first column switching signal SW01 is set to "LOW" and the second column switching signal SW01 is set to "LOW". The switching signal SW23 is set to “HIGH”, and the second intermediate data line IDL23 in the same second column tree is switched.
Is automatically connected to the data line DL, and the first intermediate data line IDL01 in the unselected first column tree is automatically connected to the reference data line RDL.

According to the first embodiment, the first,
In the second column tree, the column tree including the memory cell selected and read is connected to the data line DL, and the unselected tree is connected to the reference data line RDL. Can be almost equal to the capacity. In particular, the first and second column trees respectively
If the wiring structure and the number of connected memory cells are almost the same, it is possible to accurately adjust the wiring capacitance and the junction capacitance.

Since the first and second column trees can be arranged in the same memory cell array, their positions can be close to each other. For this reason, noise resistance, particularly resistance to local noise, can be further enhanced.

Further, since the first and second column trees are both main bodies, there is a disadvantage in terms of area as compared with a case where a dummy capacitor is provided or a case where a dummy bit line or a dummy memory cell is provided. Few.

Note that, in the first embodiment, for simplicity,
Although the main bit line belonging to the first column tree and the main bit line belonging to the column tree in the second column tree are adjacent to each other, the invention is not limited to this. For example, it may be separated from every other main bit line or more.

(Second Embodiment) Prior to the description of the second embodiment, an equalizing operation will be described.

The equalizing operation is performed to eliminate the influence of the previous read data, and is an operation of short-circuiting the corresponding nodes on the main body side and the reference side.

FIG. 2A is a circuit diagram showing a sense circuit with an equalizing circuit, and FIGS. 2B and 2C are circuit diagrams showing examples of the equalizing circuit.

Specifically, as shown in FIG. 2, an equalizing circuit (sense line equalizing circuit, data line equalizing circuit) 0201 is provided in the sense circuit, and the sense line SA and the reference sense line are used by using these equalizing circuits 0201. The line RSA and the data line DL and the reference data line RDL are short-circuited. The equalizing operation is performed based on the equalizing pulse signal EQL. This signal EQL is generated in response to an address change or the like from the pulse generation circuit.

FIG. 3 is an operation waveform diagram showing an equalizing operation.

As shown in FIG. 3, upon receiving an address change (time t0), a row (word line WL) and a column (column selection signal lines Hi and Di) are selected. Thereafter, the equalizing pulse signal EQL becomes "HIGH" and the equalizing operation is started (time t1). After the equalizing is performed to some extent, the equalizing operation is released (time t2). Some time after the equalizing operation is canceled, the output SAOUT of the sense circuit is determined (time t3), and thereafter, data is output from the output circuit unit (time t4).

During the equalizing period (equalizing period), the signal EQL is set to “HIGH” as shown in FIG.
Is determined by the pulse length of the signal EQL.

As shown in FIG. 4B, if the pulse length becomes shorter than necessary, the previous data cannot be completely initialized, which causes a delay in the read operation.

On the other hand, as shown in FIG. 4C, when the equalizing pulse becomes longer than necessary, the time for outputting the output SAOUT is simply delayed.
This causes a delay in the read operation.

As described above, there is an optimum value for the pulse length of the signal EQL, and if the optimum value is shorter or longer than the optimum value, the read time becomes longer as shown in FIG. Therefore, in order to perform a high-speed read operation, it is understood that the optimum value of the pulse length is desired to be as short as possible.

However, with the circuit configuration shown in FIG. 2A, there is a limit in shortening the optimum value. About this, FIG.
This will be described with reference to FIG.

FIG. 6A is a circuit diagram showing the nonvolatile semiconductor memory according to the first embodiment, and FIG. 6B is a circuit diagram showing the potential change of the data line and the change of the main bit line in the circuit shown in FIG. It is a waveform diagram which shows the electric potential change of an end.

As shown in FIG. 6B, when the equalizing operation is started, the potential of the data lines (DL, RDL) becomes
Get to the same level quickly. On the other hand, the potentials at the ends of the main bit lines (End MBL, End RMBL) do not immediately match. This is because, as shown in FIG. 6A, since the distance from the node being equalized to the end of the main bit line is long, the effect of equalizing does not appear immediately. This is a delay caused by the CR of the main bit line, and is limited for structural reasons.

If the equalizing operation is canceled before the potentials at the ends of the main bit lines are brought to the same level, the actual equalization has not been completed, and the data may be inverted at that point. And the output of the sense circuit is delayed.

The second embodiment is intended to improve the situation that the read operation is delayed, and to provide a nonvolatile semiconductor memory capable of speeding up the read operation.

FIG. 7 is a circuit diagram showing a nonvolatile semiconductor memory according to the second embodiment of the present invention.

As shown in FIG. 7, the main feature of the second embodiment is that equalization for performing equalization for each main bit line is performed.
The main bit line equalizing circuit 0701 is provided.
This makes it possible to suppress a delay caused by the CR of the main bit line.

The position where main bit line equalize circuit 0701 is arranged may be at the end of a memory cell array including several blocks as shown in FIG.
As shown in (B), the distance may be approximately １ ／ from each end of the memory cell array.

Further, as shown in FIG. 8C, the distance may be approximately one-third from one end of the memory cell array and approximately two-thirds from the other end (end on the sense circuit side) of the memory cell array.
In principle, it is considered that the arrangement shown in FIG. 8C has the smallest CR delay. Because the sense circuit has a data line equalizing circuit and the main bit line MBL
Is also equalized from the data line equalizing circuit.
For this reason, in the arrangement shown in FIG. 8C, the distance from the main bit line equalizing circuit 0701 or the data line equalizing circuit to the part of the main bit line MBL farthest from the main bit line equalizing circuit 0701 is almost equal to the entire length of the main bit line MBL. 1/3, CR
Delay can be suppressed better.

As shown in FIG. 8D, the number of main bit line equalizing circuits 0701 is not limited to one, and a plurality of main bit line equalizing circuits may be provided. If possible, it is more effective to provide a plurality of main bit line equalizing circuits 0701 to suppress the CR delay.

Next, the main bit line equalizing circuit 0701
A specific circuit example will be described.

FIG. 9A is a circuit diagram showing one circuit example of the main bit line equalizing circuit 0701, and FIG. 9B is a circuit diagram showing another circuit example.

As shown in FIG. 9A, the main bit line equalizing circuit 0701 is, for example, a CMOS transfer gate, as shown in FIG. 9B, like the data line equalizing circuit and the sense line equalizing circuit. , NM
It is possible to configure only from the OS.

However, care must be taken in some cases. That is, when writing, the main bit line has a high voltage,
For example, since the bias is biased to about 6 V, the main bit line equalizing circuit 0701 cannot be constituted by ordinary transistors. Here, a normal transistor refers to a transistor that forms a data line equalizing circuit or a sense line equalizing circuit. That is, the main bit line equalizing circuit 0701 needs to be formed of a high-breakdown-voltage transistor that can withstand a bias during writing. FIG. 10A shows an example of a high-breakdown-voltage transistor, and FIG.
0 (B).

As shown in FIGS. 10A and 10B, a high-breakdown-voltage transistor is different from a normal transistor in, for example, the thickness TOX of a gate insulating film. For example, the thickness TOX of the gate insulating film in the high breakdown voltage type transistor is formed to be thicker than the thickness TOX of the gate insulating film in the normal transistor.

In the second embodiment, the equalize control signal MBLEQL may be a signal of the VCC-VSS level or a signal of the VH-VSS level which is internally boosted.

In the second embodiment, the main bit line equalizing circuit 0701 is controlled by the control signal MBLEQL. However, the main bit line equalizing circuit 0701 may be controlled by the control signal EQL for controlling the data line equalizing circuit and the sense line equalizing circuit. good.

(Third Embodiment) The number of bit lines per block is usually about 1000. For the device having such a large number of bit lines, consider the equalization for each main bit line described in the second embodiment.

Assuming that the number of bit lines is “about 1000” and the number of first column selection signals in one block is “4”, the number of main bit lines of the device according to the present invention is “about 50”.
0 (1000/2) ". That is, the number of main bit line pairs is" about 250 pairs ", and the number of main bit line equalizing circuits 0701 is" about 250 ".

In such a device, when the main bit line equalizing operation is performed, "about 250
The individual main bit line equalizing circuit 0701 is simultaneously activated, and there is a concern that the operating current at the time of the read operation increases.

The third embodiment is intended to improve the situation that the operating current at the time of the read operation is increased, and to reduce the power consumption.

FIG. 11 is a circuit diagram showing a nonvolatile semiconductor memory according to the third embodiment of the present invention.

As shown in FIG. 11, the main feature of the third embodiment is that the control signal MBLEQL is decoded by using a part of the internal address signal. Specifically, the control signal MBLEQL is divided into two systems of control signals MBLEQL0 and MBLEQL1, and the number of main bit line equalizing circuits activated at one time is reduced. This makes it possible to reduce the operating current at the time of reading.

Each of the control signals MBLEQL0 and MBLEQL1 may be generated, for example, by linking to the second column selection signal Di. That is, when the number of the second column selection signal Di is, for example, an even number, the control signal MBLEQL0 is set to “HIGH” and the control signal MBLEQL0 is set to “HIGH”.
BLEQL1 is set to “LOW”. In the case of an odd number, the control signal MBLEQL0 may be set to "LOW" and the control signal MBLEQL1 may be set to "HIGH". As a result, of the "about 250" equalizing circuits 0701, only a half "about 125" can be activated, and the operating current during the read operation can be reduced.

In the example shown in FIG. 11, the control signal MB
Although LEQL is divided into two systems, it may be divided into more systems, for example, four systems, eight systems, etc. By dividing into a large number in this manner, the number of equalizing circuits 0701 activated at one time during the read operation can be further reduced, and the operating current at the time of read can be further reduced.

(Fourth Embodiment) Prior to the description of the fourth embodiment, the operation at the end of the equalizing operation will be described.

FIG. 12A is a circuit diagram, FIG. 12B is an operation waveform diagram showing the operation of the circuit shown in FIG. 12A at the end of equalization, and FIG. 12C is a circuit diagram of the equalizer circuit. is there.

As shown in FIGS. 12A and 12B, for example, the potential of the data line DL and the potential of the reference data line RDL are slightly disturbed by the switching noise at the end of equalization. This potential disturbance is caused by, for example, a difference between the capacitance of the data line DL and the capacitance of the reference data line RDL. For example, as shown in FIG. 12C, the capacitance between the gate (G) and the source (S) of the transistor forming the equalizing circuit 0201,
The smaller of the capacitance between the gate (G) and the drain (D) is greatly affected by the switching noise.

This disturbance of the potential occurs instantaneously even if the capacitance on the data line DL and the capacitance on the reference data line RDL are balanced as in the first embodiment. Is difficult to prevent.

[0178] Such disturbance of the potential causes the data lines DL and RD.
If it appears on L, the effect is immediately
The differential amplifier 3901 reacts to this,
As a result, the output of the differential amplifier 3901 is inverted, and the sensing operation may be delayed. Therefore, in order to achieve high-speed operation, it is necessary to take measures to suppress the influence of switching noise generated at the end of equalization.

In the fourth embodiment, the effect of switching noise generated at the end of equalization is suppressed, and the operation speed is increased.

FIG. 13A is a circuit diagram showing a nonvolatile semiconductor memory according to the fourth embodiment of the present invention.
13B is an operation waveform diagram showing an operation of the circuit shown in FIG. 13A at the end of equalization.

Conventionally, the equalization between data lines and the equalization between sense lines are canceled at the same time, so that the switching noise at this time is transmitted to the differential amplifier as it is.

Therefore, in the fourth embodiment, two equalizing pulse signals EQL1 and EQL2 are generated, and the differential amplifier 3901
Equalization is canceled from the equalization circuit far from
In the embodiment, the equalization is canceled from the data line equalizing circuit. At this time, as described above, the potentials of the data lines DL and RDL are disturbed, and the data may be inverted. However, by not canceling the equalization of the sense lines SA and RSA, the inverted data is not transmitted to the differential amplifier 3901. And the data lines DL, RDL
When the influence of the noise disappears, the equalization of the sense lines SA and RSA is released. As a result, the differential amplifier 3901
Can quickly determine data without being affected by noise.

Although the fourth embodiment has been described based on a sense circuit often used for a nonvolatile semiconductor memory, the form of the sense circuit is not particularly limited. For example, FIG.
As shown in FIG. 19, this is also possible in a sense circuit without the separation circuit 3903.

Assuming that, for example, a two-stage type differential amplifier 3901 as shown in FIG. 14 is used, first, the data lines DL, RDL
De-equalize each other, and then use differential amplifier 3901
In this case, the equalization between the output lines OUT and ROUT may be canceled.

In general writing, there is a sense circuit having two or more equalizing circuits, and the equalizing operation of these equalizing circuits is canceled in order from the side farthest from the output SAOUT of the sense circuit. is there.

It is to be noted that the fourth embodiment is, for example, shown in FIG.
As shown in (A), the description has been given based on an example in which the present invention is also applied to a general semiconductor memory. The present invention is also applicable to the semiconductor memories described in the first to third embodiments in which the unselected column tree is switched and connected to the reference side of the differential amplifier.

(Fifth Embodiment) FIGS. 15A and 15B are diagrams showing concerns when equalizing each main bit line.

As shown in FIG. 15A, the main bit line equalizing circuit 0701 is arranged at a position far from the read circuit section 3209. This is because the main bit line equalizing circuit 0701 is arranged to face the readout circuit unit 3209 with a memory cell array interposed therebetween, for example. Therefore, the equalization of the main bit line equalizing circuit 0701 is canceled in synchronization with the data line equalizing circuit and the sense line equalizing circuit, for example, the same equalizing pulse signal.
When released using EQL, as shown in FIG.
There is a situation that the time t2 at which the equalization of the main bit line equalizing circuit 0701 is released is later than the time t1 at which the equalization of the data line equalizing circuit and the sense line equalizing circuit is released. This is because the signal line transmitting the equalizing pulse signal EQL becomes long, and a CR delay occurs in the signal EQL. For this reason, there is a concern that the effective equalizing time is extended and the reading operation is delayed.

FIG. 16A is a circuit diagram showing a nonvolatile semiconductor memory according to the fifth embodiment of the present invention.
FIG. 17B is an operation waveform diagram illustrating an operation of the circuit illustrated in FIG.

Therefore, in the fifth embodiment, FIG.
As shown in (A), in the pulse generation circuit 1601, a signal MBLEQL for controlling the main bit line equalization circuit 0701 is used.
Is separated from the signal EQL that controls the sense line equalizing circuit and the data line equalizing circuit. Further, as shown in FIG. 16B, the time t1 at which the signal MBLEQL transitions from "HIGH" to "LOW" is made earlier than the time t2 at which the signal EQL transitions from "HIGH" to "LOW". Accordingly, the time t3 at which the equalization of the main bit line equalizing circuit 0701 is released is substantially equal to the time at which the equalization of the data line equalizing circuit and the sense line equalizing circuit is released.
Or it can be faster. This makes it possible to make the effective equalizing time equal to the equalizing time of the data line equalizing circuit or the sense line equalizing circuit.

The fifth embodiment is similar to the fourth embodiment in that the equalizing operation of the equalizing circuit is sequentially canceled from the side farthest from the output SAOUT of the sense circuit. It is possible to eliminate the concerns of equalization every time.

(Sixth Embodiment) FIG. 17A is a circuit diagram showing a pulse generation circuit 3802, and FIG. 17B is an operation waveform diagram thereof.

First, a pulse start signal EQLSTART serving as a trigger for pulse generation is input to the delay circuit 1701. The pulse start signal EQLSTART is also input to the logic gate 1702 at the same time, where the equalization pulse signal EQL is generated by the logic of the delay signal B passed through the delay circuit 1701. In other words, the equalizing pulse length is determined by the delay circuit
It can be said that it is determined by the delay time DELAY of 1701.
Note that the illustrated logic gate unit 1702 is only a specific example.

FIG. 18A is a circuit diagram showing a specific circuit example of the delay circuit 1701, and FIG. 18B is a diagram showing its external power supply dependency.

The delay circuit 1701 shown in FIG.
This is the simplest delay circuit constituted by a C-system inverter (using an external power supply VCC as a power supply). As shown in FIG. 18B, the delay time of the delay circuit 1701 has a VCC dependency that when the VCC is high, the delay time is too short as compared with the proper VCC, and when the VCC is low, the delay time is too long as compared with the proper VCC. Very large. Therefore, in the pulse generation circuit 3802 having the delay circuit 1701, the following situation occurs.

Normally, in a non-volatile semiconductor memory, internal read signals (word line WL, column select signal Hi and column select signal Hi) are used not by the external power supply VCC but by the internal boosted potential VH or VREAD boosted inside the integrated circuit during the read operation. , Di, etc.)
Generate.

Referring to FIG. 19, the relationship between the internal signal of the core section and the equalizing pulse signal will be described.

As shown in FIG. 19, after the internal address signal changes, the internal signal of the core section rises with a decoder delay which is provided in the decoder. As described above, this delay is caused by the transistor using the internal boosted potential VH or VREAD (boost transistor). Since the internal boosted potentials VH and VREAD do not depend on VCC, the decoder delay time does not change even when VCC changes.

On the other hand, the conventional pulse generation circuit 3802
Is simply composed of a transistor that uses VCC as a power supply, so that the pulse length of the equalizing pulse signal EQL becomes too short when VCC is high and becomes too long when VCC is low. Therefore, there is a possibility that the access time may be delayed.

The sixth embodiment is intended to provide a pulse generating circuit which has a small dependence on the external power supply and is compatible with the decoder delay of the core.

FIG. 20A is a block diagram showing a pulse generating circuit according to the sixth embodiment of the present invention, and FIG.
FIG. 20A is a circuit diagram showing an example of the delay circuit shown in FIG. 20A, and FIG. 20C is a circuit diagram showing an example of the level converter shown in FIG. 20B.

As shown in FIG. 20A, the pulse generation circuit 2001 according to the sixth embodiment includes a pulse start signal EQLS
A delay circuit 2002 receiving the TART and a logic gate unit 2003 receiving the pulse start signal EQLSTART and the delay signal passed through the delay circuit 2002 and generating an equalize pulse signal EQL by the logic of these signals are provided.

As shown in FIG. 20B, the delay circuit 2002
Is input to the level converter 2004. The level converter 2004 uses the VCC of the pulse start signal EQLSTART.
This is a circuit for converting the logic level of −VSS to the logic level of VH−VSS. Here, the boosted internal power supply VH
May be the same as the power supply used in the decoder of the core unit. FIG. 20C shows a circuit example of the level converter 2004.
Shows a cross-coupled level converter.

The output of the level converter 2004 is input to the step-up system inverter 2005. Booster inverter 2005
Is composed of a transistor that is not used for a VCC power supply, that is, a high breakdown voltage transistor, and its power supply is VH. The last inverter 2006 is also a step-up inverter, but its power supply is VCC.

A characteristic of the delay circuit 2002 shown in FIG. 20B is that the power supply of the delay circuit 2002 is not the external power supply VCC, but the boosted internal power supply VH. This makes it possible to eliminate the dependency of the delay circuit 2002 on the external power supply.

The high withstand voltage type transistor constituting the boosting type inverter is manufactured by the same process as the high withstand voltage type transistor used in the decoder of the core, for example. Thus, the transistor forming the delay circuit 2002 and the transistor forming the decoder are mutually
The same effects are caused by process variations (channel length, threshold voltage, oxide film thickness, etc.) and temperature fluctuations. Therefore, as compared with the conventional delay circuit, the circuit is more resistant to process variations and temperature fluctuations.

The power supply of the final stage inverter 2006 is set to V
By using CC, it is possible to correspond to an equalizing circuit (consisting of VCC transistors) used in the sense circuit.

In the sixth embodiment, of the first and second column trees, the selected column tree is switched to the input side of the differential amplifier, and the unselected column tree is switched to the reference side of the differential amplifier. The present invention is not limited to the semiconductor memory described in the first to third embodiments of connection, but can be applied to, for example, a general semiconductor memory described in the section of the related art.

Further, the sixth embodiment is not limited to the delay circuit of the semiconductor memory, but can be applied to delay circuits of various semiconductor integrated circuit devices.

(Seventh Embodiment) Prior to the description of the seventh embodiment, an equalizing pulse trimming function will be described.

The function of trimming the equalizing pulse is as follows.
For example, it is a function of measuring the pulse length for each chip and adjusting it to an optimum value.

Normally, there are some differences between the result value of the simulator and the measured value, such as transistor characteristics. For this reason, the desired pulse length may not be obtained. If no action is taken on such a chip, the access of the chip will be slow and the yield will not increase. Therefore, the pulse length of the equalizing pulse in individual units such as between chips (may be between wafers or lots) can be adjusted after a chip is completed by a storage unit (programmable ROM such as an aluminum fuse). There is a need.

FIG. 21A is a circuit diagram showing a delay circuit having a trimming function, and FIG. 21B is an operation waveform diagram showing its operation.

As shown in FIG. 21A, a delay circuit 2101 having a trimming function includes an inverter chain 2102,
NO receiving signal via inverter chain 2102
An R gate 2103 and a transfer gate 2104 with a reset function for short-circuiting the middle of the inverter chain 2102 and another input of the NOR gate 2103 are provided. This delay circuit
The delay time DELAY of 2101 is determined by the logic of the control signals A and B.

For example, as shown in FIG. 21B, when the control signals A and B are both "HIGH", the delay time DELAY
Is determined by six inverter delays.

When the control signal A is "HIGH" and the control signal B is "LOW", the delay time DELAY is determined by four inverter delays, and both the control signals A and B are "LO".
In the case of "W", the delay time DELAY is determined by two inverter delays.

Therefore, by making these control signals A and B adjustable by the data in the storage section, the pulse length after the chip is completed can be adjusted. However, FIG.
The delay circuit shown in FIG. 1A has the following problem when trying to finely adjust the delay time.

That is, in the delay circuit 2101 shown in FIG. 21A, a transfer gate 2104 is inserted in the middle of an inverter chain (delay path). Therefore, the settable delay time includes a delay due to the parasitic capacitance C of the transfer gate 2104, and it is not possible to set a detailed delay time.

In the case where a finer delay time cannot be set, a failure such as an inability to adjust the pulse length will be made in consideration of further increasing the speed of the operation, that is, further shortening the pulse length of the equalizing pulse. is assumed.

The seventh embodiment is intended to solve the above-mentioned concerns and to provide a delay circuit with a trimming function capable of setting a finer delay time.

FIG. 22A is a circuit diagram showing a delay circuit having a trimming function according to a seventh embodiment of the present invention.
FIG. 22B is an operation waveform diagram showing the operation, and FIG.
(C) is a block diagram showing an example of generation of an adjustment signal.

As shown in FIG. 22A, delay circuit 2201
Is a plurality of (three in this example) delay elements 2202 which receive an input signal IN and have different delay times, respectively.
After receiving the output from 2202, the adjustment signals (three in this example) A,
A switching circuit 2203 for selecting one of the outputs of the delay element 2202 based on B and C is provided.

In this example, the power supply of the delay element 2202 and the switching circuit 2203 is VH. For this purpose, a level converter 2004 for converting the logic level of the input IN is provided. The power supply of the last inverter 2006 is at VH.

Next, the operation will be described.

The input signal IN of the delay circuit is input to a plurality (three in this example) of level converters 2004. Then, as shown in FIG. 22B, when the input signal IN becomes “HIGH”, the inverters in the respective delay elements 2202 start operating. The switching circuit 2203 receives the output from the delay element 2202 and validates the delay time of any one of the delay elements 2202 based on the adjustment signals A, B, and C.

In this example, a NOR gate is shown as one circuit example of the switching circuit 2203. In this case, by setting any of the control signals A, B, and C to "HIGH",
The delay time of the delay element 220 can be made effective. At this time, the logic levels of the adjustment signals A, B, and C are V
It becomes H-VSS level.

An example of generation of adjustment signals A, B and C is shown in FIG.
It is shown in (C).

As shown in FIG. 22C, the storage unit 2204 is provided with a programmable ROM, for example, a fuse or a nonvolatile memory cell. The ROM stores adjustment signals A, B, and C. The data to be set to “HIGH” is programmed. The storage unit 2204 is activated, for example, in response to an external signal.

The pulse length control circuit 2205 sets any of the adjustment signals A, B, and C to "HIGH" based on the data programmed in the storage unit 2204.

According to the delay circuit of the seventh embodiment, there is no transfer gate in the middle of the delay element 2202 (delay path). Therefore, the configurable delay times include:
The parasitic capacitance of the transfer gate is not included.

Also, as in this example, the switching circuit 2203 is
By using a simple logic gate such as a NOR gate, the switching circuit 2203 can be operated as a part of the delay element. And from the switching circuit 2203,
The transfer gate can be eliminated, and no extra parasitic capacitance is provided in the delay path.

As described above, according to the seventh embodiment, it is possible to obtain a delay circuit with a trimming function capable of setting a finer delay time.

(First Modification of Seventh Embodiment) FIG.
FIG. 15 is a circuit diagram illustrating a delay circuit with a trimming function according to a first modification of the seventh embodiment.

The difference between the delay circuit 2301 shown in FIG. 23 and the delay circuit 2201 shown in FIG. 22 is the input portion to which the input IN is input.

In other words, in the delay circuit 2201 shown in FIG. 22, the input signal IN is input to all of the level converters 2004 provided before the delay elements 2202, and the switching circuit provided after the delay elements 2202 is provided. Delay element 2202 enabled in circuit 2203
The output was selected and switched.

On the other hand, the delay circuit according to the first modification example
In 2301, a first switching circuit 2302 is provided in a stage preceding each level converter 2004. In the first switching circuit 2302, a delay element 2202 that is enabled based on the adjustment signals A, B, and C is provided.
Select in advance.

As an example of the first switching circuit 2302, an AND gate is shown. In this case, by setting any of the adjustment signals A, B, and C to “HIGH”, any of the delay elements 2202 is enabled, and the delay time is set. According to the first modification, the inverter delay of the boosting system that determines the delay time is hardly affected by the trimming.

(Second Modification of Seventh Embodiment) FIG. 24
(A) is a circuit diagram showing a delay element according to a second modification of the seventh embodiment.

Although the delay element 2202 shown in FIGS. 22 and 23 is an inverter, it is not limited to an inverter. For example, as shown in FIG.
It may be configured to include a capacitance C and a resistance R. At this time,
Each of the capacitor C and the resistor R is formed of an element that can withstand the boosted potential VH.

At this time, as an example of the resistor R that can withstand the boosted potential VH, there is a diffusion resistor shown in FIG. This diffusion resistance is obtained by lowering the impurity concentration of the N-type layer and the P-type impurity concentration around the N-type layer, respectively, as compared with the VCC-type diffusion resistance shown in FIG.
The breakdown voltage of the PN junction is increased.

As an example of the capacitance C that can withstand the boosted potential VH, there is a MOS capacitor shown in FIG. This MOS capacitor has a voltage V V shown in FIG.
For example, it is formed using a high withstand voltage type MOS transistor in which the thickness TOX of the gate insulating film is larger than that of the CC type MOS capacitor.

(Third Modification of Seventh Embodiment) In the seventh embodiment, the boosted potential VH is used as the power supply for the inverter. However, the idea of the seventh embodiment is not limited to the boosted potential alone. Since it is not, it is shown in a more general form.

FIG. 25 is a generalized version of delay circuit 2201 shown in FIG.

As shown in FIG. 25, the input IN is a delay element 22
The output of the delay element 2202 is switched by a switching circuit 2203 and output as an output OUT.

Since the power supply is VCC, the level converter 2004 is omitted.

(Fourth Modification of Seventh Embodiment) FIG.
This is a generalization of the delay circuit 2301 shown in FIG.

As shown in FIG. 26, the input IN is input to the first switching circuit 2302, where the input IN is switched and input to the delay element 2202.

Since the power supply is VCC, the level converter 2004 is omitted.

The seventh embodiment and the first to seventh embodiments are described.
The delay circuit according to the fourth modification is configured such that, of the first and second column trees, a selected column tree is switched to an input side of a differential amplifier and an unselected column tree is switched to a reference side of a differential amplifier. The present invention is not limited to the semiconductor memory described in the first to third embodiments, but may be applied to, for example, a general semiconductor memory described in the section of the related art.

The seventh embodiment and the first to seventh embodiments are described.
The delay circuit according to the fourth modified example is not limited to a semiconductor memory, and is used as a delay circuit of a semiconductor integrated circuit device.
Can be applied.

(Eighth Embodiment) Next, an example of a write system circuit suitable for an apparatus having first and second column trees will be described.
This will be described as an eighth embodiment.

FIG. 27 is a circuit diagram showing a nonvolatile semiconductor memory according to the eighth embodiment of the present invention.

As shown in FIG. 27, in the case of the device having the first and second column trees, the write gate 2701 is connected to the write power supply VDDP and the first and second intermediate data lines IDL01 and IDL23.
It is good to arrange between. Write gate 2701 in this example
Receive a common write control signal PRG.

The write control signal PRG is provided in two systems, for example, corresponding to the first intermediate data line IDL01 and the second intermediate data line IDL23, and these intermediate data lines IDL01, IDL23 are provided.
Of the write gates 23, the write gate on the write-selected side may be turned on, and the write gate on the non-selected side may be turned off. However, in this case, the number of write control signal lines increases.

On the other hand, in this example, the number of the write control signal lines is reduced by sharing the write control signal.

When the write control signal is shared in this manner, the intermediate data line on the non-selection side or the main bit line is charged and the power seems to be lost. It's not much of a problem.

(Modification of Eighth Embodiment) Next, another example of a writing system suitable for a device having first and second column trees will be described as a modification of the eighth embodiment.

For example, as described in the first embodiment, the column switching signals SW01 and SW23 are the first column selection signals H
Is linked to. Therefore, for example, in the device shown in FIG. 1, when the bit line Bi: BL0 is selected, the column switching signal SW01 is set to “H” together with the first column selection signal Bi: H0.
IGH ”. Then, the following situation occurs.

The bias transistor of the separation circuit 3903 is arranged ahead of the column switching gate 0101. This bias transistor is usually made of a VCC type transistor. Therefore, if the column switching gate 0101 is turned “on” during the write operation, a bias applied to, for example, the first and second intermediate data lines IDL01 and IDL23 is applied to the bias transistor during the write operation. Therefore, the bias transistor is destroyed.

To eliminate such a situation, for example, as shown in FIG. 28A, "OFF" is applied between the column switching gate 0101 and the bias transistor at the time of writing.
What is necessary is just to arrange | position the switch 2801 which performs. However, in this case, extra capacitance and resistance are added to the data line at the time of reading.

Therefore, as shown in FIG. 28B, in this modification, the column switch selection decoder 0106
At the time of a write operation, control is performed such that the column switching gate 0101 is forcibly turned off. Thus, at the time of the write operation, the first and second intermediate data lines IDL01 and IDL23 and the bias transistor of the separation circuit 3903 are separated from each other by the column switching gate 0101. Therefore, it is possible to suppress the destruction of the bias transistor of the sense circuit without disposing an extra switch, for example, with the configuration shown in FIG.

(Ninth Embodiment) In the above embodiment, the description has been made with respect to the "type B" column decoder. However, as shown in FIG. 29, the present invention can be applied to the "type A" column decoder as it is. It is.

(Tenth Embodiment) In the case of the type B column decoder, since the main bit line is elongated, equalization for each main bit line is effective as shown in FIG.

However, in the case of the type A column decoder, the main bit line is not so long, but rather the first and second intermediate data lines IDL01 and IDL23 are longer.
Therefore, as shown in FIG. 30, the first intermediate data line IDL01
It is preferable to provide an intermediate data line equalizing circuit 3001 for equalizing the potential of the second intermediate data line IDL23 with the potential of the second intermediate data line IDL23.

The intermediate data line equalizing circuit 3001 is the same as that shown in FIG.
1A, the end of the memory cell array including several blocks may be used, or as shown in FIG.
It may be near.

Further, as shown in FIG. 32C, the distance may be approximately 1/3 from one end of the memory cell array and approximately 2/3 from the other end (end on the sense circuit side) of the memory cell array.

As shown in FIG. 32D, the number of intermediate data line equalizing circuits 3001 is not limited to one, and a plurality of intermediate data line equalizing circuits may be provided.

The intermediate data equalizing circuit 3001 has a fourth
Of course, control as described in the fifth embodiment is also possible.

Further, both the intermediate data equalizing circuit 3001 and the main bit line equalizing circuit 0701 can be used together.

As described above, the present invention has been described with reference to the first to tenth embodiments. However, the present invention is not limited to each of these embodiments, and its implementation does not depart from the gist of the invention. Various modifications can be made within the range.

Further, each of the above-described embodiments may be practiced alone or in combination as appropriate.

Further, the above embodiments include inventions of various stages, and it is possible to extract inventions of various stages by appropriately combining a plurality of constituent elements disclosed in each embodiment. is there.

[0273]

As described above, according to the present invention, it is possible to more accurately match the capacitance on the main body side and the capacitance on the reference side while suppressing an increase in area, and to provide a semiconductor integrated circuit resistant to noise. A circuit device can be provided.

Further, it is possible to provide a semiconductor integrated circuit device in which the influence of switching noise generated at the end of equalization is suppressed and the operation speed can be increased.

Further, it is possible to provide a semiconductor integrated circuit device provided with a pulse generating circuit having a small dependence on an external power supply.

Further, it is possible to provide a semiconductor integrated circuit device having a delay circuit capable of setting a finer delay time.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a nonvolatile semiconductor memory according to a first embodiment of the present invention.

FIG. 2A is a circuit diagram showing a nonvolatile semiconductor memory with an equalizing circuit, and FIG. 2B is a circuit diagram showing an equalizing circuit.

FIG. 3 is a waveform chart showing an equalizing operation.

FIGS. 4A to 4C are waveform diagrams showing an equalizing operation for each different pulse length.

FIG. 5 is a diagram showing a relationship between a pulse length and a read time.

6A is a circuit diagram, and FIG. 6B is a circuit diagram in FIG.
7 is a waveform chart showing a potential change of the data line shown in FIG.

FIG. 7 is a circuit diagram showing a nonvolatile semiconductor memory according to a second embodiment of the present invention.

FIGS. 8A to 8D are layout diagrams each showing an example of the layout of a main bit line equalizing circuit; FIGS.

FIGS. 9A and 9B are circuit diagrams illustrating circuit examples of a main bit line equalizing circuit, respectively.

10A is a cross-sectional view illustrating a high-breakdown-voltage transistor, and FIG. 10B is a cross-sectional view illustrating a normal transistor.

FIG. 11 is a circuit diagram showing a nonvolatile semiconductor memory according to a third embodiment of the present invention.

FIG. 12 is an operation waveform diagram showing an operation at the end of equalization.

FIG. 13 is a circuit diagram showing a nonvolatile semiconductor memory according to a fourth embodiment of the present invention.

FIG. 14 is a circuit diagram showing another example of the sense circuit.

FIG. 15 is a diagram showing concerns when performing equalization for each main bit line.

FIG. 16 is a circuit diagram showing a nonvolatile semiconductor memory according to a fifth embodiment of the present invention.

FIG. 17 is a circuit diagram showing a pulse generation circuit.

FIG. 18 is a circuit diagram showing a delay circuit.

FIG. 19 is a diagram illustrating a relationship between an internal core signal and an equalize signal;

FIG. 20 is a circuit diagram showing a delay circuit according to a sixth embodiment of the present invention.

FIG. 21 is a circuit diagram showing a delay circuit having a trimming function.

FIG. 22 is a circuit diagram showing a delay circuit having a trimming function according to a seventh embodiment of the present invention.

FIG. 23 is a circuit diagram showing a delay circuit having a trimming function according to a first modification of the seventh embodiment of the present invention.

FIG. 24 is a circuit diagram showing a delay circuit having a trimming function according to a second modification of the seventh embodiment of the present invention.

FIG. 25 is a circuit diagram showing a delay circuit having a trimming function according to a third modification of the seventh embodiment of the present invention.

FIG. 26 is a circuit diagram showing a delay circuit having a trimming function according to a fourth modification of the seventh embodiment of the present invention.

FIG. 27 is a circuit diagram showing a nonvolatile semiconductor memory according to an eighth embodiment of the present invention.

FIG. 28 is a circuit diagram showing a nonvolatile semiconductor memory according to a modification of the eighth embodiment of the present invention.

FIG. 29 is a circuit diagram showing a nonvolatile semiconductor memory according to a ninth embodiment of the present invention.

FIG. 30 is a circuit diagram showing a nonvolatile semiconductor memory according to a tenth embodiment of the present invention.

FIGS. 31A to 31D are layout diagrams each showing an example of the layout of an intermediate data line equalizing circuit; FIGS.

FIG. 32 is a cross-sectional view showing a memory cell;

FIG. 33 is a block diagram showing an internal system of the nonvolatile semiconductor memory;

FIG. 34 is a circuit diagram showing a memory cell array.

FIG. 35 is a circuit diagram showing a first example of a column configuration.

FIG. 36 is a diagram showing a block configuration of a memory cell array.

FIG. 37 is a circuit diagram showing a second example of the column configuration.

FIG. 38 is a diagram showing a block configuration of a memory cell array.

FIG. 39 is a diagram illustrating a reading circuit portion.

FIG. 40 is a diagram showing a sense circuit.

FIG. 41 is a circuit diagram showing an amplifier.

FIG. 42 is a circuit diagram showing a load circuit.

FIG. 43 is a circuit diagram showing a separation circuit.

FIG. 44 is a circuit diagram showing a reference potential generation circuit.

FIG. 45 is an arrangement diagram showing an arrangement relationship between a sense circuit and a block;

FIG. 46 is a circuit diagram showing a sense circuit.

[Explanation of symbols]

 0101: column switching gate, 0102: first column selection decoder, 0103: first column gate, 0104: second column selection decoder, 0105: second column gate, 0106: column switching selection decoder, 0701: main bit line equalizing circuit 2001, a level converter, 2002, a booster inverter, 2003, a booster inverter, 2201, a level converter, 2202, an inverter, 2203, a switching circuit, 2301, a switching circuit,

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/788 29/792 F-term (Reference) 5B025 AA03 AD07 AE05 AE08 5F001 AA01 AB08 AB09 AC02 AC06 AD44 AE02 AE03 AE08 AE30 AF24 AG40 5F083 EP02 EP23 ER02 ER05 ER09 ER14 ER19 ER22 ER30 GA09 GA11 LA03 LA04 LA09 LA10 LA12 ZA07 5F101 BA01 BB05 BB17 BC02 BC11 BD27 BE02 BE05 BE07 BE14 BF08 BH21

Claims (28)

[Claims] 1. A memory cell array in which first and second memory cells storing information are arranged; a first column tree including a wiring group to which information of the first memory cell is transmitted; and the second memory cell A second column tree including a group of wires to which the information is transmitted, a sense circuit for amplifying the difference between the potential on the input side and the potential on the reference side, and the first column when the first memory cell is selected. Coupling a tree to the input side and coupling the second column tree to the reference side; when the second memory cell is selected, coupling the second column tree to the input side and the first column A semiconductor integrated circuit device, comprising: a column switching gate for coupling a tree to the reference side. 2. A memory cell array in which first and second memory cells storing information are arranged; a first bit line to which information of the first memory cell is transmitted;
A first column tree including a first main bit line to which information of the first bit line is transmitted, and a first intermediate data line to which information of the first main bit line is transmitted; and information of the second memory cell. Is transmitted to the second bit line,
A second column tree including a second main bit line to which information of the second bit line is transmitted, and a second intermediate data line to which information of the second main bit line is transmitted; the first bit line; In response to a first column selection signal that can select one of the second bit lines, the first bit line is connected to the first main bit line, and the second bit line is connected to the second main bit line. A first column gate to be coupled to the first main bit line; and a second column selection signal capable of simultaneously selecting both the first main bit line and the second main bit line. A second column gate for coupling the second main bit line to the second intermediate data line, an intermediate data line, a data line, a reference data line, a potential of the data line, and the reference data, A sense circuit for amplifying a difference between the first intermediate data line and the second intermediate data line in response to a first column switching signal, and coupling the second intermediate data line to the reference data line. A column switching gate for coupling the second intermediate data line to the data line and coupling the first intermediate data line to the reference data line in response to a second column switching signal. Semiconductor integrated circuit device. 3. The method according to claim 1, wherein the first column switching signal and the second column switching signal are generated with reference to at least a part of an address signal used for generating the first column selection signal. The semiconductor integrated circuit device according to claim 2. 4. In response to a first equalizing pulse signal,
4. The semiconductor integrated circuit according to claim 2, further comprising a main bit line equalizing circuit for equalizing a potential of said first main bit line and a potential of said second main bit line. Circuit device. 5. The main bit line equalizing circuit,
5. The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device is arranged at an end of the memory cell array. 6. The main bit line equalizing circuit,
5. The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device is arranged in the middle of the memory cell array. 7. The method according to claim 4, wherein the first equalizing pulse signal is generated with reference to at least a part of an address signal used for generating the second column selection signal. 9. The semiconductor integrated circuit device according to claim 1. 8. In response to a second equalizing pulse signal,
A data line equalizing circuit for equalizing a potential of the data line and a potential of the reference data line, wherein the equalizing operation of the main bit line equalizing circuit is performed before the equalizing operation of the data line equalizing circuit is released. 8. The semiconductor integrated circuit device according to claim 4, wherein the operation is canceled. 9. In response to a third equalizing pulse signal,
4. The semiconductor integrated circuit according to claim 2, further comprising an intermediate data line equalizing circuit for equalizing a potential of said first intermediate data line and a potential of said second intermediate data line. Circuit device. 10. An equalizing operation of the intermediate data line equalizing circuit, further comprising a data line equalizing circuit for equalizing a potential of the data line and a potential of the reference data line in response to a second equalizing pulse signal. Is
10. The semiconductor integrated circuit device according to claim 9, wherein the equalizing operation of the data line equalizing circuit is canceled before the equalizing operation is canceled. 11. The sense circuit, comprising: a sense line, a reference sense line, a first separation circuit having one end connected to the sense line and the other end connected to the data line, and one end connected to the reference sense line. A second separation circuit connected to the reference data line and the other end thereof connected to the reference data line;
A differential amplifier to be input, and a sense line equalizing circuit for equalizing a potential of the sense line and a potential of the reference sense line in response to a fourth equalizing pulse signal; 11. The semiconductor integrated circuit device according to claim 8, wherein after the equalizing operation of said data line equalizing circuit is canceled, said data line equalizing circuit is canceled. 12. The sense circuit, wherein the data line has a first input and the reference data line has a second input.
A first differential amplifier to be input, and a first differential amplifier to which one of complementary outputs of the first differential amplifier is transmitted
A second differential amplifier having an output line as a first input and a second output line to which the other of the complementary outputs is transmitted as a second input; and a second differential amplifier in response to a fifth equalizing pulse signal. An output line equalizing circuit for equalizing a potential and a potential of the second output line, wherein the equalizing operation of the output line equalizing circuit is canceled after the equalizing operation of the data line equalizing circuit is canceled. 11. The semiconductor integrated circuit device according to claim 8, wherein: 13. A control circuit for generating a pulse start signal, and a delay circuit for defining a pulse length of the first equalize pulse signal, wherein the first equalize pulse signal is generated in response to the pulse start signal. An equalizing pulse signal generation circuit, wherein the delay circuit includes a pulse start signal having a logic level including a first level and a second level lower than the first level.
A level shifter for level-shifting a signal having a logical level consisting of a third level different from the first level and the second level; and a third power supply terminal, wherein the third power supply terminal is supplied with the third level. A delay stage for delaying an output of the level shifter, the delay stage including a delay element to which the second level is supplied; a third power supply terminal receiving the third level, and a second power supply terminal receiving the second level 8. The semiconductor integrated circuit device according to claim 4, further comprising: an output stage including a gate circuit and outputting a delay signal in response to an output of the delay stage. 9. 14. A control circuit for generating a pulse start signal, and a delay circuit for defining a pulse length of the second equalize pulse signal, wherein the second equalize pulse signal is generated in response to the pulse start signal. An equalizing pulse signal generation circuit, wherein the delay circuit includes a pulse start signal having a logic level including a first level and a second level lower than the first level.
A level shifter for level-shifting a signal having a logical level consisting of a third level different from the first level and the second level; and a third power supply terminal, wherein the third power supply terminal is supplied with the third level. A delay stage for delaying an output of the level shifter, the delay stage including a delay element to which the second level is supplied; a third power supply terminal receiving the third level, and a second power supply terminal receiving the second level 8. An output stage including a gate circuit, the output stage outputting a delay signal in response to an output of the delay stage.
0. The semiconductor integrated circuit device according to any one of the above. 15. A control circuit for generating a pulse start signal, and a delay circuit for defining a pulse length of the third equalize pulse signal, wherein the third equalize pulse signal is generated in response to the pulse start signal. An equalizing pulse signal generation circuit, wherein the delay circuit includes a pulse start signal having a logic level including a first level and a second level lower than the first level.
A level shifter for level-shifting a signal having a logical level consisting of a third level different from the first level and the second level; and a third power supply terminal, wherein the third power supply terminal is supplied with the third level. A delay stage for delaying an output of the level shifter, the delay stage including a delay element to which the second level is supplied; a third power supply terminal receiving the third level, and a second power supply terminal receiving the second level 10. The semiconductor integrated circuit device according to claim 9, further comprising: an output stage that includes a gate circuit and outputs a delay signal in response to an output of the delay stage. 16. A control circuit for generating a pulse start signal, and a delay circuit for defining a pulse length of the fourth equalize pulse signal, wherein the fourth equalize pulse signal is generated in response to the pulse start signal. An equalizing pulse signal generation circuit, wherein the delay circuit includes a pulse start signal having a logic level including a first level and a second level lower than the first level.
A level shifter for level-shifting a signal having a logical level consisting of a third level different from the first level and the second level; and a third power supply terminal, wherein the third power supply terminal is supplied with the third level. A delay stage for delaying an output of the level shifter, the delay stage including a delay element to which the second level is supplied; a third power supply terminal receiving the third level, and a second power supply terminal receiving the second level 12. The semiconductor integrated circuit device according to claim 11, further comprising an output stage including a gate circuit and outputting a delay signal in response to an output of said delay stage. 17. A control circuit for generating a pulse start signal, and a delay circuit for defining a pulse length of the fifth equalize pulse signal, wherein the fifth equalize pulse signal is generated in response to the pulse start signal. An equalizing pulse signal generation circuit, wherein the delay circuit includes a pulse start signal having a logic level including a first level and a second level lower than the first level.
A level shifter for level-shifting a signal having a logical level consisting of a third level different from the first level and the second level; and a third power supply terminal, wherein the third power supply terminal is supplied with the third level. A delay stage for delaying an output of the level shifter, the delay stage including a delay element to which the second level is supplied; a third power supply terminal receiving the third level, and a second power supply terminal receiving the second level 13. The semiconductor integrated circuit device according to claim 12, further comprising: an output stage that includes a gate circuit and outputs a delay signal in response to an output of the delay stage. 18. The delay circuit is capable of adjusting a pulse length in accordance with a pulse length adjustment signal. The delay circuit has a logic comprising a first level and a second level lower than the first level. The pulse start signal having a level
A first level shifter for level-shifting a signal having a logical level consisting of a third level different from the first level and the second level; and a third power supply terminal, the third level being supplied to a second power supply. A first delay element whose terminal is supplied with the second level,
A first delay stage for delaying an output of the first level shifter; a pulse start signal having a logic level including a first level and a second level lower than the first level;
A second level shifter for level-converting a signal having a logical level consisting of a third level different from the first level and the second level; and a third power supply terminal for supplying the third level, A second delay element whose terminal is supplied with the second level,
A second delay stage to be output by the second level shifter, an output of the first delay stage, and an output of the second delay stage as inputs, respectively, and in response to the pulse length adjustment signal,
A switching circuit that outputs one of the output of the first delay stage and the output of the second delay stage; a third power supply terminal supplied with the third level, and a second power supply terminal supplied with the second level 17. The semiconductor integrated circuit according to claim 12, further comprising: an output stage that includes a gate circuit that outputs a delay signal in response to an output of the switching circuit. 18. apparatus. 19. The delay circuit is capable of adjusting a pulse length in accordance with a pulse length adjustment signal. The delay circuit receives the pulse start signal as an input, and responds to the pulse length adjustment signal. A first switching circuit that outputs one of the first output signal and the second output signal; and the first output signal having a logic level including a first level and a second level lower than the first level. A first level-shifted signal having a logic level consisting of a third level different from the first level and the second level.
A level shifter, and a first delay element supplied with the third level to a first power supply terminal and supplied with the second level to a second power supply terminal,
A first delay stage for delaying an output of the first level shifter; a pulse start signal having a logic level including a first level and a second level lower than the first level;
A second level shifter for level-converting a signal having a logical level consisting of a third level different from the first level and the second level; and a third power supply terminal for supplying the third level, A second delay element whose terminal is supplied with the second level,
A second delay stage to be output by the second level shifter, an output of the first delay stage, and an output of the second delay stage as inputs, respectively, and in response to the pulse length adjustment signal,
A second switching circuit that outputs one of the output of the first delay stage and the output of the second delay stage; the third power supply terminal receiving the third level; and the second power supply terminal receiving the second level. 17. The semiconductor device according to claim 12, further comprising: a gate circuit to which the switching circuit is supplied, and an output stage that outputs a delay signal in response to an output of the switching circuit. 18. Integrated circuit device. 20. The semiconductor device according to claim 2, further comprising: a write gate that couples the first intermediate data line and the second intermediate data line to a write power supply in response to a write control signal. The semiconductor integrated circuit device according to claim 18. 21. The semiconductor integrated circuit device according to claim 19, wherein each of the first column switching signal and the second column switching signal is not selected according to the write control signal. 22. A memory cell array in which memory cells storing information are arranged; a column tree including a group of wires to which information of the memory cells is transmitted; a data line coupled to the column tree; and a reference data line. A data line equalizing circuit for equalizing the potential of the data line and the potential of the reference data line in response to a first equalizing pulse signal, a sense line, a reference sense line, and one end connected to the sense line A first separation circuit having the other end connected to the data line; a second separation circuit having one end connected to the reference sense line and the other end connected to the reference data line; And the reference sense line is connected to the second
A differential amplifier to be input, and a sense line equalizing circuit for equalizing a potential of the sense line and a potential of the reference sense line in response to a second equalizing pulse signal, wherein the equalizing of the sense line equalizing circuit is performed. The operation of the semiconductor integrated circuit device is canceled after the equalizing operation of the data line equalizing circuit is canceled. 23. A memory cell array in which memory cells for storing information are arranged; a column tree including a group of wires to which the information of the memory cells is transmitted; a data line coupled to the column tree; and a reference data line. A data line equalizing circuit for equalizing a potential of the data line and a potential of the reference data line in response to a first equalizing pulse signal; a first input for the data line, and a second input for the reference data line.
A first differential amplifier to be input, and a first differential amplifier to which one of complementary outputs of the first differential amplifier is transmitted
A second differential amplifier having an output line as a first input and a second output line to which the other of the complementary outputs is transmitted as a second input; and a second differential amplifier in response to a second equalizing pulse signal. An output line equalizing circuit for equalizing a potential and a potential of the second output line, wherein the equalizing operation of the output line equalizing circuit is canceled after the equalizing operation of the data line equalizing circuit is canceled. A semiconductor integrated circuit device characterized by the above-mentioned. 24. A control circuit for generating a pulse start signal, comprising: a delay circuit for defining a pulse length of the pulse signal; and a pulse generating circuit for generating the pulse signal in response to the pulse start signal. The delay circuit includes a pulse start signal having a logic level including a first level and a second level lower than the first level.
A level shifter for level-shifting a signal having a logical level consisting of a third level different from the first level and the second level; and a third power supply terminal, wherein the third power supply terminal is supplied with the third level. A delay stage for delaying an output of the level shifter, the delay stage including a delay element to which the second level is supplied; a third power supply terminal receiving the third level, and a second power supply terminal receiving the second level An output stage that includes a gate circuit and outputs a delay signal in response to an output of the delay stage. 25. A control circuit for generating a pulse start signal; a pulse length control circuit for generating a pulse length adjustment signal in accordance with pulse length setting information; A pulse generator that generates the pulse signal in response to the pulse start signal, the delay circuit comprising: a first level; The pulse start signal having a logical level consisting of a second level lower than the first level;
A first level shifter for level-shifting a signal having a logical level consisting of a third level different from the first level and the second level; and a third power supply terminal, the third level being supplied to a second power supply. A first delay element whose terminal is supplied with the second level,
A first delay stage for delaying an output of the first level shifter; a pulse start signal having a logic level including a first level and a second level lower than the first level;
A second level shifter for level-converting a signal having a logical level consisting of a third level different from the first level and the second level; and a third power supply terminal for supplying the third level, A second delay element whose terminal is supplied with the second level,
A second delay stage to be output by the second level shifter, an output of the first delay stage, and an output of the second delay stage as inputs, respectively, and in response to the pulse length adjustment signal,
A switching circuit that outputs one of the output of the first delay stage and the output of the second delay stage; a third power supply terminal supplied with the third level, and a second power supply terminal supplied with the second level And an output stage for outputting a delay signal in response to an output of the switching circuit. 26. A control circuit for generating a pulse start signal; a pulse length control circuit for generating a pulse length adjustment signal in accordance with pulse length setting information; A pulse generation circuit that generates a pulse signal in response to the pulse start signal, the pulse circuit including: a delay circuit that can adjust a pulse length according to a signal; A first switching circuit that outputs one of a first output signal and a second output signal in response to the pulse length adjustment signal; a first level; and a second level lower than the first level. The first output signal having a logic level consisting of a third level different from the first level and a signal having a logic level consisting of the second level The first shift 1
A level shifter, and a first delay element supplied with the third level to a first power supply terminal and supplied with the second level to a second power supply terminal,
A first delay stage for delaying an output of the first level shifter; a pulse start signal having a logic level including a first level and a second level lower than the first level;
A second level shifter for level-converting a signal having a logical level consisting of a third level different from the first level and the second level; and a third power supply terminal for supplying the third level, A second delay element whose terminal is supplied with the second level,
A second delay stage to be output by the second level shifter, an output of the first delay stage, and an output of the second delay stage as inputs, respectively, and in response to the pulse length adjustment signal,
A second switching circuit that outputs one of the output of the first delay stage and the output of the second delay stage; the third power supply terminal receiving the third level; and the second power supply terminal receiving the second level. And an output stage for outputting a delay signal in response to an output of the switching circuit. 27. A control circuit for generating a pulse start signal; a pulse length control circuit for generating a pulse length adjustment signal in accordance with pulse length setting information; A pulse generator that generates the pulse signal in response to the pulse start signal, the delay circuit delays the pulse start signal. A first delay stage for delaying the pulse start signal, a second delay stage for delaying the pulse start signal, and an output of the first delay stage or an output of the second delay stage in response to the pulse length adjustment signal. A semiconductor integrated circuit device, comprising: a switching circuit that outputs a signal; and an output stage that outputs a delay signal in response to an output of the switching circuit. 28. A control circuit for generating a pulse start signal; a pulse length control circuit for generating a pulse length adjustment signal in accordance with pulse length setting information; A pulse generation circuit that generates a pulse signal in response to the pulse start signal, the pulse circuit including: a delay circuit that can adjust a pulse length according to a signal; A first switching circuit that outputs one of a first output signal and a second output signal in response to the pulse length adjustment signal; a first delay stage that delays the first output signal; (2) a second delay stage for delaying an output signal, an output of the first delay stage, and an output of the second delay stage as inputs, respectively, in response to the pulse length adjustment signal;
A second switching circuit that outputs one of the output of the first delay stage and the output of the second delay stage; and an output stage that outputs a delay signal in response to the output of the switching circuit. A semiconductor integrated circuit device comprising: