JP2002204153A - Level converter and semiconductor device therewith - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level converter which can improve operation minimum (circuit performance) of level conversion operation. SOLUTION: Level shifters 60, 61, 62 of three stages (or more) are connected in cascade. An input signal IN is converted to a VH-to-Vss voltage by a level shifter 60 of a first stage, and a VH-to-Vss voltage output from the level shifter 60 of a first stage is converted to a VH-to-VL1 voltage by the level shifter 61 of a second stage. Thereafter, a VH-to-VL1 voltage output from the level shifter 61 of a second stage is converted to a VH-to-VL2 voltage by the level shifter 62 of a third stage. Each potential has a relation of VH>Vss>VL1>VL 2, and VH is constant. Since the withstand voltage between level shifters is set within a fixed range and conversion potential difference between levels shifters can be made small, performance of conversion operation can be raised.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level converter used for a decoder circuit in a semiconductor memory device, for example, and a semiconductor device provided with the level converter.

[0002]

2. Description of the Related Art Conventionally, this type of level converter is constructed, for example, as shown in FIGS.

The level converter shown in FIG. 20 comprises a high level shifter 11 having an address selection line as an input IN, and a low level shifter 12 having a high level conversion line which is a complementary output of the high level shifter 11 as an input. The output OUT of the level shifter 12 is supplied to a level conversion selection line.

The high-level shifter 11 is supplied with VH level and Vss level voltages as power supplies, and when the Vcc level is input to the input terminal in, the output terminals out and / are output.
VH level and low level are connected to the high side of a high level conversion line connected to out (“/” prefixed to the sign means an inverted signal or a terminal to which the inverted signal is input or output). Vss (0 V) is output to the low) side.

On the other hand, voltages of VH level and VL level are supplied to the low level shifter 12 as a power source, and complementary signals HH and HH of a high level conversion line are supplied from input terminals in and / in.
/ HH, and outputs VH or VL level from output terminals out and / out. This low level shifter 12 is set to 0
Necessary when generating a potential of a level lower than V.

FIG. 21 shows an example of the relationship between the VH level or VL level voltage for supplying power to the circuit shown in FIG. 20 and the operation of the semiconductor memory device. At the time of writing to a semiconductor memory device, VH is set to 9 V, VH
0 V is given as L. In erasing, VH is set to 1
-8 V is applied as V and VL, and 5 V and 0 V are applied as VH and VL at the time of reading. At the time of the verify program, 7V is applied as VH and 0V is applied as VL. At the time of verify erase, 2V is applied as VH and -2V is applied as VL.

FIG. 22 shows an example of a circuit configuration of the high-level shifter 11 in the level converter shown in FIG. This high-level shifter 11 is an N-channel type MO
It comprises S transistors Q1, Q2, P-channel MOS transistors Q3, Q4 and an inverter 13. The input signal from the input terminal in is supplied to the gate of the MOS transistor Q1 from the input terminal in, and the input signal from the input terminal in is supplied to the gate of the MOS transistor Q2.
Is supplied after being inverted. These MOS transistors Q
1 and Q2 have their sources connected to the ground point Vss and their gates connected cross-coupled between each drain and the power supply VH.
A pair of MOS transistors Q3 and Q4 are provided.
The common drain connection point of the MOS transistors Q1 and Q3 and the common drain connection point of the MOS transistors Q2 and Q4 are output terminals / out and out, respectively.
Becomes

The high-level shifter 11 receives an input signal of 0 V at its input terminal in as shown in FIG.
The output terminal out is at 0 V, and the output terminal / out is at the VH level. On the other hand, when a Vcc level input signal is applied to the input terminal in, the output terminal out is at the VH level and the output terminal
out becomes 0V.

FIG. 24 shows a P-channel MOS transistor Q in the high-level shifter 11 shown in FIG.
3 and Q4 are shown in FIG. 25, and FIG.
2 shows an element configuration of N-channel MOS transistors Q1 and Q2 in the high-level shifter 11 shown in FIG. As shown in the figure, a P-channel MOS transistor includes an N-type well region 1 formed in a P-type semiconductor substrate 14.
5 are formed. In addition, the N-channel type MOS transistor has a P-type MOS transistor formed in the N-type well region 15.
It is formed in a well region.

FIG. 26 shows a circuit configuration example of the low-level shifter 12 in the level converter shown in FIG. This low level shifter 12 is an N-channel type MO
It comprises S transistors Q5, Q6 and P-channel MOS transistors Q7, Q8. An input signal is supplied from the input terminal in to the gate of the MOS transistor Q7, and the input terminal / in is supplied to the gate of the MOS transistor Q8.
Supplies complementary input signals. The sources of the MOS transistors Q7 and Q8 are connected to a power supply VH, and a pair of MOS transistors Q5 and Q6 are provided between each drain and the power supply VL. Then, the common drain connection point of the MOS transistors Q8 and Q6 becomes the output terminal out.

As shown in FIG. 27, when a 0 V input signal is applied to the input terminal in and a VH level input signal is applied to the input terminal / in, the output terminal out of the low level shifter 12 goes to the VL level. On the other hand, when a VH level signal is applied to the input terminal in and an input signal of 0 V is applied to the input terminal / in, the output terminal out is provided.
Goes to the VH level.

Next, the level converter having the above configuration will be considered in more detail with reference to FIGS. When a Vcc level signal is received as the input signal IN, the VH level is supplied to the high level conversion line HH connected to the output terminal of the high level shifter 11, and the level conversion selection which is an output signal line as a level converter is provided. The VH level is also output to the line. On the other hand, when a signal of 0 V is received as the input signal IN, 0 V is supplied to the high-level conversion line HH,
The VL level is output to the level conversion selection line.

What should be noted here is the withstand voltage of the transistors constituting the level converter.

In the case of a nonvolatile semiconductor memory device, for example, at the time of writing, 9 V is applied to the control gate of the memory cell.
, VH = 9V and VL = 0V, but this voltage is also a constraint from the withstand voltage of the transistor.

For example, when a high level (= 9 V) is output from the output terminal out by the high level shifter 11 (see FIG. 22), a potential difference of 9 V between the source and drain of the transistors Q2 and Q3 and between the gate and drain. Is given.

Therefore, in order to apply -8 V to the control gate of the memory cell during the erasing operation, the breakdown voltage (Ma
VL = −8 V VH = maximum 1 (= 10−9) V from the condition of (× 9 V) (the transistor constituting the low-level shifter 12 has a withstand voltage of 9 V, and the high-level shifter 11 has a withstand voltage of 9 V). Is not a problem.)

At this time, if the configuration of “high-level shifter + low-level shifter (= level converter having a two-stage configuration)” is adopted as in the above-described example, the following problem occurs.

[Problem 1] Since the power supply (VH level) is 1 V for the high-level shifter 11 (it is necessary to match the high level of the low-level shifter 12), for example, an N-channel MOS transistor and a P-channel M
If the threshold voltage of the OS transistor is about 1 V, it is difficult to operate at a sufficient speed (FIG. 22).
When the output terminal out is set to a high level by the transistor Q4, the potential difference between the gate and the source cannot be turned on at 1 V).

[Problem 2] Even if the high-level shifter 11
, Even if a potential is generated from the low level shifter 12
Between 0 and 1 V (high level shifter 11
Threshold voltage), VH = 1V,
Under the condition of VL = −8 V, the size of the transistors Q7 and Q8 must be considerably increased, and the speed is remarkably reduced due to the charging of the parasitic capacitance.

That is, the memory cell is written at a high speed.
The potential required for erasing is determined, and the withstand voltage condition of each transistor is also determined. If an attempt is made to generate the potential required by the memory cell under such conditions, the conventional level converter may operate under a voltage condition close to the operation minimum, resulting in a problem that the performance is extremely deteriorated. there were.

[0021]

As described above, the conventional level converter needs to be operated under a voltage condition close to an operation minimum in order to generate a required potential under specific conditions. There is a problem that circuit performance is reduced.

In a conventional semiconductor device having a level converter, the potential required for, for example, writing / erasing a memory cell at high speed is determined, and the transistor withstand voltage condition is also determined. In order to generate a required potential, it is necessary to operate under a voltage condition close to the operation minimum, and there is a problem that the circuit performance also deteriorates.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a level converter capable of improving an operation minimum (circuit performance) of a level conversion operation.

Another object of the present invention is to provide a semiconductor device having a level converter capable of improving an operation minimum (circuit performance) of a level conversion operation while observing conditions of a potential required by a memory cell and a withstand voltage of a transistor. It is to provide a device.

[0025]

A level converter according to the present invention comprises: a first level shifter for converting a logic level comprising a first level and a second level into a logic level comprising a third level and a fourth level; A second level shifter that receives an output of the first level shifter and converts a logic level including a third level and a fourth level into a logic level including a fifth level and a sixth level; and receives an output of the second level shifter. , A third level shifter for level-converting a logic level consisting of a fifth level and a sixth level to a logic level consisting of a seventh level and an eighth level;
Level and the fourth level have the same potential, the third level and the fifth level have the same potential, the fifth level and the seventh level have the same potential, and the third level has the first potential. The fourth level is higher than the sixth level, and the sixth level is higher than the eighth level.

Further, the level converter of the present invention comprises a first level shifter for converting a logic level consisting of a first level and a second level into a logic level consisting of a third level and a fourth level, and the first level shifter. And a second level shifter for converting a logic level consisting of the third level and the fourth level into a logic level consisting of the fifth level and the sixth level, and receiving the output of the second level shifter and receiving the fifth level. And a third level shifter for converting a logic level consisting of the sixth level to a logic level consisting of the seventh level and the eighth level, wherein the second level and the fourth level have the same potential, The third level and the fifth level have the same potential, the sixth level and the eighth level have the same potential, the third level is higher than the first level, and the third level is higher than the first level. Level is higher than the fourth level, the seventh level is characterized by higher than the fifth level.

Further, the level converter according to the present invention comprises: a first level shifter for converting a logic level comprising a first level and a second level into a logic level comprising a third level and a fourth level; and the first level shifter. And a second level shifter for converting a logic level consisting of the third level and the fourth level into a logic level consisting of the fifth level and the sixth level, and receiving the output of the second level shifter and receiving the fifth level. And a third level shifter for level-converting a logic level comprising the sixth level to a logic level comprising the seventh level and the eighth level; and a logic level comprising the seventh level and the eighth level receiving the output of the third level shifter. And a fourth level shifter for converting the second level and the fourth level into a logic level comprising a ninth level and a tenth level. The third level and the fifth level are the same potential, the sixth level and the eighth level are the same potential, the seventh level and the ninth level are the same potential, The third level is higher than the first level, the sixth level is higher than the fourth level, the fifth level is higher than the seventh level, and the eighth level is higher than the tenth level. And

Furthermore, the level converter of the present invention converts the input logic level to a different logic level and outputs the converted output signal from the first to n-th (n is a positive integer of 3 or more) level shifters. The input terminals are sequentially connected in cascade,
Adjacent level shifters operate at a power supply voltage in which one of the voltage levels is substantially equal to each other, sequentially change the potential difference between logic levels input to the first-stage level shifter, and output from the last-stage level shifter.

A level converter according to the present invention is a level converter for converting a logic level of a signal output from an address converter to an address signal line in a semiconductor memory device, and comprises a first level and a second level. A first level shifter for converting a level into a logical level including a third level and a fourth level, and receiving the output of the first level shifter, converting the logical level including the third level and the fourth level into a fifth level and a fifth level. A second level shifter for converting the level to a logic level consisting of six levels, and receiving the output of the second level shifter, changing the logic level consisting of the fifth level and the sixth level to a logic level consisting of the seventh level and the eighth level And a third level shifter for converting the first level shifter to the first level during the erase operation of the semiconductor memory device. And the sixth level of the second level shifter is a second negative potential lower than the first negative potential, and the eighth level of the third level shifter is a third negative potential lower than the second negative potential. It is characterized by having.

A level converter according to the present invention is a level converter for converting a logical level of a signal output from an address conversion unit to an address signal line in a semiconductor memory device, wherein the level converter converts the logic level between the first level and the second level. A first level shifter for level-converting a logical level into a logical level comprising a third level and a fourth level, and receiving the output of the first level shifter and converting the logical level comprising the third level and the fourth level to a fifth level And a second level shifter for converting the level to a logic level comprising a sixth level, and receiving the output of the second level shifter, and converting the logic level comprising the fifth level and the sixth level into a logic level comprising the seventh level and the eighth level Receiving the output of the third level shifter and converting the logic level consisting of the seventh level and the eighth level to the third level shifter. A fourth level shifter for converting a level to a logic level comprising a first level and a tenth level, wherein the third level output from the first level shifter is a first positive potential and a fourth level during an erasing operation of the semiconductor memory device. Is a first negative potential, and a sixth level output from the second level shifter is a second negative potential lower than the first negative potential.
A seventh level outputted from the third level shifter is a third positive potential lower than the first positive potential;
The tenth level output from the fourth level shifter is a fourth negative potential lower than the third negative potential.

The semiconductor device of the present invention has a first level converter composed of three or more level shifters connected in cascade, and a second level converter composed of one level shifter or two level shifters connected in cascade. And a switch circuit for selecting and outputting one of an output signal of the first level converter and an output signal of the second level converter according to a control signal corresponding to an operation mode. And

According to the above configuration, the breakdown voltage between the level shifters can be kept within a certain range, and the conversion potential difference between the level shifters can be reduced, so that the performance of the conversion operation can be improved.

Therefore, the operation minimum (circuit performance) of the level conversion operation can be improved. Further, the operation minimum (circuit performance) of the level conversion operation can be improved while observing the conditions of the potential required by the memory cell and the withstand voltage of the transistor.

[0034]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIGS. 1 to 15 illustrate a first level converter and a semiconductor device having the level converter of the present invention, respectively. ) Is shown as an example.

FIG. 1 is a system block diagram of the EEPROM. This EEPROM comprises a memory cell array 21, a row decoder 22, a column decoder 23, a source / well decoder 24, an input circuit 25, a control circuit 26, a booster circuit 27, a write circuit 28, a read circuit 29, an output circuit 30, and the like. I have. The memory cell array 21 has m rows of memory cells (X coordinate).
They are arranged in n columns (Y coordinates). Row decoder 2
2 outputs a data storage position signal on the word line coordinates (X coordinate) to the memory cell array 21. The column decoder 23 outputs a data storage position signal on the coordinate (Y coordinate) of the bit line in the cell to the memory cell array. The source / well decoder 24 outputs the potential of the P-type well region and the potential of the source region commonly connected to the memory cell array 21. The input circuit 25 receives an address control signal. The control circuit 26
Decodes the signal output from the input circuit 25 and decodes each circuit unit (row decoder 22, column decoder 23,
A control signal is output to the source / well decoder 24 and the booster 27). The booster circuit 27 generates a high voltage used for writing, erasing, and reading with respect to the memory cells in the memory cell array 21. The output of the booster circuit 27 is supplied to the row decoder 22 and the column decoder 23. You. The write circuit 28 performs a write operation and a verify operation, and receives write data. The read circuit 29 determines the state of the memory cell at the time of reading. The output circuit 30 outputs the read data.

FIG. 2 shows a configuration example of the memory cell array 21 in the system block diagram shown in FIG. 1, and is a schematic configuration diagram of the memory cell array 21 in the flash memory. Flash memory here means
This is to erase a plurality of memory cells simultaneously. In the same P-type well region, a plurality of memory cells MC of an erase unit are arranged in m rows and n columns (m and n are natural numbers of 2 or more; in FIG. 2, m = 3, n = 4 is shown) (mx).
n memory cell array).

The control gates of the memory cells MC belonging to the same row are connected in common to the word lines WL0 to WL2 corresponding to the rows, and the drains of the memory cells MC belonging to the same column have the bit lines BL0 to BL3 in the cell corresponding to the columns. Are connected in common. The P-type well regions in which the memory cells MC are formed are commonly connected in a matrix, and the source regions of the memory cells MC are also commonly connected in a m × n memory cell array belonging to the same P-type well region by a source line SL. ing.

When writing and reading, a specific 1
When selecting a bit, the word line WLm (m = 0,
1, 2) are generated by the row decoder 22 and the bit lines B
Ln (n = 0, 1, 2, 3) is alternatively selected by the column decoder 23, so that the selected memory cell M
C performs the above-described write and read operations.

The erasing operation is performed in the same p-type well region as m
Xn memory cell arrays are collectively performed.

FIG. 3 shows a structure called a stack gate type as an example of a storage element (memory cell MC) which is a basic unit of the EEPROM. For example, an N-type well region 32 is formed in a P-type semiconductor substrate 31, and a P-type well region 33 is formed in a surface region of the N-type well region 32. Stack gate type memory cell MC
Are source and drain regions (N-type impurity diffusion layers) 34 and 35 formed at predetermined intervals in the surface region of the P-type well region 33, and these source and drain regions 3
A gate insulating film 36, a floating gate (polysilicon layer) 37, an insulating film 38 above the floating gate, and a control gate (polysilicon layer) 39 are sequentially stacked on the P well region 33 between the gate insulating layers 4 and 35. .

Next, the operation of this type of memory cell MC will be briefly described.

For writing (data storage) into the memory cell MC, for example, 5 V is applied to the drain region 35, and the P-type well region 33 (also to the P-type semiconductor substrate 31 and the N-type well region 32) and the source region 34 0V (ground potential) is applied,
Further, a voltage of about 9 V is applied to the control gate 39. Since the floating gate 37 is not connected to an external power supply,
The potential of the gate insulating film 36 and the insulating film on the floating gate 38
Control gate 3 by the coupling ratio formed by
9, is uniquely determined from the potentials of the source region 34, the drain region 35, and the P-type well region 33.

By setting each electrode at such a potential, hot electrons having high energy generated by a strong lateral (source-drain) electric field are generated, and a part of the hot electrons is generated by the barrier of the gate insulating film 36. , And is injected into the floating gate 37. As a result, writing is performed on the memory cell MC.

Further, erasing (erasing data) of the memory cell MC is performed by writing (floating gate 37) as described above.
This means extracting electrons from the floating gate 37 of the memory cell MC in a state where electrons are stored in the memory cell MC. The following method may be used.

N-type well region 32 and P-type well region 33
For example, 9 V is applied to the source region 34, and −8 V is applied to the control gate 39. As a result, the P-type well region 3
3, and a considerably strong electric field (10 MV / cm or more) is applied to the gate insulating film 36 between the source region 34 and the floating gate 37. Under such a strong electric field, a quantum-mechanical Fowler-Noldheim current (tunnel current) flows through the gate insulating film 36, and by utilizing the result, the floating gate 37 and the P-type well region 33 and the source region 34 are used. The electrons are drawn out, and the memory cell MC is erased.

On the other hand, the reading (data reading) of the memory cell MC is performed with respect to the memory cell MC written or erased by the above-described method with respect to each floating gate 37.
Is performed using the fact that the potentials of More specifically, when an N-type channel is to be formed directly below the floating gate 37 of the memory cell MC, the memory cell MC in the written state stores electrons in the floating gate 37, and thus the memory cell MC in the written state Forming a channel in MC requires that the floating gate 37 be more positively charged than forming a channel in an erased (ie, no stored) memory cell MC. At this time, as described above, the potential of the floating gate 37 is controlled by the coupling ratio formed by the gate insulating film 36 and the insulating film 38 above the floating gate, the control gate 39, the source region 34, the drain region 35, and the P-type well. Since the potential is uniquely determined from the potential of the region 33, the potential of the control gate 39 is set to “the memory cell in the written state does not form a channel, but the memory cell in the erased state A channel is formed ”(this potential is set to VREAD). Therefore, while giving an appropriate potential difference between the drain and the source, the control gate 39
By setting the potential of VREAD to VREAD, nothing occurs because the memory cell in the written state does not have a channel formed, but the memory cell in the erased state has a channel formed, as in a normal N-channel MOS transistor. -A current determined by the potential difference between the sources and the potential of the floating gate 37 flows. Then, when the memory cell receives the potential VREAD at the control gate 39, the read circuit 29 determines whether or not a current flows, thereby reading the information of the memory cell.

FIG. 4 is a circuit configuration example of the row decoder 22 in the system block diagram shown in FIG. The row decoder 22 includes an address converter 42, a level converter 44, and a buffer 46.

The row selection internal address signal ADD generated by the input circuit 25 and the control circuit 26 is supplied to an address conversion unit 42 via an internal address signal line 41, and the address conversion unit 42 selects one of the row selection internal address signals ADD. Address selection line 43 is activated. Since the word line WLn uses a potential other than the power supply voltage (Vcc) in any of the read, write, and erase operations, the signal on the address select line 41 is input to the level converter 44 for performing the voltage conversion. Then, a voltage is applied from the buffer 46 for shaping the waveform of the signal on the level conversion selection line 45, which is the output, to the word line WLn.

FIG. 5 shows another example of the circuit configuration of the row decoder circuit 22. The row decoder 22 includes address conversion units 42a and 42b, level converters 44a and 4
4b, an address converter 47 and a buffer 46.

Part ADD of the internal address signal for row selection generated by input circuit 25 and control circuit unit 26
a and ADDb are respectively converted into separate address conversion units 42a,
42b to supply each address selection line 43a,
Activate 43b. These address selection lines 43a,
The signals on 43b are individually converted to level converters 44a and 44b.
And the level-converted selection signal subjected to level conversion is input to the address conversion unit 47. Then, the output of the address conversion unit 47 is input to the buffer 46, and the voltage is transferred to the word line WLn.

The essential difference between the row decoder 22 shown in FIGS. 4 and 5 is that, in the case of the circuit shown in FIG. 4, an address selection line is selected (at once) from an internal address signal. In the case of the circuit shown in FIG. 5, the internal address signal is divided into two systems, and the respective address selection lines 43a, 43a,
43b, the level conversion selection line is again received by the address conversion unit 47 after being passed through the level converters 44a and 44b, and is selected as an alternative. FIG. 5 shows an example in which the system is divided into two systems for the sake of simplicity, but the present invention is not limited to this example, and three or more systems may be used.

FIG. 6 shows an example of the configuration of the address converters 42, 42a and 42b in the circuits shown in FIGS. These address converters 42, 42a, 4
2b is an internal address signal ADD (ADDa, ADD
An AND gate 50 that takes the logical product of b) is used, and the address selection line 43 is selected as an alternative.

FIG. 7 shows an example of the configuration of the address converter 47 in the circuit shown in FIG. The address conversion unit 47 is composed of an AND gate 51 which takes the logical product of the level conversion selection signal, and the output of which is output from the word line WLn.
Is the selected address. The power supply of the AND gate 51 receives the level-converted signal (not Vcc).
There are a high potential VH and a low potential VL (VH and VL are potentials generated inside the chip and change according to the operation mode of the chip).

FIG. 8 shows a configuration example of the buffer 46 in the circuits shown in FIGS. This buffer 46 is composed of inverters 52 and 53 whose input terminals and output terminals are cascaded. These inverters 5
The power supplies 2 and 53 have a high potential VH and a low potential VL to receive the level-converted signal.

FIG. 9 is a diagram for explaining the level converter according to the first embodiment of the present invention. The level converters 44 and 4 in the circuits shown in FIGS. 4 and 5 are described.
4a and 44b show an example of the configuration, and the above problem 2
This is a configuration example for solving (the low-level shifter 12 operates under conditions close to the minimum operation).

This level converter comprises a high level shifter 6
0, a low-level shifter 61 and a low-level shifter 62 are connected in cascade. The high-level shifter 60 converts the input signal IN into a voltage between VH and Vss (0 V). The low level shifter 61
VH-Vss output from the high level shifter 60
The voltage between them is converted into a voltage between VH and VL1. The low-level shifter 62 converts the voltage between VH and VL1 output from the low-level shifter 61 to V
This is converted into a voltage between H-VL2.

The high-level shifter 60 is provided, for example, in FIG.
And the low-level shifters 61 and 62 are configured, for example, in the same manner as the circuit shown in FIG. Each of the P-channel MOS transistors in each of the level shifters 60, 61, and 62 has the same cross-sectional configuration as shown in FIG. 24, and each of the N-channel MOS transistors has the same as the cross-sectional configuration shown in FIG.

In the conventional level converter having a two-stage configuration as shown in FIG. 20, the circuit threshold of low-level shifter 12 must be set between VH-0V. In this case, the circuit threshold value of the low-level shifter 62 may be set within the range of VH-VL, and the operation margin can be made wider than in the conventional case.

As shown in FIG. 10, for example, when generating a control gate voltage of -8 V at the time of erasing, VH =
By setting 1V, VL1 = -2V, and VL2 = -8V, the circuit threshold value of the low-level shifter 62 may be set in the range of -2 to 1V. When writing,
VH = 9V, VL1 = 0V, and VL2 = 0V may be set. It should be noted here that the low-level shifter 61 is also within the breakdown voltage design due to the relationship between VH and VL1.

That is, in the two-stage level converter,
The conversion potential difference between the high level and the low level may increase, and the operation margin of the second-stage low level shifter 12 is lost. Therefore, by making the level shift operation into three stages, the converted potential difference between each level shifter is reduced, and the level shift operation is facilitated (operation margin is improved).
are doing.

FIG. 11 shows another example of the configuration of the high-level shifter 60 in the circuit shown in FIG. The high level shifter 60 includes inverters 63, 64-1,.
64-2 and N-channel MOS transistors Q9, Q1
0. The inverter 63 includes:
It operates at a voltage between the power supply Vcc and 0 V, and an input signal is supplied from an input terminal in. One end of a current path of a MOS transistor Q9 having a gate connected to the power supply Vcc is connected to an output terminal of the inverter 63. The inverters 64-1 and 64-2 operate at a voltage between VH-0V,
The input terminal of the inverter 64-1 is connected to the other end of the current path of the transistor Q9. One end of the current path of the MOS transistor Q10 is connected to the power supply VH, the other end of the current path is connected to the input terminal of the inverter 64-1, and the gate is connected to the output terminal of the inverter 64-1. The output terminal of the inverter 64-1 is used as out, and the output terminal of the inverter 64-2 is connected to the input terminal of the inverter 64-2 and used as / out.

Even with such a configuration, basically the same operation as that of the high-level shifter shown in FIG. 22 is performed.

FIGS. 12 and 13 show circuits for generating the voltages VH and VL used in the above-described level converter, respectively. These voltages VH and VL are generated by boosting by boosting circuits 65 and 67 in the chip, or generated by converting the generated voltages into potentials by regulator circuits 66 and 68.

The voltage generating circuit shown in FIG. 12 generates a positive high voltage VH, and includes a booster circuit 65, a regulator circuit 66, and switches SW1 to SW3. The voltage V1 output from the booster circuit 65 is output as the power supply VHn via the switch SW1. Further, the output voltage V1 of the booster circuit 65 is
6 and converted into a potential, and output as a power supply VHm via a switch SW2. The switch SW3 is provided between the switches SW1 and SW2. By selectively switching the switches SW1 to SW3,
A potential can be selectively output.

The voltage generating circuit shown in FIG. 13 generates a negative high voltage VL, and like the voltage generating circuit generating the positive high voltage VH shown in FIG.
It is composed of a regulator circuit 68 and switches SW4 to SW6. Voltage V2 output from booster circuit 67
Is output as the power supply VLn via the switch SW4. Further, the output voltage V2 of the booster circuit 67 is supplied to the regulator circuit 68 to be converted in potential, and the switch S
It is output as the power supply VLm via W5. Switch S
W6 is provided between the switches SW4 and SW5, and can selectively output a potential by selectively switching each of the switches SW4 to SW6.

For example, as shown in FIG. 10, to generate VH (1 V) at the time of erasing, the switches SW2 and SW
3 to turn on the output voltage VSW of the regulator circuit 66.
May be used. To generate VL1 (-2V),
The switch SW5 is turned on to use the output voltage VBSW of the regulator circuit 68. In order to generate VL2 (−8V), the switch SW4 is turned on and the booster circuit 6 is turned on.
7 may be used.

On the other hand, to generate VH (9 V) at the time of writing, the switch SW1 is turned on and the output voltage V1 of the booster circuit 65 may be used. VL1, VL2 (0V)
May be directly used as the potential of the ground point Vss.

FIG. 14 is a circuit diagram showing a configuration example of the booster circuit 65 in the circuit shown in FIG. This booster circuit 65 includes diodes D1 to D3, capacitors C1,
C2 and inverters 69 and 70. The power supply voltage Vdd is applied to the anode of the diode D1. The diode D1 has a cathode connected to the diode D1.
2 and one electrode of the capacitor C1 are connected. The clock signal CLK is supplied to an input terminal of the inverter 69. The other terminal of the capacitor C1 and the input terminal of the inverter 70 are connected to the output terminal of the inverter 69. The cathode of the diode D2 is connected to the anode of the diode D3 and one electrode of the capacitor C2. The output terminal of the inverter 70 is connected to the other electrode of the capacitor C2. The boosted voltage V1 is output from the cathode of the diode D3.

The boosting circuit 67 in the circuit shown in FIG. 13 has basically the same configuration as that in FIG.

FIG. 15 is a circuit diagram showing a configuration example of the regulator circuit 66 in the circuit shown in FIG.
This regulator circuit 66 includes differential amplifiers 71 and 72,
N channel type MOS transistors Q11, Q12, Q1
5, Q16, P-channel MOS transistor Q13,
Q14 and resistors R1 to R4. The reference potential Vref is applied to the non-inverting input terminals (+) of the differential amplifiers 71 and 72. These differential amplifiers 71, 72
Output terminals of the MOS transistors Q11 and Q11, respectively.
Twelve gates are connected. MOS transistor Q
The sources of the MOS transistors Q1 and Q12 are connected to the ground point Vss, and the current mirror-connected MOS transistors Q1 are connected between each drain and the output terminal (V1 node) of the booster circuit 65.
3, Q14. The resistors R1, R2 and the current path of the MOS transistor Q15 are connected in series between the common drain connection point of the MOS transistors Q12, Q14 and the ground point Vss. The inverting input terminals (−) of the differential amplifiers 71 and 72 are connected to the connection points of the resistors R1 and R2, respectively, to form a feedback loop. The gate of the MOS transistor Q15 is supplied with a program signal PRG indicating a program state.
The resistors R3 and R4 and the current path of the MOS transistor Q16 are directly connected between the drain of the MOS transistor Q15 and the ground point Vss. And the above M
An erase signal ERS indicating an erased state is supplied to the gate of the OS transistor Q16.

The regulator circuit 66 configured as described above
In this case, the output voltage VSW has different potentials at the time of programming and at the time of erasing.

The regulator circuit 68 in the circuit shown in FIG. 13 has basically the same configuration as that in FIG.

According to the above configuration, the breakdown voltage between the level shifters can be kept within a certain range and the conversion potential difference between the level shifters can be reduced, so that the performance of the conversion operation can be improved.

In the above description, the MOS transistor forming the level converter is an ordinary P-channel or N-channel MOS transistor. However, the MOS transistor in the semiconductor memory device has a thicker gate oxide film. By using a withstand voltage transistor, not only the performance of the conversion operation can be improved, but also the withstand voltage can be improved.

[Second Embodiment] In the example of FIG. 13 described above, each potential is Vss>VL1> VL2, and VH = constant, but such a relationship is not necessarily required.

For example, when it is desired to generate 12 V at the output OUT, a configuration as shown in FIG. 16 may be employed. This level converter is configured by cascade-connecting a high-level shifter 75, a low-level shifter 76, and a high-level shifter 77. The high-level shifter 75 converts the input signal IN into a voltage between VH1 and Vss.
The low level shifter 76 is connected to the high level shifter 7.
5 between VH1-Vss is VH1-Vss.
The voltage is converted into a voltage between L. The high-level shifter 77 converts a voltage between VH1 and VL output from the low-level shifter 76 into a voltage between VH2 and VL. Each of the above voltages is, for example, VH1 = 6
V, VH2 = 12V, and VL = 3V.

Here, it is defined that the high level shifter changes on the VH side and the low level shifter changes on the VL side.

The high-level shifters 75 and 77 are configured, for example, in the same manner as the circuits shown in FIGS. 22 and 11, and the low-level shifter 76 is configured, for example, in the same manner as the circuit shown in FIG. Also, each level shifter 75, 7
6 and 77 are shown in FIG.
4 is the same as the cross-sectional configuration shown in FIG.
The S transistor has the same cross-sectional configuration as shown in FIG.

In the second embodiment, in order to output 12 V, as a first step, the voltage is converted to a withstand voltage of, for example, 6 V, then the VL level is set to 3 V, and then the VH level is set to 12 V. In this manner, the level can be increased stepwise, so that the withstand voltage of the transistor does not exceed 9 V.

That is, according to the second embodiment, when converting to a potential exceeding the withstand voltage of the transistor, the potential is increased stepwise, thereby enabling level conversion within the withstand voltage design.

[Third Embodiment] FIG. 17 shows a level converter according to a third embodiment of the present invention.
This embodiment is a configuration for solving problem 1 (operating under a voltage condition close to the minimum operation of the high-level shifter and the low-level shifter).

This level converter comprises a high level shifter 8
0, a low-level shifter 81, a high-level shifter 82, and a low-level shifter 83. The high-level shifter 80 converts the input signal IN into a voltage between VH1 and Vss. The low level shifter 81
Is VH1- output from the high-level shifter 80.
It converts a voltage between Vss to a voltage between VH1 and VL1. The high level shifter 82 converts a voltage between VH1 and VL1 output from the low level shifter 81 into a voltage between VH2 and VL1. The low level shifter 83 converts a voltage between VH2 and VL1 output from the high level shifter 82 into a voltage between VH2 and VL2. The potential levels are, for example, VH1 = 5V, VH2 = 1V, VL1 = −2V, V
L2 = −8V.

The reason that the level of VL is stepped from VL1 to VL2 is to prevent the low-level shifter from operating under a voltage condition close to the operation minimum.

A feature of this embodiment is that the level of VH is changed from VH1 to VH2.

As described in the above voltage example, by setting the power of the input high-level shifter to 5 V, VH2 is made higher than 1 V to improve the operating voltage condition of the first-stage high-level shifter 80. The low-level shifter 81 has a voltage within the withstand voltage range.
The conversion to the L1 level prepares for the improvement of the operating voltage condition of the low-level shifter 83. High level shifter 82
In consideration of the withstand voltage at the time of conversion in the low-level shifter 83, the VH level is set low and VH2 = 1V to avoid the withstand voltage problem in the low-level shifter 83. The low-level shifter 83 performs the level conversion with a margin as a circuit threshold finally.

[Fourth Embodiment] FIG. 18 is a diagram for explaining a semiconductor device according to a fourth embodiment of the present invention. The level according to the first to third embodiments is described. It is a semiconductor device using a converter. This circuit has a first path passing through the level converter 90 and a second path passing through the level converter 91, and these two paths are selected and used by the switch circuit 92. . The level converter 90 is the level converter according to the above-described first to third embodiments, and the level converter 91 is a high-level shifter, a low-level shifter, or a high-level shifter as shown in FIG. And a low-level shifter.

The switch circuit 92 is composed of clocked inverters 93 and 94 operating at voltages VH and VL, for example, as shown in FIG. 19, and supplies control signals CS and / CS to their clock input terminals. Then, when one clocked inverter is operating, the other clocked inverter is in a non-operating state.

When a high-speed operation is required, such as a memory read operation, or when the operation margin is not so strict (when the erase operation is not performed), the clocked inverter 94 is in the operating state and the clocked inverter 93 is in the non-operating state. By setting the operation state and selecting the second path having a small number of stages, the delay of the level conversion can be reduced with respect to the operation requiring the speed. On the other hand, when a high-speed operation is not required or when an operation margin is strict, such as an erase operation, the clocked inverter 93 is set to the operation state, the clocked inverter 94 is set to the non-operation state, and the first path is selected. Stabilize.

According to such a configuration, the operation minimum (circuit performance) of the level conversion operation can be improved while observing the conditions of the potential required by the memory cell and the withstand voltage of the transistor.

Although the present invention has been described with reference to the first to fourth embodiments, the present invention is not limited to each of the above-described embodiments, and the scope of the present invention does not depart from the gist of the present invention. Can be variously modified. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent features. For example, even if some components are deleted from all the components shown in each embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and the effects described in the column of the effect of the invention can be solved. In a case where at least one of the effects described above is obtained, a configuration in which this component is deleted can be extracted as an invention.

[0091]

As described above, according to the present invention, a level converter capable of improving the operation minimum (circuit performance) of the level conversion operation can be obtained.

Further, a semiconductor device having a level converter capable of improving the operation minimum (circuit performance) of the level conversion operation while observing the conditions of the potential required by the memory cell and the withstand voltage of the transistor can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a level converter according to a first embodiment of the present invention and a semiconductor device including the level converter, and includes a nonvolatile semiconductor memory device (EEP).
(ROM).

FIG. 2 is a circuit diagram showing a configuration example of a memory cell array in the system block diagram shown in FIG. 1 and showing a schematic configuration of a memory cell array in a flash memory;

FIG. 3 is a cross-sectional view illustrating a structure called a stack gate type as an example of a storage element (memory cell) which is a basic unit of an EEPROM.

FIG. 4 is a block diagram showing a circuit configuration example of a row decoder in the system block diagram shown in FIG. 1;

FIG. 5 is a block diagram showing another example of the circuit configuration of the row decoder in the system block diagram shown in FIG. 1;

FIG. 6 is a circuit diagram showing a configuration example of an address conversion unit in the circuits shown in FIGS. 4 and 5;

FIG. 7 is a circuit diagram showing a configuration example of an address conversion unit in the circuit shown in FIG. 5;

FIG. 8 is a circuit diagram showing a configuration example of a buffer in the circuits shown in FIGS. 4 and 5;

FIG. 9 is a circuit diagram for explaining the level converter according to the first embodiment of the present invention, and showing a configuration example of the level converter in the circuits shown in FIGS. 4 and 5;

FIG. 10 is a diagram for explaining the operation of the level converter shown in FIG. 9;

FIG. 11 is a circuit diagram showing another configuration example of the high-level shifter in the circuit shown in FIG. 9;

12 is a circuit diagram showing a configuration example of a voltage generation circuit that generates a positive voltage used in the level converter shown in FIG.

FIG. 13 is a circuit diagram showing a configuration example of a voltage generation circuit that generates a negative voltage used in the level converter shown in FIG. 11;

FIG. 14 is a circuit diagram illustrating a configuration example of a booster circuit in the circuit illustrated in FIG. 12;

15 is a circuit diagram showing a configuration example of a regulator circuit in the circuit shown in FIG.

FIG. 16 is a circuit diagram for explaining a level converter according to a second embodiment of the present invention, showing another configuration example of the level converter in the circuits shown in FIGS. 4 and 5;

FIG. 17 is a circuit diagram for explaining a level converter according to a third embodiment of the present invention, and showing still another configuration example of the level converter in the circuits shown in FIGS. 4 and 5;

FIG. 18 is a circuit diagram for describing a semiconductor device including a level converter according to a fourth embodiment of the present invention.

FIG. 19 is a circuit diagram showing a configuration example of a switch circuit in the circuit shown in FIG. 18;

FIG. 20 is a circuit diagram showing a conventional level converter.

21 is a diagram showing an example of a relationship between a VH level or a VL level given to the circuit shown in FIG. 20 and an operation of the semiconductor memory device;

FIG. 22 is a circuit diagram showing a configuration example of a high-level shifter in the circuit shown in FIG. 20;

23 illustrates an input / output relationship of the circuit illustrated in FIG. 22;

FIG. 24 shows a P-channel type M in the circuit shown in FIG. 22;
FIG. 4 is a cross-sectional view illustrating an element configuration of an OS transistor.

FIG. 25 shows an N-channel type M in the circuit shown in FIG. 22;
FIG. 4 is a cross-sectional view illustrating an element configuration of an OS transistor.

FIG. 26 is a circuit diagram showing a configuration example of a low-level shifter in the circuit shown in FIG. 20;

FIG. 27 is a diagram showing an input / output relationship of the circuit shown in FIG. 24;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 21 ... Memory cell array, 22 ... Row decoder, 23 ... Column decoder, 24 ... Source / well decoder, 25 ... Input circuit, 26 ... Control circuit, 27 ... Boost circuit, 28 ... Write circuit, 29 ... Read circuit, 30 ... Output Circuit 31 P-type semiconductor substrate 32 N-type well region 33 P-type well region 34 Source region 35 Drain region 36 Gate insulating film 37 Floating gate 38 Insulation on floating gate Film, 39 control gate, 41, 41a, 41b internal address signal line, 42, 42a, 42b address conversion section, 43, 43a, 43b address selection line, 44, 44a, 44b level converter, 45, 45a, 45b: Level conversion selection line, 46: Buffer, 47: Address conversion unit, 50, 51: AND gate , 52,53,63,64-1,64-2,69,70 ...
Inverter, 60, 75, 77, 80, 82: High level shifter, 61, 62, 76, 81, 83: Low level shifter, 65, 67: Booster circuit, 66, 68: Regulator circuit, 71, 72: Differential amplifier, 90, 91: level converter, 92: switch circuit, MC: memory cell, WL0, WL1, WL2, WLn: word line, BL0, BL1, BL2, BL3: bit line, ADD, ADDa, ADDb: internal address signal, Q9 to Q16: MOS transistors, SW1 to SW6, switches, D1 to D3, diodes, C1, C2, capacitors, VH, VH1, VH2, VL, VL1, VL2, power supply potential.

Claims (14)

[Claims] A first level shifter for converting a logic level comprising a first level and a second level into a logic level comprising a third level and a fourth level; and a third level receiving an output of the first level shifter. And the fourth
A second level shifter for level-converting a logic level consisting of a fifth level and a sixth level to a logic level consisting of a fifth level and a sixth level;
A third level shifter for level-converting a logic level comprising a seventh level and a logic level comprising an eighth level; wherein the second level and the fourth level have the same potential; The fifth level is at the same potential, the fifth level and the seventh level are at the same potential, the third level is higher than the first level, and the fourth level is higher than the sixth level. The level converter, wherein the sixth level is higher than the eighth level. 2. A first level shifter for converting a logic level consisting of a first level and a second level to a logic level consisting of a third level and a fourth level; and a third level receiving an output of the first level shifter. And the fourth
A second level shifter for level-converting a logic level consisting of a fifth level and a sixth level to a logic level consisting of a fifth level and a sixth level;
A third level shifter for level-converting a logic level comprising a seventh level and a logic level comprising an eighth level; wherein the second level and the fourth level have the same potential; The fifth level has the same potential, the sixth level and the eighth level have the same potential, the third level is higher than the first level, and the sixth level is higher than the fourth level. The level converter, wherein the seventh level is higher than the fifth level. 3. A first level shifter for level-converting a logic level consisting of a first level and a second level to a logic level consisting of a third level and a fourth level, and a third level receiving an output of the first level shifter. And the fourth
A second level shifter for level-converting a logic level consisting of a fifth level and a sixth level to a logic level consisting of a fifth level and a sixth level;
A third level shifter for level-converting a logic level consisting of a level to a logic level consisting of a seventh level and an eighth level;
A fourth level shifter for level-converting a logical level comprising a ninth level and a logical level comprising a tenth level, wherein the second level and the fourth level are at the same potential; The fifth level has the same potential, the sixth level and the eighth level have the same potential, the seventh level and the ninth level have the same potential, and the third level has a higher potential than the first level. The level converter, wherein the sixth level is higher than the fourth level, the fifth level is higher than the seventh level, and the eighth level is higher than the tenth level. 4. An output terminal and an input terminal of first to n-th (n is a positive integer of 3 or more) level shifters for converting an input logic level to a different logic level and outputting the converted logic level are sequentially cascaded. The adjacent level shifters operate at a power supply voltage in which one of the voltage levels is substantially equal to each other, sequentially change the potential difference of the logic level input to the first-stage level shifter, and output from the last-stage level shifter. Level translator. 5. The first to third level shifters are formed in a semiconductor chip, and the third to third level shifters are formed in the semiconductor chip.
3. The level converter according to claim 1, further comprising a potential generation unit configured to generate at least one of a level to an eighth level. 6. The first to fourth level shifters are formed in a semiconductor chip, and the third to fourth level shifters are formed in the semiconductor chip.
4. The level converter according to claim 3, further comprising a potential generating means for generating at least one of a level to a tenth level. 7. The first to third level shifters are formed in a semiconductor chip, and a potential generating means provided in the semiconductor chip, and a potential generating means provided in the semiconductor chip and generated by the potential generating means. 3. The level converter according to claim 1, further comprising a potential conversion unit configured to convert a potential to generate at least one of the third to eighth levels. 8. The first to fourth level shifters are formed in a semiconductor chip, and a potential generating means provided in the semiconductor chip, and a potential generating means provided in the semiconductor chip and generated by the potential generating means. Converting a potential into at least one of the third to tenth levels
4. The level converter according to claim 3, further comprising: a potential converter that generates two potentials. 9. A level converter for converting a logical level of a signal output from an address converter to an address signal line in a semiconductor memory device, wherein a logical level comprising a first level and a second level is converted to a third level. A first level shifter for converting the level to a logic level consisting of a third level and a fourth level;
A second level shifter for level-converting a logic level comprising a fifth level and a sixth level to a logic level comprising a fifth level and a sixth level;
A third level shifter for converting a logic level of the first level shifter to a logic level of a seventh level and an eighth level; 1 negative potential, the sixth level of the second level shifter is a second negative potential lower than the first negative potential, and the eighth level of the third level shifter is a third negative potential lower than the second negative potential. A level converter characterized by being a potential. 10. A level converter for converting a logical level of a signal output from an address converter to an address signal line in a semiconductor memory device, wherein a logical level comprising a first level and a second level is converted to a third level. A first level shifter for converting a level to a logic level consisting of a third level and a fourth level;
A second level shifter for level-converting a logic level consisting of a fifth level and a sixth level to a logic level consisting of a fifth level and a sixth level;
A third level shifter for level-converting a logic level consisting of a level to a logic level consisting of a seventh level and an eighth level;
A fourth level shifter for level-converting a logic level comprising a ninth level to a logic level comprising a ninth level; and a third level output from the first level shifter during an erasing operation of the semiconductor memory device. Is the first
The positive potential and the fourth level are first negative potentials. The sixth level output from the second level shifter is a second negative potential lower than the first negative potential, and the seventh level output from the third level shifter. A level converter, wherein a level is a third positive potential lower than the first positive potential, and a tenth level output from the fourth level shifter is a fourth negative potential lower than the third negative potential. 11. A first level converter configured by cascading three or more level shifters, a second level converter configured by cascading one level shifter or two level shifters, and an operation mode. And a switch circuit for selecting and outputting one of the output signal of the first level converter and the output signal of the second level converter in response to a control signal corresponding to the above. 12. The semiconductor device according to claim 11, wherein said first level converter comprises the level converter according to any one of claims 1 to 10. 13. The semiconductor device according to claim 11, further comprising a memory unit, wherein said switch circuit selects an output signal of said second level converter during a data read operation of said memory unit. . 14. The device according to claim 11, further comprising a memory unit, wherein the switch circuit selects an output signal of the first level converter during a data write or erase operation of the memory unit. Semiconductor device.