JP2007172743A - Storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase read-out speed for a nonvolatile memory cell without increasing layout area. <P>SOLUTION: A flash memory (2) is provided with a flash memory array (30) consisting of a plurality of nonvolatile memory cells MM00, MM01, MM0m, MMy0, MMym arranged in matrix. A current source (36) for read-out supplies a current in parallel to respective main bit lines BL0, BK1, BLm in read-out operation. A column switch circuit (37) connects the main bit line specified by an address signal out of a plurality of main bit lines to a common bit line CNBL. A sense amplifier (38), in read-out operation, receives a read-out signal transmitted to the common bit line, compares a potential of the main bit line connected to the common bit line with the reference potential Vref, detects whether a current is made to flow between a drain D and a source SC of the nonvolatile memory cell to be read or not. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a storage device including a nonvolatile memory cell, for example, a technique effective when applied to a flash memory.

  The nonvolatile memory includes a plurality of nonvolatile memory cells that can store information by changing an electrical threshold voltage. The nonvolatile memory, when reading or verifying, applies a predetermined voltage to the word line and detects whether or not a current flows between the drain and the source of the nonvolatile memory cell. Make a decision.

  Patent Document 1 describes a memory in which a bit line connected to a nonvolatile memory cell is connected to a common data line via a transfer gate such as a column switch, and a current source transistor is connected to the common data line. There is. An input terminal of a read amplifier is connected to the common data line.

JP 2000-173280 A

  The inventor has studied a means for speeding up reading from a nonvolatile memory cell. In Patent Document 1, each time a bit line is selected by a column switch in reading or verifying, a charge current is supplied from a current source transistor to the selected bit line. The read amplifier detects whether or not a current flows through the nonvolatile memory cell in a state where the selected bit line is completely charged. For this reason, in Patent Document 1, when the selection of a bit line is switched by a column switch in reading or verifying, it is necessary to wait until charging of the newly selected bit line is completed.

  In addition, the present inventor connects a current source transistor to each bit line, and provides one read amplifier for each of the two bit lines so that one bit line is mutually read and the other is a reference. Thus, a configuration in which a read operation using a read amplifier was performed by controlling the current source was studied. The output of the read amplifier is connected to the shared data line via the column switch. According to this, in the read operation, current is supplied to each bit line by a unique current source transistor, so even if the column switch is switched, the bit line to be selected by the switching is changed. There is no need to wait for a new current to be supplied from the current source transistor. However, since a read amplifier is arranged for each column switch, the layout area becomes large.

  An object of the present invention is to provide a memory device that can speed up reading from a nonvolatile memory cell without increasing the layout area.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A memory device according to the present invention includes a memory array (30), a current source circuit (36), a column switch circuit (37), and an amplifier circuit (38). The memory array has a plurality of word lines (CG0, CGy), a plurality of first data lines (BL0, BL1, BLm), and a plurality of second data lines. The memory array is connected between a corresponding first data line and a second data line, and a plurality of nonvolatile memory cells (MM00, MM01, MM0m, MMy0, MMy1, MMym). The current source circuit supplies a current in parallel to each of the first data lines in a read operation. The column switch circuit connects a first data line designated by an address signal among the plurality of first data lines to a common data line (CMBL). In the read operation, the amplifier circuit inputs and amplifies the read signal transmitted to the common data line.

  As described above, since the current is always supplied to each of the first data lines in the read operation, even if the selection of the first data by the column switch circuit is switched, the first data line is selected by the switching. There is no need to wait for a new current to be supplied to the data line. That is, since the current source circuit supplies current to the first data line in parallel, the potentials of the plurality of first data lines are stabilized in parallel. Thus, in a read operation for a plurality of nonvolatile memory cells, if the time until the potential of one first data line reaches a predetermined potential has elapsed, the first data line is output by the column switch circuit. Immediately after the selection is switched, the read data can be determined by the output of the amplifier circuit. As a result, reading from the nonvolatile memory cell can be speeded up.

  In addition, since the read signal is input to the amplifier circuit by connecting the first data line and the common data line by the column switch circuit, the amplifier circuit for the plurality of first data lines connectable to the common data line is One is sufficient and the layout area does not increase.

  As a specific form of the present invention, the first data line includes a main bit line (BL0, BLm, BLx) and a string switch (ST00, ST0m, ST0x, STy0, STym, STym) on the main bit line. And sub-bit lines (lbl0, lblm, lblx, lbls, lblt, lblu) connected via. The nonvolatile memory cell is connected between the sub bit line and the second data line. As described above, in the read operation, by switching the string switch, only the sub bit line connected to the nonvolatile memory cell to be read can be connected to the main bit line, and the load capacity of the first data line can be reduced. The overall size can be reduced.

  As a specific form of the present invention, the second data line is shared by the nonvolatile memory cells connected to the adjacent sub bit lines. From the above, the number of common source lines in the memory array can be reduced.

  As a specific form of the present invention, the column switch circuit includes a first column switch (YA0, YAm) connected to each of the first data lines and a second column connected to the common data line. Column switches (YB0, YBn). The first column switch is grouped for each of a predetermined number of the first data lines, and selects a first data line commonly designated by a part of the address signal for each group. The second column switch selects a first data line designated by the remaining signal of the address signal from the first data lines selected by the first column switch. From the above, when the first data line designated by the address signal is selected from among the plurality of first data lines, the first column switch is selected by using the lower bits of the address signal, for example, without selecting it once. After selection, the second column switch is selected using the upper bits. Thereby, the column switch circuit can be hierarchized, and the scale of the logic circuit in the decoder can be reduced.

  As a specific form of the present invention, the plurality of nonvolatile memory cells are connected in parallel between the corresponding first data line and the second data line. From the above, the memory array is configured as a NOR type.

  As a specific form of the present invention, the plurality of nonvolatile memory cells are connected in series between the corresponding first data line and the second data line. From the above, the memory array is configured as a NAND type.

  [2] A memory device according to the present invention includes a plurality of bit lines, a plurality of nonvolatile memory cells connected to each of the plurality of bit lines, and one or a plurality of sense circuits. An input of the sense circuit is connected to each of at least two bit lines via a switch circuit. A current supply circuit for supplying current in parallel is connected to each of the at least two bit lines. In a read operation from the non-volatile memory cell connected to the at least two bit lines, the current is applied while the at least two bit lines and the sense circuit are disconnected under the control of the switch circuit. A current is supplied from the supply circuit to the at least two bit lines. Under the control of the switch circuit, one of the at least two bit lines is connected to the sense circuit to read out data stored in the first nonvolatile memory cell, and then the control of the switch circuit The other of the at least two bit lines is connected to the sense circuit to read data stored in the second nonvolatile memory cell.

  From the above, in the read operation, when the number of external output bits is one, only one sense circuit is required for at least two bit lines. Further, in the read operation, when the number of external output bits is a plurality of bits, the number of sense circuits is arranged according to the number of external output bits. In either case, the layout area does not increase because only one sense circuit is required for at least two bit lines that can be connected to the input of the sense circuit via the switch circuit. Furthermore, since the current is supplied in parallel to at least two bit lines under the control of the switch circuit, the potential is stabilized in parallel. When the selection of at least two bit lines is switched under the control of the switch circuit in a state where this potential is stable, the data stored in the nonvolatile memory cell can be immediately determined by the sense circuit. . As a result, reading from the nonvolatile memory cell can be speeded up.

  As a specific form of the present invention, a central processing unit is further provided. The switch circuit is controlled according to control from the central processing unit. From the above, the reading operation is executed by the central processing unit.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to speed up reading from the nonvolatile memory cell without increasing the layout area.

  FIG. 2 shows an example of a data processor to which the present invention is applied. The data processor 1 is, for example, a single-chip microcomputer with built-in flash memory, and includes a flash memory (FLASH) 2 and a central processing unit (CPU) 3. The CPU 3 has a control theory (CNTLOGIC) 4 inside and performs all control of the data processor 1 based on a program stored in a read-only memory (ROM) 5. The ROM 5 stores programs to be executed by the CPU 3 and fixed data. A random access memory (RAM) 6 stores the calculation results by the CPU 3 and also serves as a work area for the CPU 3. A direct memory access controller (DMAC) 7 performs control to transfer data in a predetermined block unit between the ROM 5 and RAM 6 and an external memory (not shown). A serial communication interface circuit (SCI) 8 performs serial communication with an external device (not shown). A timer (TIMER) 9 counts the set time, and when the set time is reached, sets a flag or generates an interrupt request. A clock pulse generation circuit (CPG) 10 generates a clock signal having a certain frequency and supplies it to the clock line 11 as a system clock.

  Input / output ports (IOP) 12 to 20 are input / output terminals for externally connecting the data processor 1. The flash memory 2, the CPU 3, the ROM 5, the RAM 6, the DMAC 7, and the IOPs 12 to 16 are connected via a main address bus (IAB) 21 and a main data bus (IDB) 22, respectively. The peripheral circuits such as the timer 9 and the SCI 8 and the IOPs 12 to 20 are connected via a peripheral address bus (PAB) 23 and a peripheral data bus (PDB) 24, respectively. Further, the bus sequence controller (BSC) 25 controls the transfer of signals between the IAB 21 and IDB 22, and the PAB 23 and PDB 24, and controls the state of each bus.

  FIG. 3 shows an example of functional blocks of the flash memory 2. In the figure, systems such as address signals and control signals are omitted. The flash memory 2 is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon by a MOS integrated circuit manufacturing technique. The flash memory 2 has a flash memory array 30. The flash memory array 30 is composed of a plurality of nonvolatile memory cells arranged in a matrix.

  The control circuit 31 receives a control signal input from the outside, and controls the flash memory 2 as a whole in accordance with commands such as writing, erasing, and reading according to the state of the control signal. Various signals such as read data and write data for the flash memory array 30 are input to and output from the input / output circuit 32. The address buffer 33 temporarily stores an address input from the outside. An X decoder 34 and a Y decoder 35 are connected to the address buffer 33, respectively. The X decoder 34 performs decoding based on the row address output from the address buffer 33. The Y decoder 35 performs decoding based on the column address output from the address buffer 33. Further, the flash memory 2 includes a read circuit used for read or verify (hereinafter referred to as read operation), for example. The read circuit includes a read current source 36, a column switch circuit 37, a sense amplifier 38, and the like. The write circuit 39 latches the write data input via the input / output circuit 32 and controls data writing. The power supply circuit 40 generates a write pulse voltage and an erase pulse voltage used for writing, erasing and the like.

  FIG. 1 shows an example of a read circuit of the flash memory 2 according to Embodiment 1 of the present invention. The read circuit is a circuit that makes it possible to detect storage information of a plurality of nonvolatile memory cells MM00, MM01, MM0m, MMy0, MMy1, and MMym constituting the flash memory array 30 in a read operation. A column switch circuit 37, a sense amplifier 38, and the like. The nonvolatile memory cells MM00, MM01, MM0m, MMy0, MMy1, and MMym are not particularly limited, but are configured by an insulated gate n-channel field effect transistor (hereinafter referred to as nMOS) having a two-layer gate structure. For example, the nonvolatile memory cell MM00 includes a P-type well region PW provided on a P-type silicon substrate, a source SC and a drain DR formed in the P-type well region PW, a floating gate FG, and a control gate CG. Have. The floating gate FG is disposed on the channel formation region between the source SC and the drain DR via a thin gate oxide film as a tunnel insulating film. The control gate CG is disposed on the floating gate FG via an insulating film. In the nonvolatile memory cell MM00, the drain DR is connected to the main bit line BL0, the control gate CG is connected to the word line CG0, and the source SC is connected to the source line. This source line is connected to VSS of 0 V at the time of reading. The plurality of nonvolatile memory cells MM00, MM01, MM0m, MMy0, MMy1, and MMym are connected in parallel between the corresponding main bit lines BL0, BL1, and BLm and the source lines, and the corresponding word lines CG0 and CGy. Is selectively controlled. The flash memory array 30 is configured as a NOR type.

  Next, the read circuit will be described in detail. The read current source 36 includes current sources p0, p1, and pm of p-channel field effect transistors (hereinafter referred to as pMOS), each gate terminal is connected to the switch control line SAP, and the drain terminal is the main bit line BL0. , BL1 and BLm, and the source terminal is connected to VDD of 1.5V, for example. Therefore, the read current source 36 supplies a read current in parallel to the main bit lines BL0, BL1, and BLm in the read operation. That is, the read current is always supplied to the main bit lines BL0, BL1, and BLm in the read operation. The column switch circuit 37 includes, for example, nMOS column switches Y0, Y1, and Ym, and is connected to the main bit lines BL0, BL1, and BLm, respectively. The column switch circuit 37 selects the main bit line specified by the address signal from the plurality of main bit lines BL0, BL1, and BLm based on the selection signal output from the Y decoder 35, and this main bit line. Are connected to the common bit line CMBL.

  The sense amplifier 38 has a positive input terminal connected to the common data line CMBL and a negative input terminal connected to the reference potential Vref. In the sense amplifier 38, the read signal transmitted from the main bit line selected by the column switch circuit 36 to the common data line CMBL is input to the positive input terminal, and the reference potential Vref is input to the negative input terminal. The sense amplifier 38 compares this read signal with the reference potential Vref, and outputs the result from the output terminal out to the input / output circuit 32.

  Here, the read signal is a current path between the drain DR and the source SC of the nonvolatile memory cell to be read by constantly supplying a read current to the plurality of main bit lines BL0, BL1, and BLm. It is a signal indicating the potential of the main bit line determined according to whether or not it is formed. Since the current path is not formed when the threshold voltage of the nonvolatile memory cell is high, the potential of the main bit line is determined to be a potential close to VDD of the read current source 36, for example, and the threshold voltage of the nonvolatile memory cell is If it is low, a current path is formed, so that the potential is determined to be low. In other words, since the potential of the main bit line is determined to be one of the two potentials, if the reference potential Vref is set to a potential between the two potentials, the sense amplifier 38 can read the nonvolatile data. The threshold voltage of the memory cell can be determined. Hereinafter, the time until the potential of the main bit line reaches one of the two potentials is referred to as a bit line stabilization time.

  When the nonvolatile memory cell MM00 is to be read, the word line CG0 is selected and the column switch Y0 is turned on after the potential of the main bit line BL0 is determined. Then, the sense amplifier 38 detects whether a current path is formed between the drain DR and the source SC of the nonvolatile memory cell MM00, and determines the threshold voltage.

  Specifically, 1.5 V is applied to the word line CG0 as a selection voltage so that the write state and the erase state of the nonvolatile memory cell MM00 can be distinguished, the switch control line SAP is set to 0 V, and Vref is set to 1. Apply 0V. At this time, 0 V is applied to the word line CGy and 0 V is applied to the column switches Y0, Y1, and Ym as non-selection voltages. Since the current sources p0, p1, and pm supply read currents to the main bit lines BL0, BL1, and BLm in parallel, the potentials of the main bit lines BL0, BL1, and BLm are determined after the bit line stabilization time has elapsed. The Then, 1.5 V is applied to the column switch Y0 to connect the main bit line BL0 and the common bit line CMBL. The sense amplifier 38 compares the potential of the main bit line BL0 transmitted to the common bit line CMBL with a reference potential of 1.0 V, and outputs the result from the output terminal out. In the sense amplifier 38, if the potential of the main bit line BL0 is 1.0 V or more, the output value of the output terminal out is 1.5 V, and if the potential of the main bit line BL0 is less than 1.0 V, the output terminal out. Output value becomes 0V. That is, if the output terminal out of the sense amplifier 38 is 1.5V, the nonvolatile memory cell MM00 is determined to be in the write state because the current path is not formed and the threshold voltage is high, and similarly, the output value is 0V. For example, a current path is formed and the threshold voltage is low, so that the erase state is determined.

  That is, in the read operation of the nonvolatile memory cell MM00, the bit line stabilization time and the time from when the column switch Y0 is turned on until the output value is output from the output terminal out of the sense amplifier 38 (hereinafter referred to as detection time). ). This detection time includes, for example, the charging time of the parasitic capacitance when the column switch Y0 is turned on. The parasitic capacitance charging time is the time for charging the wiring capacitance and the diffusion layer capacitance between the column switch Y0 and the sense amplifier 38. After the column switch Y0 is turned on, the sense amplifier 38 determines the main bit line BL0. This is the time required for the input potential to be input. However, the wiring capacitance and the diffusion layer capacitance are smaller than the main bit line capacitance, and therefore, the charging time of the capacitance is shorter than the bit line stabilization time.

  FIG. 4 illustrates a timing chart of the read operation in the read circuit illustrated in FIG. Here, a case where a plurality of nonvolatile memory cells MM00, MM01, and MM0m are to be read will be described. The read current is supplied in parallel from the read current source 36 to the main bit lines BL0, BL1, and BLm at time t0, and the respective potentials are determined at time t1. Since the read current source 36 continues to supply the read current to the main bit lines BL0, BL1, and BLm from time t1 to time t2, the potential of each main bit line maintains the potential at time t1. it can. Further, after the bit line stabilization time has elapsed, the column switch Y0 is turned on, and the threshold voltage of the nonvolatile memory cell MM00 is determined by the sense amplifier 38. This period is a reading period of the nonvolatile memory cell MM00 in the drawing.

  Next, in the read period of the nonvolatile memory cell MM01, 0V is applied to the column switch Y0 and 1.5V is applied to the column switch Y1. When the determined potential of the main bit line BL1 is input to the sense amplifier 38 via the common bit line CMBL, the threshold voltage of the nonvolatile memory cell MM01 is determined by the sense amplifier 38. Similarly, in the read period of the nonvolatile memory cell MM0m, 0V is applied to the column switches Y0 and Y1, and 1.5V is applied to the column switch Ym. When the determined potential of the main bit line BLm is input to the sense amplifier 38 via the common bit line CMBL, the threshold voltage of the nonvolatile memory cell MM0m is determined by the sense amplifier 38. At time t2, 0V is applied as a non-selection voltage to the word line CG0, and the read operation is completed. As described above, the read period of the nonvolatile memory cells MM00, MM01, MM0m eliminates the bit line stabilization time and only requires the detection time of the sense amplifier 38.

  In short, the read circuit of the flash memory 2 requires the bit line stabilization time of the main bit line BL0 in the read operation of the nonvolatile memory cell MM00, but the read operation of the nonvolatile memory cells MM01 and MM0m requires the bit line stability. Time can be omitted. In other words, in the read circuit, even if the selection of the main bit lines BL1 and BLm by the column switch circuit 37 is switched in the read operation, the read operation has already been performed on the main bit lines BL1 and BLm to be selected by the switching. Since the working currents are supplied in parallel, there is no need to wait for the respective potentials to be determined. Therefore, according to the flash memory 2, it is possible to speed up reading from a plurality of nonvolatile memory cells constituting the flash memory array 30.

  Further, since only one sense amplifier 38 is required for all the main bit lines BL0, BL1, and BLm that can be connected to the common data line CMBL, the layout area of the read circuit does not increase. Furthermore, since the read current source 36 supplies the read current to the main bit lines BL0, BL1, and BLm in parallel, the column switch circuit 37 does not need to pass the read current. For this reason, the gate widths of the column switches Y0, Y1, and Ym can be reduced.

  In other words, if the time required for the read operation for a plurality of non-volatile memory cells is the same as the conventional time, if the bit line stabilization time for one bit line has elapsed, Since the other bit line stabilization time can be omitted, the detection time of the sense amplifier 38 can be lengthened. For this reason, the determination accuracy of the threshold voltage of the nonvolatile memory cell to be read can be increased while setting the time required for the read operation to be the same as the conventional time. This also increases the accuracy of verification after the rewrite operation, for example, and reduces the unnecessary rewrite operation, thereby reducing the stress associated with voltage application to the nonvolatile memory cell and improving the number of rewrites. You can also.

  FIG. 5 shows an example of a read circuit of a flash memory according to the second embodiment of the present invention. Hereinafter, in each of Embodiments 2 to 6, parts having the same functions and the like as those of the read circuit of the flash memory 2 described above are denoted by the same reference numerals, and duplicated description will be omitted as appropriate. This flash memory includes a flash memory array 41. The flash memory array 41 includes a plurality of nonvolatile memory cells MM00, MM01, MM0m, MMy0, MMy1, and MMym. The plurality of nonvolatile memory cells MM00, MM01, MM0m, MMy0, MMy1, and MMym are connected in series between the corresponding main bit lines BL0, BL1, and BLm and the source lines, and the corresponding word line CG0. , CGy is selectively controlled. The flash memory array 41 is configured as a NAND type. The read circuit is a circuit that makes it possible to detect information stored in a plurality of nonvolatile memory cells MM00, MM01, MM0m, MMy0, MMy1, and MMym that constitute the NAND flash memory array 41, and is a read current source 36. A column switch circuit 37, a sense amplifier 38, and the like. In the read circuit, when the nonvolatile memory cell MM00 is to be read, the flash memory array 41 is a NAND type, so that a transfer voltage of 3.0 V is applied to unselected word lines typified by the word line CGy. The Other operations are the same as the read operation in the read circuit of the flash memory 2 described above. The transfer voltage is a voltage at which the non-volatile memory cell connected to the word line CGy becomes conductive even in the write state, and is applied to the word line CG0 to distinguish between the write state and the erase state of the non-volatile memory cell MM00. The selected voltage is higher than the selected voltage.

  FIG. 6 illustrates a timing chart of the read operation in the read circuit illustrated in FIG. This timing chart differs from the timing chart shown in FIG. 4 in that 3.0 V is applied to the word line CGy as a transfer voltage at time t0. For this reason, since the potentials of the main bit lines BL0, BL1, and BLm are determined at time t1, the read period of the nonvolatile memory cells MM00, MM01, and MM0m performed at times t1 and t2 is only the detection time of the sense amplifier 38. Just do it. Therefore, according to the flash memory of the second embodiment, it is possible to speed up reading from a plurality of nonvolatile memory cells constituting the flash memory array 41.

  FIG. 7 shows an example of a read circuit of a flash memory according to Embodiment 3 of the present invention. The flash memory includes a flash memory array 42. The flash memory array 42 includes a plurality of nonvolatile memory cells MM00, MM0m, MM0x, MMy0, MMym, and MMyx. The read circuit includes a read current source 43, a column switch circuit 44, a sense amplifier 38, and the like. The flash memory array 42 has a larger number of main bit lines than the flash memory array 30 described above. Accordingly, the read current source 43 includes pMOS current sources p0, pm, and px, which are connected to the main bit lines BL0, BLm, and BLx, and supply the read current in parallel.

  The column switch circuit 44 is a circuit for connecting a main bit line designated by an address signal from a plurality of main bit lines BL0, BLm, BLx to a common bit line CMBL. For example, nMOS column switches YA0, YAm , YB0, YBn. The column switches YA0 and YAm are grouped by the first common bit line CMBL1 and the second common bit line CMBL2, respectively. The main bit lines BL0, BLm, BLx are connected to the grouped column switches YA0, YAm. The column switch YB0 connects the column switches YA0 and YAm grouped by the first common bit line CMBL1 to the common bit line CMBL. The column switch YBn connects the column switches YA0 and YAm grouped by the second common bit line CMBL2 to the common bit line CMBL.

  In short, the column switch circuit 44 is hierarchized. The grouped column switches YA0 and YAm select the main bit line designated in common using, for example, the lower bits of the address signal for each group. Thereafter, the column switches YB0 and YBn select the main bit line from the main bit lines selected by the column switches YA0 and YAm for each group using, for example, the upper bits of the address signal. Therefore, when the main bit line is selected from the main bit lines BL0, BLm, BLx in the column switch circuit 44, the number of bits of the address signal can be reduced. Can be reduced.

  FIG. 8 illustrates a timing chart of the read operation in the read circuit illustrated in FIG. In the read operation, when the main bit line specified by the address signal is selected by the column switch circuit 44 in the read operation, the read circuit sets a timing for turning on the grouped column switches YA0 and YAm and the column switches YB0 and YBn. Except for the points to consider, it is the same as the read circuit of the flash memory 2 described above. This timing chart is for reading a plurality of nonvolatile memory cells MM00, MM0m, MM0x, and is shown in FIG. 4 except that 0 V is applied to the column switches YA0, YAm, YB0, YBn at times t0 to t1. This is the same as the timing chart. Therefore, the potentials of the main bit lines BL0, BLm, and BLx are determined at time t1, and the read period of the nonvolatile memory cells MM00, MM0m, and MM0x performed at times t1 and t2 is only the detection time of the sense amplifier 38. .

  That is, in the read period of the nonvolatile memory cell MM00, 1.5 V is applied to the column switches YA0 and YB0, and the threshold voltage of the nonvolatile memory cell MM00 is determined by the sense amplifier 38. In the read period of the nonvolatile memory cell MM0m, 1.5V is applied to the column switches YAm and YB0, and the threshold voltage of the nonvolatile memory cell MM0m is determined by the sense amplifier 38. Similarly, in the read period of the nonvolatile memory cell MM0x, 1.5V is applied to the column switches YAm and YBn, and the threshold voltage of the nonvolatile memory cell MM0x is determined by the sense amplifier 38.

  As described above, in the flash memory according to the third embodiment, the read operation of the nonvolatile memory cell MM00 requires the bit line stabilization time of the main bit line BL0, but the read operation of the nonvolatile memory cells MM0m and MM0x The bit line stabilization time of the bit lines BLm and BLx can be omitted. Therefore, according to the read circuit of the flash memory of the third embodiment, the read operation with respect to the plurality of nonvolatile memory cells constituting the flash memory array 42 can be speeded up.

  FIG. 9 shows an example of a read circuit of a flash memory according to Embodiment 4 of the present invention. The read circuit can detect storage information of a plurality of nonvolatile memory cells MM00L, MM00R, MM01L, MM01R, MM0xL, MM0xR, MMy0L, MMy0R, MMy1L, MMy1R, MMyxL, and MMyxR constituting the flash memory array 45 in a read operation. It is a circuit to make. The read circuit includes a read current source 43, a column switch circuit 44, a sense amplifier 38, and the like. The flash memory array 45 has a main / sub bit line structure, and further has a structure in which nonvolatile memory cells connected to adjacent sub bit lines share a source line. That is, in the plurality of nonvolatile memory cells, for example, the sub-bit lines lbl0, lbl1, lbl2, lbl3, lblq, and lblr are connected to the drain terminals.

  The sub-bit lines lbl0, lbl2, and lblq are commonly connected to the main bit lines BL0, BL1, and BLx via string switches ST0L, ST1L, and STxL connected to the selection control line Z0, respectively. The sub bit lines lbl1, lbl3, and lblr are commonly connected to the main bit lines BL0, BL1, and BLx through string switches ST0R, ST1R, and STxR connected to the selection control line Z1, respectively. Thereby, the load capacity of the bit line can be reduced as a whole. In the plurality of nonvolatile memory cells, word lines CG0 and CGy are connected to the control gate CG. For example, the source terminals of the plurality of nonvolatile memory cells MM00R, MM01L, MMy0R, and MMy1L connected to the adjacent subbit lines lbl1 and lbl2 share the source line. Thereby, the flash memory array 45 can reduce the number of common source lines.

  When the nonvolatile memory cell MM00L is to be read, 1.5 V is selected as the selection voltage for the word line CG0, 1.5 V is selected for the selection control line Z0, 0 V is used for the switch control line SAP, and 1.0 V is used as the reference potential for Vref. Apply each. At this time, 0 V is applied to the word line CGy and 0 V is applied to the column switches YA0, YA1, YAm, YB0, and YBn as non-selection voltages. Further, 0 V is applied to the selection control line Z1. Since the current sources p0, p1, and px supply read currents to the main bit lines BL0, BL1, and BLx in parallel, after the bit line stabilization time has elapsed, the main bit lines BL0, BL1, and BLx and the sub-bit lines The potentials of lbl0, lbl2, and lblq are determined. Then, 1.5 V is applied to the column switches YA0 and YB0, and the main bit line BL0 and the sub bit line lb0 are connected to the common bit line CMBL via the column switches YA0 and YB0 and the string switch ST0L. The sense amplifier 38 compares the potentials of the main bit line BL0 and the sub bit line lbl0 with a reference potential of 1.0 V, and outputs the result from the output terminal out.

  FIG. 10 illustrates a timing chart of the read operation in the read circuit illustrated in FIG. In this timing chart, a plurality of nonvolatile memory cells MM00L and MM00R connected to the main bit lines BL0, BL1, and BLx through string switches connected to the word line CG0 and connected to different selection control lines Z0 and Z1. , MM01L, MM01R, MM0xL, and MM0xR are read. Therefore, the read circuit applies 1.5 V to the selection control line Z0 at time t0 to t2, reads data from the nonvolatile memory cells MM00L, MM01L, and MM0xL, and sets 1 to the selection control line Z1 at time t2 to t4. .5 V is applied, and the nonvolatile memory cells MM00R, MM01R, and MM0xR are read.

  The read operation at the times t0 to t1 is the same as that when the nonvolatile memory cell MM00L is a read target. That is, at time t1, the potentials of the main bit lines BL0, BL1, and BLx and the sub bit lines lbl0, lbl2, and lblq are determined. Therefore, 1.5 V is applied to the column switches YA0 and YB0 in the read period of the nonvolatile memory cell MM00L, and the threshold voltage of the nonvolatile memory cell MM00L is determined by the sense amplifier 38. During the read period of the nonvolatile memory cell MM01L, 1.5V is applied to the column switches YA1 and YB0, and the threshold voltage of the nonvolatile memory cell MM01L is determined by the sense amplifier 38. Similarly, in the read period of the nonvolatile memory cell MM0xL, 1.5 V is applied to the column switches YAm and YBn, and the threshold voltage of the nonvolatile memory cell MM0xL is determined by the sense amplifier 38. As described above, the reading period of the nonvolatile memory cells MM00L, MM01L, and MM0xL performed at the times t1 to t2 is only the detection time of the sense amplifier 38.

  Next, at time t2, 0V is applied to the selection control line Z0 and 1.5V is applied to the selection control line Z1. As a result, the read current from the current sources p0, p1, px is supplied in parallel to the main bit lines BL0, BL1, BLx and the sub bit lines lbl1, lbl3, lblr. The potentials of BL0, BL1, BLx, and sub-bit lines lbl1, lbl3, lblr are determined. Therefore, 1.5 V is applied to the column switches YA0 and YB0 during the read period of the nonvolatile memory cell MM00R, and the threshold voltage of the nonvolatile memory cell MM00R is determined by the sense amplifier 38. In the read period of the nonvolatile memory cell MM01R, 1.5 V is applied to the column switches YA1 and YB0, and the threshold voltage of the nonvolatile memory cell MM01R is determined by the sense amplifier 38. Similarly, during the read period of the nonvolatile memory cell MM0xR, 1.5 V is applied to the column switches YAm and YBn, and the threshold voltage of the nonvolatile memory cell MM0xR is determined by the sense amplifier 38. As described above, the reading period of the nonvolatile memory cells MM00R, MM01R, and MM0xR performed at the times t3 to t4 is only the detection time of the sense amplifier 38.

  In short, in the flash memory according to the fourth embodiment, the read operation of the nonvolatile memory cells MM00L and MM00R requires the bit line stabilization time for the main bit line BL0 and the sub bit lines lbl0 and lbl1, respectively. However, in the read operation of the non-volatile memory cells MM01L, MM01R, MM0xL, MM0xR, the bit line stabilization time of the main bit lines BL1, BLx and the sub bit lines lbl2, lbl3, lblq, lbrl can be omitted. Therefore, according to the flash memory of the fourth embodiment, it is possible to speed up reading from a plurality of nonvolatile memory cells constituting the flash memory array 45.

  FIG. 11 shows an example of a read circuit of a flash memory according to the fifth embodiment of the present invention. The read circuit is a circuit that makes it possible to detect storage information of a plurality of nonvolatile memory cells MM00, MM0m, MM0x, MMy0, MMym, and MMyx constituting the flash memory array 46 in a read operation. A column switch circuit 44, a sense amplifier 38, and the like. The flash memory array 46 has a main / sub bit line structure, and only the sub bit lines connected to the nonvolatile memory cells to be read by the string switches ST00, ST0m, ST0x, STy0, STym, STyx are used as the main bit lines. Can connect. Thereby, the load capacity of the bit line can be reduced as a whole.

  The plurality of nonvolatile memory cells MM00, MM0m, MM0x, MMy0, MMym, MMyx, for example, are connected to the sub-bit lines lb0, lblm, lb1x, lbls, lblt, lblu at their drain terminals. The sub bit lines lbl0, lblm, and lbx are connected to the main bit lines BL0, BLm, and BLx via string switches ST00, ST0m, and ST0x connected to the selection control line Z0. The sub bit lines lbls, lblt, lblu are connected to the main bit lines BL0, BLm, BLx via string switches STy0, STym, STyx connected to the selection control line Z1. In addition, in the nonvolatile memory cells MM00, MM0m, MM0x, MMy0, MMym, and MMyx, the control gate CG is connected to the word lines CG0 and CGy, and the source terminals are connected to the common source line for each column. This common source line is connected to, for example, VSS of 0 V at the time of reading.

  FIG. 12 illustrates a timing chart of the read operation in the read circuit illustrated in FIG. This timing chart reads a plurality of nonvolatile memory cells MM00, MM0m, and MM0x, and is substantially the same as the operation up to time t2 in the timing chart shown in FIG. In other words, at time t0, the read current is supplied in parallel from the read current source 43 to not only the main bit lines BL0, BLm, and BLx but also the sub bit lines lb10, lblm, and lbx. Then, the potentials of these bit lines are determined at time t1. Since the selection control line Z1 is 0 V until time t2, the potentials of the sub-bit lines lbls, lblt, lblu do not change.

  The read period of the nonvolatile memory cells MM00, MM0m, MM0x is only the detection time of the sense amplifier 38. In short, in the flash memory according to the fifth embodiment, the read operation of the nonvolatile memory cell MM00 requires the bit line stabilization time of the main bit line BL0 and the sub bit line lbl0, but the read operation of the nonvolatile memory cells MM0m and MM0x. Then, the bit line stabilization time of the main bit lines BLm and BLx and the sub bit lines lblm and lblx can be omitted. Therefore, according to the flash memory of the fifth embodiment, it is possible to speed up reading from a plurality of nonvolatile memory cells constituting the flash memory array 46.

  FIG. 13 shows an example of a read circuit of a flash memory according to Embodiment 6 of the present invention. Compared with the read circuit of the flash memory 2 shown in FIG. 1, this read circuit controls the voltage of the switch control line SAP (hereinafter referred to as the SAP voltage) by current trimming to control the current sources p0, p1, and pm. The difference is that it functions as a constant current source. The SAP voltage is a gate voltage of current sources p0, p1, and pm using pMOS. pp and nn are pMOS. Vgi is the gate potential of nn. Similarly to the current sources p0, p1, and pm, VDD is connected to the source terminal of pp. In the amplifier 47, the reference potential Vref is connected to the negative input terminal, and the node A between nn and pp is connected to the positive input terminal.

  nn functions as a constant current source controlled by Vgi. That is, since the node A is feedback-controlled by the amplifier 47 so as to have the same potential as Vref, a constant current flows through the pp connected via the node A. Since the gate terminals of the current sources p0, p1, pm, and pp are commonly connected, a constant current also flows through the current sources p0, p1, and pm. For this reason, if the MOS sizes of the current sources p0, p1, and pm are the same, the same current flows through the main bit lines BL0, BL1, and BLm. Therefore, according to the flash memory of the sixth embodiment, a constant current source is used in the read circuit, and the threshold voltage of the nonvolatile memory cell to be read can be determined under a certain condition, thereby improving the read operation accuracy. Can be made.

  In the first to sixth embodiments, a sense latch circuit (not shown) is connected to each bit line, and the sense latch circuit is used to latch write control data. Further, the above-described current source transistor may be configured using some transistors of the sense latch circuit.

  As mentioned above, although the invention made by this inventor was concretely demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to it and can be variously changed in the range which does not deviate from the summary.

  For example, in the flash memory read circuit shown in each embodiment, the configuration in which the number of external output bits is 1 is illustrated, but the present invention is not limited to this, and the number of external output bits is a plurality of bits. For this purpose, a plurality of sets of read circuits shown in each figure may be arranged according to the number of external output bits. Further, in the read circuit of the flash memory 2 shown in FIG. 1, the flash memory array 30 may be a memory array having a structure like the flash memory arrays 45 and 46 shown in FIGS. Further, in the read circuit shown in FIG. 5, the column switch circuit 37 may have a hierarchical structure like the column switch circuit 44 shown in FIG. Further, in the flash memory read circuit shown in FIGS. 9 and 11, the flash memory arrays 45 and 46 may be memory arrays having structures like the flash memory arrays 30 and 41 shown in FIGS. The SAP voltage control by current trimming shown in FIG. 13 may be applied to the flash memory read circuit in the second to fifth embodiments.

  In each of the above embodiments, when the nonvolatile memory cell MM00 is to be read, the corresponding column switch is turned on after the bit line stabilization time has elapsed. However, the present invention is not limited to this, and at time t0. You may make it conduct. Even in this case, only the read period of the nonvolatile memory cell MM00 becomes longer by the bit line stabilization time, and the read period of other nonvolatile memory cells to be read does not change. Further, although a memory cell having a floating gate is used as a nonvolatile memory cell, the present invention is not limited to this as long as a read operation using the sense amplifier 38 is performed, and a MONOS type memory cell having an insulating charge storage region For example, it may be of an appropriate type and shape. Further, although the pMOS current sources p0, p1, and pm are used as the read current source 36, any appropriate type may be used as long as the read current can be supplied. Further, the nMOS is used as the column switch, but the present invention is not limited to this, and a pMOS or a CMOS type in which nMOS and pMOS are combined may be used. The sense amplifier 38 may be of any appropriate type as long as the potential of the main bit line and the reference potential can be compared. Further, the present invention can be applied to an appropriate semiconductor memory device such as an IC card incorporating a nonvolatile memory such as a flash memory.

FIG. 3 is an explanatory diagram illustrating the read circuit of the flash memory according to the first embodiment of the invention. It is explanatory drawing which illustrates the data processor to which this invention is applied. It is explanatory drawing which illustrates the functional block of flash memory. 3 is a timing chart of a read operation in the read circuit shown in FIG. 7 is an explanatory diagram illustrating a read circuit of a flash memory according to a second embodiment of the invention. FIG. 6 is a timing chart of a read operation in the read circuit shown in FIG. It is explanatory drawing which illustrates the read-out circuit of the flash memory which concerns on Embodiment 3 of this invention. 8 is a timing chart of a read operation in the read circuit shown in FIG. It is explanatory drawing which illustrates the read-out circuit of the flash memory which concerns on Embodiment 4 of this invention. 10 is a timing chart of a read operation in the read circuit shown in FIG. 9. FIG. 10 is an explanatory diagram illustrating a flash memory read circuit according to a fifth embodiment of the invention; 12 is a timing chart of a read operation in the read circuit shown in FIG. It is explanatory drawing which illustrates the read-out circuit of the flash memory which concerns on Embodiment 6 of this invention.

Explanation of symbols

1 Data processor 2 Flash memory (FLASH)
3 Central processing unit (CPU)
5 Read-only memory (ROM)
6 Random access memory (RAM)
7 Direct memory access controller (DMAC)
8 Serial communication interface circuit (SCI)
9 Timer (TIMER)
10 Clock pulse generator (CPG)
11 Clock line 12-20 Input / output port (IOP)
30 Flash Memory Array 31 Control Circuit 32 Input / Output Circuit 33 Address Buffer 34 X Decoder 35 Y Decoder 36 Current Source for Reading 37 Column Switch Circuit 38 Sense Amplifier 39 Write Circuit 40 Power Supply Circuit

Claims (8)

A plurality of word lines, a plurality of first data lines, a plurality of second data lines, connected between corresponding first data lines and second data lines, and selectively switched by the corresponding word lines A memory array having a plurality of non-volatile memory cells to be controlled;
In a read operation, a current source circuit that supplies current in parallel to each of the first data lines;
A column switch circuit for connecting a first data line designated by an address signal from the plurality of first data lines to a common data line;
A storage device comprising: an amplification circuit that inputs and amplifies a read signal transmitted to the common data line in a read operation. The first data line includes a main bit line and a sub bit line connected to the main bit line via a string switch,
The memory device according to claim 1, wherein the nonvolatile memory cell is connected between the sub bit line and the second data line.   The storage device according to claim 2, wherein the second data line is shared by the nonvolatile memory cells connected to the adjacent sub bit lines. The column switch circuit includes a first column switch connected to each of the first data lines, and a second column switch connected to the common data line,
The first column switch is grouped for each of a predetermined number of the first data lines, and selects a first data line commonly designated by a part of the address signal for each group,
2. The storage device according to claim 1, wherein the second column switch selects a first data line designated by a remaining signal of the address signal from among the first data lines selected by the first column switch. .   The storage device according to claim 1, wherein the plurality of nonvolatile memory cells are connected in parallel between the corresponding first data line and the second data line.   The storage device according to claim 1, wherein the plurality of nonvolatile memory cells are connected in series between the corresponding first data line and the second data line. A plurality of bit lines; a plurality of nonvolatile memory cells connected to each of the plurality of bit lines; and a single or a plurality of sense circuits;
The input of the sense circuit is connected to each of at least two bit lines via a switch circuit,
A current supply circuit that supplies current in parallel is connected to each of the at least two bit lines.
In a read operation from the non-volatile memory cell connected to the at least two bit lines, the current is applied while the at least two bit lines and the sense circuit are disconnected under the control of the switch circuit. A current is supplied from the supply circuit to the at least two bit lines, and one of the at least two bit lines is connected to the sense circuit and stored in the first nonvolatile memory cell under the control of the switch circuit. After reading the data, the control circuit controls the memory to read the data stored in the second nonvolatile memory cell by connecting the other of the at least two bit lines to the sense circuit. apparatus. A central processing unit,
The storage device according to claim 7, wherein the switch circuit is controlled according to control from the central processing unit.

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