JPH06112443A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a NAND cell type EEPROM capable of shortening the time required for a writing of data/write verify readout operation without being accompanied by an increase in a power consumption. CONSTITUTION:An EEPROM is provided with a memory cell array 1, which has a charge storage layer and a control gate and is arranged with nonvolatile memory cells on a semiconductor substrate, a row decoder 5, which is provided at the end part in the direction of a word line of this cell array 1 and drives the control gate, and a verify control circuit, which sets a unit write time in the memory cells in a prescribed range of the array 1 to perform a writing of data and thereafter, reads out the data written in the memory cells and in the case where there is a memory cell which is insufficient in the writing, performs a rewriting in the memory cell. In the EEPROM, at the time of a write varify readout operation, a voltage to be applied to a well formed with a transistor having a conductivity type inverse to that of a transistor of the array 1 is set in a voltage higher than a supply voltage in the row decoder 5 and when the operation of the verify control circuit is changed from the writing operation of data to the write verify readout operation, this voltage is prevented from being reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device (EEPROM) using an electrically rewritable memory cell having a floating gate and a control gate, and more particularly to an N-type semiconductor memory device.
EEPRO having a memory cell array of AND cell configuration
Regarding M.

[0002]

2. Description of the Related Art A NAND cell type EEPROM capable of high integration is known as one of EEPROMs. This is to connect a plurality of memory cells in series such that their sources and drains are shared by adjacent ones and connect them to a bit line as a unit. A memory cell is usually a FETMOS in which a charge storage layer and a control gate are stacked.
Have a structure. The memory cell array is integrated and formed in a p-type well formed on a p-type substrate or an n-type substrate. NA
The drain side of the ND cell is connected to the bit line via the selection gate, and the source side is also connected to the source line (reference potential wiring) via the selection gate. The control gates of the memory cells are continuously arranged in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. The data write operation is performed in order from the memory cell farthest from the bit line. A high voltage Vpp (= 20V is applied to the control gate of the selected memory cell.
(Approx.) Is applied to the control gate and the select gate of the memory cell on the bit line side of the intermediate potential VppM (= 10V).
(Approx.) Is applied and 0 V or an intermediate potential is applied to the bit line depending on the data. When 0V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. This shifts the threshold value of the selected memory cell in the positive direction. This state is, for example, "1". When an intermediate potential is applied to the bit line, electron injection does not occur, so the threshold value does not change and remains negative. This state is "0"
Is.

Data erasing is simultaneously performed on all memory cells in the NAND cell. That is, all control gates and select gates are set to 0V, bit lines and source lines are set in a floating state, and a high voltage of 20V is applied to the p-type well and n-type substrate
Is applied. As a result, in all memory cells, electrons in the floating gate are emitted to the p-type well, and the threshold value shifts in the negative direction.

In the data read operation, the control gate of the selected memory cell is set to 0V, the control gates and the selection gates of the other memory cells are set to the power supply potential Vcc (= 5V), and whether or not a current flows in the selected memory cell. It is performed by detecting whether or not.

As is clear from the above description of the operation, the NA
In the ND cell type EEPROM, the unselected memory cells act as transfer gates during write and read operations. From this point of view, the threshold voltage of the programmed memory cell is limited. For example, the preferable range of the threshold value of the memory cell programmed with "1" is 0.5 to 3.5V.
It will be about. Considering changes with time after data writing, variations in manufacturing parameters of memory cells, and variations in power supply voltage, the threshold distribution after data writing is required to be in a smaller range.

However, it is difficult to keep the threshold value range after "1" writing within the permissible range by the conventional method of writing data in all memory cells under the same condition with fixed write potential and write time. . For example, the characteristics of memory cells vary due to variations in the manufacturing process. Therefore, looking at the write characteristics, there are memory cells that are easy to write and memory cells that are hard to write. On the other hand, a method has been proposed in which writing is performed while verifying by adjusting the writing time so that the threshold value of each memory cell is written so as to fall within a desired range. Next, write while verifying (write /
A conventional example of the write verify read operation) will be briefly described with reference to FIG.

First, a block selecting operation (step S1)
After that, the n-well of the row decoder is boosted from the power supply potential Vcc to the boosted potential VppW using the booster circuit (step S2). At this time, a part of the control gate and the select gate changes from the ground potential Vss to the power supply potential Vcc. Subsequently, the control gate of the memory cell to be written is set to the boosted potential VppW from the power supply potential Vcc to perform the write operation (step S3), and then the potentials of the control gate and the select gate are returned to the ground potential Vss. Further, the potential of the n-well of the row decoder is returned to the power supply potential Vcc.

Then, a write verify read operation (step S4) is performed, and when all the potentials of the bit lines connected to the memory cells for writing "1" data are determined to be "L" level, that is, "1" data. When the writing is sufficient in all of the memory cells to be written, the block selection cancel operation (step S5) is performed, and the write / write verify read operation is completed. Further, when it is determined that the potential of at least one of the bit lines connected to the memory cell for writing “1” data is “H” level, that is, at least one of the memory cells for writing “1” data is
On the other hand, if there are insufficiently written memory cells, the operations of steps S2 → S3 → S4 are performed again. And
S2 → S3 → S4 → S2 → S3 → S4 until writing is sufficient in all the memory cells for writing “1” data.
--->S2->S3-> S4 is repeated, and then S5 is performed to complete the write / write verify read operation.

As described above, when the operations of S2 to S4 are frequently performed during the write / write verify read operation, in the method of repeating a plurality of times, n is repeated each time the loop of S2 to S4 is repeated.
Since the operation S2 of boosting the well from Vcc to VppW is performed, the required time τ1 is required for the number of loops.
Therefore, there is a drawback that the time required for the write / write verify read operation becomes long. In addition, if the current supply capability of the booster circuit that generates the VppW potential is increased to shorten τ1, the problem that the power consumption increases will occur.

[0011]

As described above, the conventional N
In the AND cell type EEPROM, it is difficult to shorten the time required for the data write / write verify read operation, and there is a problem that power consumption increases in order to solve this.

The present invention has been made in consideration of the above circumstances, and an object thereof is to shorten the time required for the data write / write verify read operation without increasing the power consumption. To provide a NAND cell type EEPROM.

[0013]

In order to solve the above problems, the present invention adopts the following configuration.

That is, the present invention provides a memory cell array in which a charge storage layer and a control gate are stacked on a semiconductor substrate, and memory cells arranged in an array for electrical rewriting by transfer of charges between the charge storage layer and the substrate. Provided at one end or both ends of the memory cell array in the word line direction,
A row decoder including elements formed on a plurality of wells having a polarity opposite to that of a well in which a memory cell array is formed, and a unit write time is set in memory cells in a predetermined range of the memory cell array and data writing is performed at the same time. In a non-volatile semiconductor memory device having a verify control means for reading the memory cell data and rewriting if there is a memory cell that has not been sufficiently written, at least one of the wells of opposite polarities at the time of a write verify operation. It is characterized in that the applied voltage is higher than the power supply voltage.

Further, the present invention is characterized in that the voltage applied to the well to which a voltage higher than the power supply voltage is applied does not drop when the data write operation is changed to the write verify read operation in the above structure. further,
In the memory cell array, a plurality of memory cells are connected in series to form a NAND cell, and one end of the NAND cell is connected to a bit line through a select gate, which is applied to a well of a row decoder during a write verify operation. The voltage higher than the power supply voltage is higher than the voltage applied to the select gate.

[0016]

In the present invention, at the start of the data write / write verify read operation, at least one of the plurality of n wells in which the plurality of p channel MOSFETs of the row decoder is formed is supplied with a predetermined high voltage (from the power supply voltage). After being charged to a voltage higher than the power supply voltage), the data write operation and the write verify read operation are performed once while maintaining the predetermined high voltage, or the write operation → write verify read operation → write operation → write verify read Operation →… → Write operation → Write verify Read operation is repeated multiple times in order. Then, after there are no insufficiently written memory cells, the voltage of the n-well to which the high voltage is applied is lowered to the power supply voltage, and then the process is terminated.

As described above, according to the present invention, the number of times the n-well to which the high voltage is applied is charged from the power supply voltage to a predetermined high voltage is determined by the number of times the data write operation and the write verify read operation are sequentially repeated. Instead, the data write / write verify read operation can be performed only once. Therefore, the time required for the data write / write verify read operation can be shortened without increasing the power consumption.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a NAN in one embodiment of the present invention.
The structure of a D-cell type EEPROM is shown. Data writing, reading, rewriting to the memory cell array 1,
And the bit line control circuit 2 for performing the verify read.
Is provided. The bit line control circuit is connected to the data input / output buffer 6 and receives as an input the output of the column decoder 3 which receives the address signal from the address buffer 4. In addition, a row decoder 5 for controlling a control gate and a select gate for the memory cell array 1 is used.
And a substrate potential control circuit 7 for controlling the potential of the p substrate (or p type well) in which the memory cell array 1 is formed.

The bit line control circuit 2 is mainly composed of a CMOS flip-flop, and has a latch operation for writing data, a sensing operation for reading the potential of the bit line, a sensing operation for verify reading after writing, and a re-writing operation. Latch the write data.

2A and 2B are a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array,
3A and 3B are cross-sectional views taken along the lines AA 'and BB' of FIG. 2A, respectively. A plurality of NAs are formed on the p-type silicon substrate (or p-type well) 11 surrounded by the element isolation oxide film 12.
A memory cell array composed of ND cells is formed.
Explaining one NAND cell, in this embodiment, eight memory cells M _{1 to} M ₈ are connected in series to form one NAND cell. Each memory cell has a floating gate 1 on a substrate 11 with a gate insulating film 13 interposed therebetween.
4 (14 ₁ , 14 ₂ , ..., 14 ₈ ) are formed, and the control gate 16 (16 ₁ , 1 ₁ , 1
6 ₂ , ..., 16 ₈ ) are formed and configured. The n-type diffusion layers 19 serving as the source and drain of these memory cells are connected in series so that adjacent n-type diffusion layers 19 are shared by both.

On the drain side and the source side of the NAND cell, select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ formed at the same time as the floating gate and control gate of the memory cell, respectively.
Is provided. The substrate on which the elements are formed is covered with the CVD oxide film 17, and the bit line 18 is provided on the substrate. The bit line 18 is in contact with the drain side diffusion layer 19 at one end of the NAND cell. The control gates 14 of the NAND cells arranged in the row direction are commonly connected to the control gate line C.
It is arranged as G ₁ , CG ₂ , ..., CG ₈ . These control gate lines become word lines. Selection gate 14 ₉ ,
16 ₉ and 14 ₁₀ and 16 ₁₀ are also continuously arranged in the row direction as select gate lines SG ₁ and SG ₂ .

FIG. 4 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix. The memory cell array is composed of a plurality of NAND cell blocks 20 (20 _{1 to} 20 _n ) as shown in FIG.

FIG. 6 shows a specific configuration of the row decoder 5 of FIG. 1 for one NAND cell block 20 ₁ . The row decoder 5 uses a plurality of address signals a _i
NAND gate G1 which is the logical product of
With respect to the selected block, the node N1 becomes "H" level.

The row decoder 5 includes an enable circuit 51,
High voltage switching circuit 52 and drive circuit 53 for various gates
Etc. The high voltage switching circuit 52 is a p-channel MO
It is composed of S load transistors Qp13 and Qp14 and n-channel MOS driver transistors Qn43 and Qn44. The signal of the node N1 is input to the gate of one driver transistor Qn43 via the transfer gates Qn41, Qn42, Qp11, Qp12 of the enable circuit 51, and inverted by the inverter I8 to the gate of the other driver transistor Qn44. It As a result, complementary outputs are obtained in the high voltage switching circuit 52. The input signal VPPRW connected to the high voltage switching circuit 52 is the boosted potential VPP during the write operation and the erase operation, respectively.
It is set to W (= 18V) and VPPE (= 20V), and is set to the Vcc potential in other cases.

Further, each control gate CGi (i = 1 to 8)
And the input signal CGiD (i = 1 to 8) are p channel MOS transistors Qp21 to Qp2 having a negative threshold voltage.
8 and n-channel MOS transistors Qn52, Qn54 to Qn66 having a positive threshold voltage, and nodes N3 and N4 are connected to the gates of the p-channel and n-channel MOS transistors, respectively. Also,
Each control gate CGi is connected to the ground potential through n-channel MOS transistors Qn53, Qn55 to Qn67, and the gate of this n-channel MOS transistor has a node N3.
Are connected.

The selection gates SGi (i = 1, 2) and the input signals SGiD (i = 1, 2) are connected via n-channel MOS transistors Qn50, Qn68 and p-channel MOS transistors Qp20, Qp29, respectively. p-channel,
Nodes N3 and N4 are connected to the gates of the n-channel MOS transistors, respectively. Further, each select gate SGi is connected to the input signal Vuss via the n-channel MOS transistors Qn51 and Qn69, and the n-channel MO
The node N3 is connected to the gate of the S transistor.

The bit line BL is provided on one side of the NAND cell.
k (k = 1 to m) and the other side is connected to the source potential Vcsource. Further, the potential Vwell of the p-well in which the memory cell is configured is set to the boosted potential VPPE (= 20V) during the erase operation, and is set to the ground potential during other operations. In addition, Qp13, Qp14,
The n-well composed of Qp20 to Qp29 is set to VNwell.

The timing of the write operation and the write verify read operation of the row decoder 5 thus configured will be described with reference to FIGS. 7 and 8. First of all,
The operation timing in the selected block will be described by taking the case where the third cell of the NAND cells is selected as an example.

In the standby state, the logical product of the plurality of address signals ai is "L". Therefore, the node N1 is Vss, the node N2 is Vcc, the node N3 is Vcc, and the node N.
4 is in the Vss state. Therefore, SG1, SG2, CG
i (i = 1 to 8) and an n-channel MO connecting the ground potential
S-transistors Qn51, Qn53, Qn55, Qn57, Qn59, Qn61,
Since Qn63, Qn65, Qn67 and Qn69 are in the ON state, SG1, SG2 and CGi (i = 1 to 8) are all Vss.
Is in a state.

Subsequently, when the write / write verify read operation is started, the block selection operation ((1) in FIGS. 7 and 8) is first performed. Since RDENB and the address signal ai become Vss → Vcc, the node N1 also becomes Vss → Vcc, so that the node N3 becomes Vcc → Vss and the node N4 becomes Vss.
→ Vcc, SG1, SG2, CGi (i = 1 to 8)
The n-channel and p-channel MOS transistors connecting S1D, SG1D, SG2D, and CGiD (i = 1 to 8) are all turned on. In addition, SG1, SG2, CGi (i =
All n-channel MOS transistors connecting 1 to 8) to the ground potential are turned off.

Subsequently, VPPRW and VNwell are changed from Vcc to V
The n-well boosting operation ((2) in FIGS. 7 and 8) at ppW (for example, 18 V) is performed. In this case, the p-channel MOS to which the VppW potential in the row decoder is applied is generally used.
Since the n-well in which the transistor is configured is shared by multiple blocks, the n-well of the non-selected block must be charged as Vcc → VppW, and the number of blocks sharing this n-well. When there are many, the load of the booster circuit that generates VppW becomes large. In addition, since the current supply capability of the booster circuit is sufficiently smaller than that of the power supply,
The time required for changing PRW and VNwell from Vcc to VppW (τ1 in FIG. 8) becomes long. An example of this type of booster circuit is shown in FIG. This booster circuit includes n-channel MOS transistors Qn13 to Qn22 and an inverter I10 to
It is composed of I14 and capacitors C1 to C5 and has a well-known structure.

Subsequently, a write operation ((2) in FIGS. 7 and 8) is performed. First, SG1D and CGiD (i = 1 to 1) are written.
8) becomes Vss → Vcc, SG1, SG2, CGi
(I = 1 to 8) also becomes Vss → Vcc. At the same time, the potential of the bit line connected to the memory cell for writing "0" data, that is, the memory cell for keeping the threshold voltage negative becomes Vss → Vcc, and further becomes Vcc → VM8 (for example, 8V). In this case, if there are many memory cells that write "0" data, many bit lines must be changed from Vcc to VM8, which increases the load of the booster circuit that generates VM8. As in the case where VPPRW and VNwell are changed from Vcc to VppW, the required time (τ2 in FIG. 8) becomes long.

Subsequently, SG1D and CGiD (i = 1 to 1)
8) is Vcc → VM10 (eg 10V), so SG
1, CGi (i = 1 to 8) also becomes Vcc → VM10. In this case, since only SG1 and CGi (i = 1 to 8) in the selected block are charged as Vcc → VM10, the load capacity of the booster circuit for generating VM10 is not so large, and therefore Vcc → The time required to charge with VM10 is also sufficiently shorter than τ1 and τ2 as shown in FIG.

Subsequently, when CG3D becomes VM10 → VppW, CG3 also becomes VM10 → VppW. Also in this case, VppW
Since the only part to be charged up to is CG3, the load capacitance of the part where the booster circuit for generating VppW charges from VM10 to VppW is not so large. Therefore, as shown in FIG. 8, the time required to set VM10 → VppW is τ1,
Compared with τ 2, it is sufficiently short. After CG1, 2, 4-8 and SG1 are kept at VM10 and CG3 is kept at VppW for a while, SG1D and CGiD (i = 1 to 8) are all V
SG1, CGi (i = 1 to 8) because it drops to ss potential
Also becomes Vss.

Then, the potential of the bit line connected to the memory cell for writing "0" data becomes VM8 → Vss, the write operation is completed, and the write verify read operation (FIGS. 7 and 8).
Enter (4) inside. RDENB and address signal line ai
Does not change at all from the write operation to the write verify read operation, and the voltage of VPPRW and VNwell does not change. Therefore, the node N in the row decoder of FIG.
The voltages of 1, N2, N3 and N4 also do not change.

When the program verify read operation is started, first the bit line is charged as Vss → Vcc, then SG1D,
SG1D and CGiD (i = 1, 2, 4-8) are Vss → V
cc, CG3D is Vss → Vvrfy (however, Vss ≦ Vvrfy <V
cc), SG1, SG2, CG1, 2, 4-8
Changes from Vss to Vcc, and CG3 changes from Vss to Vvrfy. Then, the potential of the bit line connected to the memory cell for "1" data writing is V as the cell current does not flow in the corresponding NAND cell when writing to the memory cell is sufficient.
When the cc potential is maintained and the writing to the memory cell is insufficient, the cell current flows in the corresponding NAND cell, so that the bit line potential decreases. On the other hand, the bit line potential connected to the memory cell for writing "0" data is lowered because the cell current flows in the corresponding NAND cell. CG1, 2, 4-8, SG1, SG
After the potential of 2 is kept at Vcc and the potential of CG3 is kept at Vvrfy for a while, CG1 to 8, SG1 and SG2 are lowered to Vss potential, the bit line potential is subsequently detected, and read data is obtained.

When all the potentials of the bit lines connected to the memory cells for writing "1" data are determined to be "L" level, that is, the writing is sufficient for all the memory cells for writing "1" data. If so, the block selection cancel operation ((5) in FIGS. 7 and 8) is performed, and the write / write verify read operation is completed. Further, when it is determined that the potential of at least one of the bit lines connected to the memory cell for writing “1” data is “H” level, that is, at least one of the memory cells for writing “1” data is If there is a memory cell in which writing is insufficient, the operation of (3) → (4) in FIGS. 7 and 8 is performed again until writing is sufficient in all the memory cells in which “1” data is written. (3) → (4) → (3) → (4) →… → (3)
→ After repeating (4), (5) is performed, and the write / write verify read operation is completed.

FIG. 10 shows a flowchart of the write / write verify read operation described above. Here, steps S1 to S5 correspond to (1) to (5) in FIGS. The difference from the conventional FIG. 12 is that when at least one of the memory cells for writing “1” data has a memory cell for which writing is insufficient, the process returns to step S3 instead of step S2. Is. For this reason, the potential of the n-well of the row decoder is held at the boosted potential VppW even after the writing is completed, and the potential of the n-well is set to the power supply potential after it is determined that the writing of all the cells of "1" data writing is sufficient. Returning to Vcc. Next, the operation timing in the non-selected block will be described by taking the case where the third cell of the NAND cells is selected as an example.

During write / write verify read operation,
Since the node N1 is always at the Vss potential, the nodes N3 and N4 are always kept at Vcc and Vss, respectively. Therefore, the n-channel and p-channel MOS transistors connecting SG1D, SG1D, and CGiD (i = 1 to 8) and SG1, GS2, and CGi (i = 1 to 8) are always off. Further, since the n-channel MOS transistors connecting SG1 and SG2 to Vuss and the n-channel MOS transistors connecting CG1 to 8 and the ground potential are always on, SG1, SG2 and CG1-8 are always V
It is fixed at ss potential. However, VNwell and V
Since PPRW is shared with the selected block, it is at VppW potential during the operations of steps S3 and S4. Therefore, the capacity of the n-well shared by the non-selected block and the selected block is a main cause of increasing the time of τ1.

As described above, in this embodiment, VPPRW and VNwell are always operated during the operations of steps S3 and S4 in FIGS.
Is kept at the VppW potential, and therefore, even if the number of times of repeating steps S3 and S4 in FIG. 10 during the write / write verify read operation is large, VNwell and VPPR are
Since the operation to change W from Vcc to VppW can be entered only once,
Even if τ1 is long, the effect of τ1 on the time required for the entire write / write verify read operation is small, so the write / write verify read operation can be performed at high speed without increasing the current supply capability of the booster circuit, that is, without increasing the power consumption. Can be converted.

Further, at the time of operation of steps S3 and S4, V
Since only one CG3 in the selected block is charged using the booster circuit that generates ppW, it is not necessary to always maintain the supply capability of the booster circuit during the operation of step S2. Steps S3 and S4
Even if the supply capability of the booster circuit that generates VPPW during operation is reduced, the time required for the operations in steps S3 and S4 can be maintained to the same extent as when the capability is not reduced, and therefore, during the operations in steps S3 and S4. The power consumption can be kept small.

For comparison, timing charts of the conventional example shown in FIG. 12 are shown in FIGS. 13 and 14. Since the potential of the n-well is returned to Vcc at the end of step S3, it is not possible to return to step S3 even if it is determined that writing is insufficient after step S4, and it is returned to step S2. For this reason, the operation of changing VNwell or VPPRW from Vcc to VppW is repeated during the write / write verify read operation, which leads to an increase in the total time required for the write / write verify read operation and an increase in power consumption. .

Further, the case where the booster circuit of FIG. 9 is used to generate VPPW will be considered more concretely as an example. FIG. 11 is a diagram showing the timing of the input signal of the booster circuit.

Since it is not necessary to generate VPPW during the operations of steps S1 and S5, the input signal φp, /
φp is a constant potential, for example, φp = Vss, / φp
= Vcc (Fig. 11 (c)). Step S
Since a large load such as the n-well of the row decoder must be charged during the two operations, the oscillation cycle of φp, / φp is shortened to enhance the current supply capability of the booster circuit (see FIG. 11).
(B)). In this case, since the number of times of charging / discharging C1 to C5 in FIG. 9 per unit time is large, the power consumption becomes large.

Since only one CG3 needs to be charged during the operation of steps S3 and S4, the supply capability of the booster circuit does not have to be so high, and therefore, there is no problem even if the period of oscillation of φp, / φp is lengthened. No (FIG. 11 (b)). In this case, as compared with the case of FIG. 11A, the number of times of charging / discharging C1 to C5 in FIG. 9 per unit time is small, so that the power consumption is small. Furthermore, in the operations of steps S3 and S4, it is sufficient to maintain the potential of the portion at the VppW potential except during the operation of setting CG3 to VM10 → VppW. Can be reduced without any problem, and the power consumption can be further reduced.

As described above, the method of increasing the supply capability of the booster circuit at the time of charging and lowering the supply capability of the booster circuit at the time of maintaining the boosted voltage after charging to reduce the power consumption is V.
As well as the booster circuit that generates the ppW potential,
At the operation timing of (1), it is also effective in the booster circuit for generating the VM8 potential, and the power consumption can be greatly reduced. In this way, a booster circuit with a large charging load requires a high supply capacity during charging, and thus consumes a large amount of power. Therefore, it is very effective to reduce the supply capacity and reduce power consumption when maintaining a boosted voltage. Is.

Further, as described above, the power consumption of the booster circuit that generates VppW during the operations of steps S3 and S4 can be made smaller than that during the operation of step S2. You can Therefore, even if the power consumption of the booster circuit that generates the VM8 potential is increased by the same amount as the amount of decrease in the power consumption, the power consumption of the conventional operation is not exceeded, and the power consumption of the booster circuit is increased. The current supply capacity can be increased by the increased amount. Therefore, it is possible to shorten the time τ2 required to change the potential of the bit line connected to the memory cell for writing "0" data from Vcc to VM8. That is, the time required for the write / write verify read operation can be shortened. As can be seen from FIG. 10, this time reduction is more effective as the number of times the operations of steps S3 and S4 are repeated increases, and more time can be reduced. The present invention has been described above with reference to the operation timings of FIGS. 7 and 8. However, it goes without saying that the present invention is not limited to the above embodiment and various modifications can be made.

[0049]

As described above, according to the present invention, the write / write verify read operation can be speeded up without increasing the power consumption during the write / write verify read operation as compared with the prior art. Further, it becomes possible to reduce the power consumption at the time of write / write verify read as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a NAND cell type EE according to an embodiment of the present invention.
The block diagram which shows the basic composition of PROM.

FIG. 2 is a plan view and an equivalent circuit diagram showing a NAND cell configuration according to an embodiment.

FIG. 3 is a sectional view taken along line AA ′ and BB ′ of FIG.

FIG. 4 is an equivalent circuit diagram of the memory cell array in the embodiment.

FIG. 5 is a schematic diagram showing an arrangement of a memory cell array in the embodiment.

FIG. 6 is a circuit diagram showing a configuration of a row decoder unit in the embodiment.

FIG. 7 is a timing chart showing operations of data writing and write-verify reading.

FIG. 8 is a timing chart showing operations of data writing and write-verify reading.

FIG. 9 is a circuit diagram showing a configuration of a booster circuit that generates a high voltage.

FIG. 10 is a flowchart showing the operation of the embodiment.

FIG. 11 is a timing diagram of input signals of the booster circuit.

FIG. 12 is a flowchart showing the operation of a conventional example.

FIG. 13 is a timing chart showing operations of conventional data writing and write-verify reading.

FIG. 14 is a timing chart showing operations of conventional data writing and write verify reading.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Bit line control circuit, 3 ... Column decoder, 4 ... Address buffer, 5 ... Row decoder, 6 ... Data input / output buffer, 7 ... Substrate buffer circuit, 14 ... Floating gate, 15 ... Control gate, 18 ... bit line. 51 ... Enable circuit, 52 ... High voltage switching circuit, 53 ... Select gate and control gate drive circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location H01L 29/792 H01L 29/78 371 (72) Inventor Hideko Ohira Toshiba Komukai Toshiba, Kawasaki City, Kanagawa Prefecture Town No. 1 Toshiba Corporation Research Institute

Claims (5)

[Claims] 1. A memory cell array in which a charge storage layer and a control gate are laminated on a semiconductor substrate, and a memory cell is formed in which memory cells are electrically rewritten by transfer of charges between the charge storage layer and the substrate. A row decoder provided at one end or both ends in the word line direction of the cell array and including elements formed on a plurality of wells having a polarity opposite to that of the well in which the memory cell array is formed; and a memory within a predetermined range of the memory cell array. The unit has a unit write time and data is written at the same time. After that, the memory cell data is read, and if there is an insufficiently written memory cell, re-writing is performed. The voltage applied to at least one of the wells of opposite polarity is higher than a power supply voltage. Nonvolatile semiconductor memory device. 2. A memory cell array in which a charge storage layer and a control gate are laminated on a semiconductor substrate, and memory cells are formed in an array in which electric rewriting is performed by transfer of charges between the charge storage layer and the substrate. A row decoder that is provided at one end or both ends in the word line direction of the cell array and drives the control gate, and after simultaneously writing data by setting a unit write time to memory cells in a predetermined range of the memory cell array, Verify control means for reading the memory cell data and performing rewriting when there is a memory cell that has not been sufficiently written, and during the write verify operation, among the row decoders,
A nonvolatile semiconductor memory device characterized in that a voltage directly connected to a control gate of the memory cell and applied to a well having a transistor of a conductivity type opposite to that of the transistor of the memory cell is higher than a power supply voltage. 3. A memory cell array, wherein a plurality of memory cells are connected in series to form a NAND cell, and one end of the NAND cell is connected to a bit line through a select gate. 3. The voltage higher than the power supply voltage applied to the well of the row decoder is higher than the voltage applied to the select gate.
The non-volatile semiconductor memory device described in 1. 4. The voltage applied to a well to which a voltage higher than the power supply voltage is applied does not drop when changing from a data write operation to a write verify read operation. Nonvolatile semiconductor memory device. 5. A memory cell array in which a charge storage layer and a control gate are stacked on a semiconductor substrate, and in which memory cells to be electrically rewritten by exchanging charges between the charge storage layer and the substrate are arranged in an array, and the memory cell array. A row decoder provided at one end or both ends in the word line direction of the cell array and having a plurality of address input signals, and after simultaneously writing data by setting a unit write time in a predetermined range of memory cells of the memory cell array And verify control means for reading the memory cell data and rewriting when there is a memory cell that has not been sufficiently written, after the plurality of address input signals are set before the data write operation is started, A non-volatile semiconductor memory device characterized in that it does not change until a write verify operation is completed.