JPH06309883A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the occurrence of malfunctions at the time of reading out a nonvolatile semiconductor memory and to increase the writing speed to the memory by selectively adding a readout voltage clamped at a prescribed voltage or lower to the gate of a memory cell at the time of reading out data from the memory cell. CONSTITUTION:The connecting points of transistors (Tr) 13 and 13' for clamping potential which are connected to Trs 14 and 14' for selecting a bit line BL and dummy bit line DBL with resistors 12 and 12' are drawn out. The connecting points are respectively connected to both inputs of a differential sense amplifier 15 through a data line DL and dummy data line DDL. At the time of reading out data from a cell Tr 11, the Trs 13 and 13', upon the gates of which bias potentials are impressed, clamp the potentials at the lines BL and DBL. When the potentials are clamped, a readout control circuit 16 selectively applies a readout voltage Vc1 clamped at 4-5V across the gates of Trs 11 and 11'. Therefore, the occurrence of reading out malfunctions can be prevented and the operating power supply voltage range can be widened, and then, the writing speed can be increased, because a relation, Vin>Vref, is maintained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory mounted on a non-volatile memory integrated circuit or a logic type integrated circuit, and more particularly to a means for clamping a gate voltage of a non-volatile memory cell when reading the cell. .

[0002]

2. Description of the Related Art In nonvolatile semiconductor memories such as EPROM (UV erasable / rewritable ROM) and EEPROM (electrically erasable / rewritable ROM), a data memory is generally FLOTOX (Floating g).
ate Tunnel Oxide) type cell is composed of EEPROM, and program memory is EPROM or ETOX (EPRO).
Flash EE using Mwith Tunnel Oxide type cell
It is composed of PEOM.

Conventionally, when reading these nonvolatile memory cells, the gates of the cells are driven by a power supply voltage supplied from the outside of the integrated circuit chip. For this reason, when the write amount of the cell is smaller than the write amount sufficient to turn off the cell and the read power supply voltage is high, the gate voltage of the cell exceeds the threshold voltage of the cell and the cell is in the on state. And the cell current flows. Depending on the magnitude of this cell current, a sense amplifier for comparing the voltage input according to this cell current with a reference voltage to read out cell data is
An erroneous operation of reading data opposite to the cell data may occur.

On the other hand, in order to avoid the above-mentioned malfunction of reading, if the writing time is set long enough so that the writing amount of the cell is sufficient for the cell to be in the OFF state, high-speed writing becomes impossible. The problem of being possible arises.

[0005]

As described above, in the conventional nonvolatile semiconductor memory, since the gate of the cell is driven by the power supply voltage supplied from the outside of the integrated circuit chip, the nonvolatile memory cell is turned off. If the write amount is smaller than the sufficient write amount and the power supply voltage is high, the read malfunction occurs, and the write time is lengthened so that the write amount of the cell is sufficient to turn off the cell. There was a problem that high-speed writing would not be possible.

The present invention has been made in order to solve the above-mentioned problems, and causes a malfunction of reading when the write amount of a non-volatile memory cell is less than the write amount sufficient to turn off and the power supply voltage is high. It is an object of the present invention to provide a non-volatile semiconductor memory that can be prevented and can realize a wide operating power supply voltage range even if the cell write amount is small, and that enables high-speed writing.

[0007]

The nonvolatile semiconductor memory of the present invention is configured so that a read voltage clamped below a certain voltage can be selected as a voltage applied to the gate of the memory cell when reading the nonvolatile memory cell. It is characterized by having done.

Further, the nonvolatile semiconductor memory of the present invention is
When verifying after writing to a non-volatile memory cell, a power supply voltage supplied from the outside is applied as a read voltage to the gate of the memory cell for reading, and during normal reading, the read voltage clamped below a certain voltage is applied to the memory cell. It is characterized in that it is applied to the gate of and read out.

[0009]

When reading a non-volatile memory cell, a read voltage clamped to a certain voltage or lower can be applied to the gate of the memory cell to read, so that the write amount of the cell is sufficient to turn off. It is possible to prevent a malfunction of reading when the power supply voltage is less than the amount and the power supply voltage is high.

Therefore, a wide operating power supply voltage range can be realized even if the amount of cell writing is small, and high-speed writing is possible. Further, in the verification after writing performed by a normal general-purpose PROM writer, the power supply voltage supplied from the PROM writer is applied as a read voltage to the gate of the memory cell to read, and in a normal read, the voltage is lower than a certain voltage. It becomes possible to read by applying the clamped read voltage to the gate of the memory cell.

As a result, it is possible to secure a margin for the write amount of the cell and increase the margin for the charge retention characteristic of the write cell and the read margin when noise is added to the gate of the cell transistor in the off state. A more reliable non-volatile memory can be realized.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an EPR according to a first embodiment of the present invention.
A part of OM is shown schematically. Reference numeral 11 denotes a memory cell transistor, and a plurality of transistors are arranged in a matrix to form a memory cell array. The cell transistor 11 is composed of an NMOS transistor having a two-layer gate structure of a floating gate and a control gate.

BL is a bit line of the memory cell array, which is commonly connected to the drains of a plurality of cell transistors 11 in the same column of the memory cell array. The source of the cell transistor 11 is at ground potential (VSS).
It is connected to a node.

WL is a word line of the memory cell array, which is commonly connected to the control gates of a plurality of cell transistors 11 in the same row of the memory cell array. A load resistor 12, a bit line potential clamp NMOS transistor 13 and a bit line selection NMOS transistor 14 are connected in series between a VCC node to which a normal power supply potential VCC is applied and the bit line BL. ing.

The bit line potential clamping NMOS transistor 13 is for clamping the bit line potential at the time of reading, and its gate is supplied with the bias potential Vbias. The connection node between the bit line potential clamp transistor 13 and the resistor 12 is connected to one input node of the differential sense amplifier 15 via the data line DL.

A dummy circuit for supplying a comparison reference potential is connected to the other input node of the differential sense amplifier 15. This dummy circuit includes a dummy load resistor 12 ', a dummy bit line potential clamp NMOS transistor 13', a dummy bit line selection NMOS transistor 14 ', and a dummy bit line DBL between a VCC node and a VSS node. And dummy cell transistor 11 '
Are connected in series. The connection node between the dummy load resistor 12 'and the dummy bit line potential clamp transistor 13' is connected to the other input node of the differential sense amplifier 15 via the dummy data line DDL.

Further, when reading the cell transistor 11, the gate of the cell transistor (word line WL)
Also, as a voltage applied to the gate of the dummy cell (dummy word line DWL), the read control circuit 1 capable of selectively supplying the read voltage VCL clamped to a certain voltage or less.
6 is provided. The clamp voltage VCL is determined by the element characteristics of the cell transistor and is, for example, 4 to 5V.

FIGS. 2A and 2B show an example of operating characteristics when the clamp voltage VCL is applied to the gate of the cell transistor 11 shown in FIG. 1 during reading.
Here, VIN is the potential of the data line DL, VREF is the potential of the dummy data line DDL, Vtha is the initial value of the threshold voltage of the cell transistor, and Vthb is the threshold voltage after writing in the cell transistor.

From this figure, even when the cell write voltage is lower than the cell write voltage sufficient to turn off and the power supply voltage Vcc is high, the cell gate voltage VG exceeds the cell threshold voltage and the cell is turned on. Even if the cell is turned on and the cell current flows, the current is kept below the level at which the cell can be considered to be on, and the relationship of VIN> VREF can be maintained to prevent malfunction of reading. It can be prevented.

Therefore, a wide operating power supply voltage range can be realized even if the amount of cell writing is small, and high-speed writing becomes possible. FIG. 3 shows an example of a power supply clamp circuit provided in the read control circuit 16 for generating the clamp voltage VCL in the EPROM of the above embodiment.

This power supply clamp circuit is a depletion type (D) between the Vcc node and the clamp voltage output node.
Type) NMOS transistor 31 has a drain and a source inserted in series, and a bias voltage Vb is applied from a bias voltage generation circuit 32 to the gate thereof.

According to this circuit, VCL at the clamp voltage output node is the sum of the absolute value of the threshold voltage of the D-type transistor 31 and the bias voltage Vb. For example, when the threshold voltage of the D-type transistor 31 is -3.0V and Vb is 1V, VCL is 4V.

The bias voltage Vb is preferably constant without depending on Vcc, and an example of its configuration is shown in FIG. In the bias generation voltage circuit shown in FIG.
Is an enhancement-type (E-type) PMOS transistor, 42 is an E-type NMOS transistor, 43 is a D-type NMOS transistor, and 44 is an I-type NMOS transistor, and the standby control signal is at "H" level during standby.

FIG. 5 schematically shows a part of the precharge / discharge type EEPROM according to the second embodiment of the present invention. Compared with the EEPROM described above with reference to FIG. 1, this EEPROM has a load resistor 12,
Precharge PMOS transistor 5 in place of 12 '
1, 51 'are connected, and discharge NMOS transistors 52, 52' are inserted and connected between the source of the cell transistor 11 and the dummy cell 11 'and the VSS node, which is different in the configuration of the sense amplifier 15a.

The gates of the precharge PMOS transistors 51 and 51 'and the discharge NMOS transistors 52 and 52' are connected to the precharge signal /
PR is given.

Further, the sense amplifier 15a is configured such that one input terminal of each of the two two-input NOR gates is cross-connected to the other output terminal. Further, in the EPROM described above,
A read control circuit 16 capable of selectively supplying the clamp voltage VCL to the word line WL and the dummy word line DWL when reading the cell transistor is provided.

FIG. 6 shows an example of operating characteristics of the cell transistor and dummy cell of the circuit of FIG. FIG. 7 shows FIG.
6 is a waveform chart showing an example of a data read operation of the circuit of FIG.

Next, the data read operation of the cell transistor in FIG. 5 will be described with reference to FIGS. 6 and 7. While the precharge signal / PR is at the "L" level (precharge period), the precharge PMOS transistors 51 and 51 'are turned on, and the data line DL and the dummy data line DDL are precharged to Vcc. During the discharge period after the end of the precharge period, VIN and VREF change according to the read current of the cell transistor 11 and the read current of the dummy cell 11 ′ whose clamp voltage VCL is applied to the gate.

In this case, when the cell write amount is sufficient, VREF falls below the threshold voltage of the NOR gate of the sense amplifier 15a earlier than VIN, and the sense amplifier output voltage Vou
t remains "L".

Even when the cell write amount is smaller than the cell write amount sufficient to turn off and the power supply voltage Vcc is high, the cell gate voltage exceeds the cell threshold voltage and the cell is turned on. Even if the cell current flows in the on-state even if the cell is turned on, the current is suppressed to be equal to or lower than the current at which the cell is considered to be on-state, and VIN is lower than the threshold voltage of the NOR gate of the sense amplifier 15a earlier than VREF. It is possible to prevent the malfunction of reading.

Therefore, a wide operating power supply voltage range can be realized even if the cell writing amount is small, and high-speed writing becomes possible. By the way, when the cell gate voltage is clamped to a certain voltage or less for reading as in each of the above-described embodiments, reading can be performed with a small writing amount, but
There is a risk that the margin for the charge retention characteristic (retention) of the write cell and the read margin when noise is applied to the gate of the cell transistor in the OFF state to which the clamp voltage is applied may be reduced.

FIG. 8 shows an example of the block configuration of the EEPROM according to the third embodiment of the present invention, which is provided with such measures for reducing the margin. In FIG. 8, 61 and 62 are 2
The divided memory cell arrays 63 and 64 are row decoders which are provided corresponding to the above two memory cell arrays and select a row of the memory cell array. It has low level shifters (low level switching circuit portions) 63a and 64a for switching to.

Reference numerals 65 and 66 are provided corresponding to the above two memory cell arrays, column selectors for selecting columns of the memory cell array, 67 and 68 are column decoders provided corresponding to the above two column selectors,
Reference numeral 69 is a sense amplifier provided commonly to the two memory cell arrays.

Reference numeral 70 is a power supply clamp circuit as shown in FIG. 3, and 71 is a high voltage detection circuit for detecting a high voltage Vpp input from the outside and outputting a high voltage detection signal SVPP.
The power supply switching circuit 72 outputs the output voltage VCL of the power supply clamp circuit 70 and a normal power supply voltage supplied from the outside according to the memory operation mode specified by the program signal PGM input from the outside and the high potential detection signal SVPP. Vcc and the high voltage Vpp are switched and output, and are supplied as operating power supplies for the row level shifters 63a and 64a of the row decoder.

FIG. 9 shows a specific circuit example of FIG. Here, 11 is a cell transistor, 13 is a bit line potential clamp transistor, 14 is a bit line selection transistor, 11 'is a dummy cell transistor, 13' is a dummy bit line potential clamp transistor, and 14 'is a dummy bit line. Selection transistors, 51 and 51 'are precharge transistors, and 52 and 52' are discharge transistors. Also, P1 to P are P
N1 is an NMOS transistor whose gate is supplied with the clamp voltage VCL.

In the circuit of FIG. 9, at the time of writing, the program signal PGM is at "H" level, the high voltage Vpp is applied from the outside, the high potential detection signal SVPP is at "H" level, and the transistor P1, Since P2 and P4 are turned on and P3 and P5 are turned off, Vpp is supplied to the low level shifters 63a and 64a.

For verification, the program signal PGM becomes "L" level, the high potential detection signal SVPP becomes "H" level, the transistors P1, P2, P5 are turned off, P3,
Since P4 turns on, Vcc changes to low level shifter 63.
a, 64a.

At the time of reading, the program signal PGM becomes "L" level, the high potential detection signal SVPP becomes "L" level, the transistors P1, P2, P3 and P4 are turned off.
Since P5 is turned on, VCL goes low level shifter 63
a, 64a.

In the EEPROM of the third embodiment described above, in the write / verify / read sequence as shown in FIG. 10 by a general-purpose PROM writer, at the time of verify immediately after writing, the power supply voltage Vcc supplied from the writer is used as the read voltage. It is possible to apply the clamp voltage VCL to the gate of the memory cell and read it when applying the read to the gate of the memory cell and performing the normal read to the memory cell.

By such control, as shown in FIG. 11, by applying VCL to the gate of the cell and applying a minimum write amount ΔVthc for reading as an off-state cell, and applying VCC to the gate of the cell. When the minimum required write amount for reading as an off-state cell is represented by ΔVthv, ΔVthc <ΔVthv is always satisfied, and the difference ΔVthm.
It becomes possible to secure the write margin by (= ΔVthv−ΔVthc).

That is, in the past, in order to secure a write margin, a high voltage as a read voltage was applied to the gate of the memory cell at the time of verification immediately after writing, but this is no longer necessary.

FIG. 12 shows another example of the power supply clamp circuit of FIG. This power supply clamp circuit is different from the power supply clamp circuit shown in FIG. 3 in that it is connected to the output node of the booster circuit 81 instead of the VCC node.

By connecting the power supply clamp circuit to the output node of the booster circuit 81 as described above, the clamp voltage V
Since a voltage higher than the power supply voltage Vcc can be applied to the gate of the cell transistor below CL, it is possible to turn on the cell transistor and read it as an on-state cell transistor even with a low power supply voltage Vcc below the threshold voltage Vth of the erased cell transistor. It will be possible. Also, the low power supply voltage V
Even in CC, the current of the cell transistor increases, which enables faster reading.

In this case, even if the booster circuit 81 is used,
Since the gate voltage of the cell transistor does not exceed the clamp voltage VCL, the cell transistor in the written state is not accidentally turned on and read.

[0045]

As described above, according to the nonvolatile semiconductor memory of the present invention, a read malfunction occurs when the power supply voltage is high even if the write amount is smaller than the write amount sufficient for turning off the memory cell. It is possible to prevent this, a wide operating power supply voltage range can be realized even if the amount of cell writing is small, and high-speed writing can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of an EPROM according to a first embodiment of the present invention.

2 is a timing waveform chart showing an example of a read operation of a cell transistor in FIG.

FIG. 3 is a circuit diagram showing an example of a power supply clamp circuit in FIG.

4 is a circuit diagram showing an example of a bias voltage generation circuit in FIG.

FIG. 5 is a circuit diagram showing a part of an EPROM according to a second embodiment of the present invention.

6 is a timing waveform diagram showing an example of a read operation of the cell transistor in FIG.

7 is a waveform diagram showing an example of a data read operation of the circuit of FIG.

FIG. 8 is a block diagram showing an example of a circuit configuration of an EPROM according to a third embodiment of the present invention.

9 is a circuit diagram showing a specific example of the block configuration of FIG.

FIG. 10 is a diagram showing how a gate applied voltage of a cell transistor is switched in a write / verify / read sequence by a general-purpose PROM writer.

FIG. 11 is a timing waveform chart showing an example of operating characteristics of cell transistors in the EPROMs of FIGS. 8 and 9.

12 is a circuit diagram showing another example of the power supply clamp circuit of FIG.

[Explanation of symbols]

11 ... Cell transistor, 13 ... Bit line potential clamp transistor, 14 ... Bit line selection transistor,
BL ... bit line, WL ... word line, DL ... data line, 1
1 '... Dummy cell transistor, 13' ... Dummy bit line potential clamp transistor, 14 '... Dummy bit line selection transistor, DBL ... Dummy bit line, D
WL ... dummy word line, DDL ... dummy data line, 15
a ... Sense amplifier, 16 ... Read control circuit, 51, 5
1 '... precharge transistor, 52, 52' ... discharge transistor.

Claims (5)

[Claims] 1. A non-volatile memory cell array, and a read control circuit capable of selectively supplying a read voltage clamped below a certain voltage as a voltage applied to the gate of the memory cell in reading the memory cell of the memory cell array. A non-volatile semiconductor memory characterized by comprising. 2. The non-volatile semiconductor memory according to claim 1, wherein a row decoder for selecting a row of the memory cell array and a read voltage generated by clamping a normal power supply voltage supplied from outside to a certain voltage or less are generated. A non-volatile semiconductor memory, further comprising a power supply clamp circuit that supplies power as an operating power supply for the level shifter of the row decoder. 3. A non-volatile memory cell array and a verify after writing to a memory cell of the memory cell array are performed by applying a power supply voltage supplied from the outside as a read voltage to a gate of the memory cell to read the memory cell. A non-volatile semiconductor memory, comprising a read control circuit for applying a read voltage clamped to a certain voltage or less to a gate of a memory cell to read during normal read. 4. The nonvolatile semiconductor memory according to claim 3, wherein a row decoder for selecting a row of the memory cell array and a power supply for generating a read voltage by clamping a normal power supply voltage supplied from the outside to a certain voltage or less. A clamp circuit, a high voltage detection circuit that detects a high voltage input from the outside and outputs a high voltage detection signal, a program signal input from the outside, and a memory operation mode specified by the high potential detection signal And a power supply switching circuit for switching and outputting the output voltage of the power supply clamp circuit, a normal power supply voltage supplied from the outside, and a high voltage, and supplying the same as an operating power supply of the level shifter of the row decoder. Semiconductor memory. 5. The non-volatile semiconductor memory according to claim 2, further comprising a booster circuit connected as a power supply of the power supply clamp circuit.