JPS6129496A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make a chip size smaller in an ROM by employing a depression- type MOSFET having a small-sized FET and minimal conductive resistance value as a MOSFET for shorting across respective input lines of differential sensor amplifiers. CONSTITUTION:A potential of a column line 16 is set in accordance with data read-out from a cell 11 in a memory cell array 10, level-shifted to a potential V1, and supplied to one signal input line 23 of a differential sensor amplifier 22. A comparison potential generator circuit 24 supplies a comparison potential V2 to a signal input line 26 of the amplifier 22 with use of a dummy memory cell 25 for consisting of MOSFETs similar to the cell 11. The data detecting action of the amplifier 22 is controlled by a pair of control signals CE. In this case a depression-type MOSFET37 is provided in order to short across the lines 23 and 26 according to a pulse signal phi. Thus, when a speed at setting the lines 23 and 26 to the same potential is approximately equal to the conventional one, the FET37 can be sufficiently scaled down compared with an enhancement MOS FET.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data read-only semiconductor memory device equipped with a differential sense amplifier.

[Technical Background of the Invention] In general, differential sense amplifiers are often used in semiconductor storage devices (hereinafter referred to as memories) because their operation is stable and they can detect extremely small potential differences.

By the way, R that can read and write data
In an AM (random access type memory) or the like, a pair of data having mutually opposite levels is output as memory data. For this reason, this pair of data is led to a pair of signal input lines of a differential sense amplifier for data detection. However, in the case of ROM (data read-only memory), 1"
Or, since the data of either one of 110 I+ is not output, a comparison potential is prepared using a dummy memory cell transistor equivalent to the memory cell as a sense amplifier used in the ROM, and this potential is used as the column line potential. The signal is also supplied to a sense amplifier for data detection.

FIG. 2 is a circuit diagram showing the structure of a conventional mask ROM using, for example, an N-channel insulated gate field effect transistor (hereinafter referred to as MO8l-transistor). In the figure, 10 is a memory cell array, 11 is a memory cell consisting of a MOS transistor provided in the memory cell array 10 and stores data depending on the level of the threshold voltage, 12 is a MOS transistor for column selection, and 13 is a row 14 is a column decoder, 15 is a row line 16 is a column line, 17 to 19 are MOS transistors for loads, and 20 and 21 are resistors for generating bias voltage.

The potential of the column line 16 is set according to the data read from the memory cell 11 in the memory cell array 10, and the column line potential 1 is level-shifted to potential 1 by the transistor 19, and the differential sense amplifier 22 is supplied to one signal input line 23 of.

Reference numeral 24 denotes a comparison potential generation circuit, which includes a dummy memory cell 2 made of a MOS transistor similar to the memory cell 11.
5 to the other signal input line 2 of the sense amplifier 22.
It generates the comparison potential ■2 to be supplied to 6, and 2
7.28 is a bias generating resistor similar to the resistor 20.21, and 29 is a MoS whose gate is supplied with a 111 I+ level signal and is always on, equivalent to the column selection MOS transistor 12. transistor, 30
32 to 32 are Mo8 transistors equivalent to the load MOS transistors 17 to 19;
This is a bias resistor that supplies a constant bias potential at an intermediate level.

Control signals CE and σT are supplied to the sense amplifier 22, and the data detection operation in the sense amplifier 22 is controlled by these signals.

The data detected by the sense amplifier 22 is output as output data D via the output buffer 1 circuit 35.

Note that the load transistors 17 to 19 and 30
Of the transistors 19 to 32, only transistors 19 and 32 are of the depletion type.

Further, the signal input line 23 of the differential sense amplifier 22,
An enhancement type Mo8)-transistor 3G for short-circuiting between the signal input lines 23 and 2f3 whose gates are supplied with the pulse signal φ is inserted between them.

In such a ROM, as shown in the timing chart of FIG. 3, when the row address signal or column address signal changes, a pulse signal φ of the "1" level is generated by a pulse generation circuit (not shown). . This pulse signal φ is supplied to the gate of an enhancement type MOS transistor 36 for shorting the signal input lines 23 and 26, thereby turning on the transistor 36 and shorting the signal input lines 23 and 26. be done. Here, when the address signal is in a state before changing, as shown in the potential state diagram of FIG.
Assume that the potential (2) of the signal input line 26 is set to a potential close to the power supply potential Vc, for example, and the potential (2) of the other signal input line 26 is set to an intermediate potential between the power supply potential Vc and the ground potential. When the signal input lines 23 and 26 are short-circuited in this state, the potentials of the signal input lines 23 and 26 are set by the transistor 36 to be between the potentials 1 and 2, as shown by 3 in FIG. set to potential.

When the pulse signal φ is set to the "0" level after a predetermined period has elapsed, the transistor 36 is turned off and the short circuit between the signal input lines 23 and 26 is released. Line 15 is selected and any column line 16
is selected, one memory cell 11 is selected, and depending on the data stored in the selected memory cell 11, the potential V3 of one signal input line 23 moves toward the potential V1 or the ground potential. and the other signal input line 2
6 changes toward the original potential V2.

For example, if the threshold voltage of the memory cell 11 selected in the memory cell array 10 is high, the memory cell will not turn on even in the selected state, and the column line 16 will remain charged to a high potential. Therefore, one input potential of the sense amplifier 22 changes from 3 toward Vl, and is finally set to Vl. On the other hand, if the threshold voltage of the selected memory cell 11 is low, when it is selected, the memory cell is turned on and the column line 16 is discharged to the ground potential via this memory cell. One input potential of the sense amplifier 22 changes toward the ground potential from (3), and is finally set near the ground potential. At this time, the sense amplifier 22 connects the signal input lines 23 and 26
Data is detected based on the potential difference that occurs between the two.

In this ROM, the transistor 36 is switched and controlled by the pulse signal φ to switch the differential sense amplifier 2.
The data read speed is increased by short-circuiting both signal input lines 23 and 26 and setting them to the same potential.

[Problems with Background Art] By the way, in the above ROM, the differential sense amplifier 2
Transistor 3 short-circuiting both signal input lines 23.2G of 2
Since we are using an enhancement type transistor as the transistor 36, in order to set both signal input lines 23.2G to the same potential in a short period of time, we need to use a large transistor 36 and increase the value of its conduction resistance. needs to be sufficiently small. Since such a ROM is usually integrated on one chip, as the size of the transistor 36 increases, the overall chip size also increases, resulting in an increase in manufacturing cost.

Further, the potential of the column line 16 is changed to the power supply potential Vc by the transistor 19.
Since the level of the pulse signal φ to be supplied to the gate of the transistor 36 must be increased above the power supply potential Vc, an extra voltage boosting circuit is required. This also has the disadvantage that the overall chip size becomes larger.

[Object of the Invention] The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to provide a semiconductor memory device that can reduce the chip size when integrated and can be manufactured at low cost. It is about providing.

[Summary of the Invention] In order to achieve the above object, the present invention provides a MOS transistor for short-circuiting between one signal input line and the other signal input line of a differential sense amplifier, even if the transistor size is small. By using a depression-type device with a small size, the chip size for integration can be reduced.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a semiconductor memory device according to the present invention implemented in a ROM in the same manner as in the prior art.

The difference between this embodiment circuit and the conventional circuit shown in FIG. 2 is that the signal input of the differential sense amplifier 22 is
A depletion type MOS transistor 37 is used as a short-circuiting MOS transistor inserted between the signal input lines 23 and 26 and short-circuiting the signal input lines 23 and 26 in response to the pulse signal φ.

By the way, the value of the current flowing between the source and drain of a MOS transistor is proportional to VG-Vth. However, VG
is the gate voltage and vth is the threshold voltage. Here, if the threshold voltage of the depletion type MOS transistor is VthD1 and the threshold voltage of the enhancement type MOS t-transistor is VthE, generally VthE>VthD ・1, so VG-Vth, D>VG-VthE. -2, and if the transistor size is the same, it is an enhancement type MO
The S transistor has a smaller conduction resistance under the same gate voltage. Therefore, the differential sense amplifier 22
When setting the signal input lines 23 and 26 to the same potential at the same speed as the conventional one, the MO
The size of the S transistor 37 can be made sufficiently smaller than the transistor 36 of the conventional circuit, so that the chip size for integration can be reduced.

On the other hand, if the transistor size of the transistor 37 in the above embodiment is set to be approximately the same as that of the transistor 36 of the conventional circuit, the speed at which the signal input lines 23 and 26 are set to the same potential can be made shorter than that of the conventional circuit. This means that the period during which the pulse signal φ is at the "1" level can be shortened, and thereby the data read speed can be increased.

Furthermore, since the threshold voltage Vt hD of the depletion type MoS transistor is a negative polarity value, the pulse signal φ
The resistance value can be made sufficiently low without boosting the ``1'' level voltage above the power supply voltage Vc.Therefore, there is no need for an extra voltage boosting circuit as in the past, and integration The chip size can be made smaller.

Furthermore, the signal input line 23°2 of the differential sense amplifier 22
If the following conditions are satisfied between the potentials V1 and 2 of Mo8 transistor 6 and the threshold voltage VthD of Mo8 transistor 37, this MoS transistor 37 is activated when pulse signal φ is at the "O" level. It can be set to the off state, and the signal input lines 23 and 26 can be isolated.

Vl > IVthDl, V2 > l VthDl...
3 Conditions such as the above-mentioned equation 3 are fully satisfied in a normal depression type.

It goes without saying that this invention is not limited to the above-mentioned embodiments, and that various modifications are possible.For example, in the above-mentioned embodiments, the case where this invention is implemented in a mask ROM has been explained, but this invention is not limited to the above-mentioned embodiments. According to this, an MOS for short-circuiting between one and the other signal input lines of a differential sense amplifier can be implemented in EPROM, etc.
! - Since a depletion type transistor with a small conduction resistance value is used even if the transistor size is small, the chip size for integration can be reduced and manufacturing can be done at low cost.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the structure of an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing the structure of a conventional ROM, and FIG. 3 is a circuit diagram showing the structure of a conventional ROM. The timing chart in FIG. 4 is a potential state diagram for explaining the operation of a conventional ROM. 10... memory cell array, 11... memory cell,
12... MOS transistor for column selection, 13...
Row decoder, 14... Column decoder, 15... Row line,
16... Column line, 17-19° 30-32... MOS transistor for load, 20.21° 27, 28...
Resistor for bias voltage generation, 22... Differential sense amplifier, 23.26... Signal input line, 24... Comparison potential generation circuit, 25... Dummy memory cell, 33.34
...Bias resistance. 37... Enhancement type MOS +- transistor for short circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] differential data detection means having first and second input lines and detecting data by comparing the potentials of both input lines;
first and second load transistors coupled to the first and second input lines, respectively; and selectively driven according to an input address signal and connected to the first input line according to pre-stored data. a memory cell for setting the potential of the line;
a dummy memory cell that sets the potential of the input line to a reference potential, and a depression type MOS that is inserted between the first and second input lines and whose switch is controlled by a pulse signal.
A semiconductor memory device comprising a transistor.