KR100364421B1 - Circuit for driving sense amplifier - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier driving circuit. In the prior art, when a sense amplifier operates in an overdriving section, a current increases rapidly in the sense amplifier driving line. By generating a voltage drop, the level of the overdriving voltage is lowered, resulting in a decrease in the sensing speed of the sense amplifier. Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and outputs the enable signals SP1_CLP, SPB1, SPB2, and SN by the sense amplifier enable signal SAEN to perform the overall operation of the sense amplifier. A sense amplifier controller for controlling; An overdriving control unit controlled by the substrate voltage enable signal VPPOK and the overdriving enable signal SPI_CLP to adjust a level so that the overdriving control signal VCLPG has a predetermined value; An overdriving voltage generator for conducting control by the overdriving control signal VCLPG and outputting a power supply voltage VDD as an overdriving voltage VDDCLP; The sensor is controlled by the output (SPB1, SPB2, SN) of the sense amplifier control unit to provide a device consisting of a sense amplifier driver for applying a driving voltage (VDL) and ground voltage (VSS) to each sense amplifier, In order to prevent the overdriving voltage from occurring in the sense amplifier driving line during the overdriving operation, a simple additional circuit is added, and the gate voltage of the transistor outputting the overdriving voltage is increased to a predetermined level to improve its driving ability. By improving, the sensing speed of the sense amplifier can be improved while reducing the degree of integration in layout design.

Description

Sense amplifier driving circuit {CIRCUIT FOR DRIVING SENSE AMPLIFIER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier, and more particularly to a transistor that generates an overdriving voltage by adding a simple additional circuit to prevent an overdriving voltage from occurring on the sense amplifier drive line when the sense amplifier is overdriving. It relates to a sense amplifier driving circuit for increasing the gate voltage to a predetermined level to improve its driving ability.

FIG. 1 is a block diagram showing the structure of a conventional sense amplifier driving circuit. As shown in FIG. 1, each of the signals SPB1, SPB2, and SN is output by the sense amplifier enable signal SAEN, and thus, the sense amplifiers 3a and 3b. A sense amplifier controller 4 for controlling the overall operation of the sensor; An overdriving voltage generator 1 for conducting control by the substrate voltage VPP and outputting a power supply voltage VDD as an overdriving voltage VDDCLP; It is controlled by the outputs SPB1, SPB2 and SN of the sense amplifier control unit 4 so that the overdriving voltage VDDCLP, the driving voltage VDL, and the sense amplifiers 3a and 3b in the sense amplifier unit 3 are controlled. An operation of a conventional device configured of the sense amplifier driver 2 for applying the ground voltage VSS will be described with reference to the accompanying drawings.

When the chip is powered up, the overdriving voltage generation unit 1 is electrically controlled by the substrate voltage VPP applied to the gate of the NMOS transistor NM1 to overdrive the power supply voltage VDD. Output to (VDDCLP) to supply stable power.

As shown in FIG. 2A, when the sense amplifier enable signal SAEN is "active" at a high potential, the sense amplifier unit 3 composed of a plurality of sense amplifiers 3a and 3b is a bit line pair BL0. Data of each cell (not shown) is sensed through ˜BLn and BLB0 to BLBn, wherein the sense amplifier control unit 4 also receives the sense amplifier enable signal SAEN and receives the bit line pairs BL0 to BLn, respectively. The enable signals SPB1, SPB2, and SN are output when a predetermined time elapses after the BLB0 to BLBn starts to develop.

That is, as shown in (b) of FIG. 2, the first pull-up enable signal SPB1 is applied to the pull-up transistor PM1 for pull-up at low potential and conducts it, and pull-down as shown in FIG. The enable signal SN is applied to the pull-down NMOS transistor NM2 at " high potential "

Meanwhile, the pull-up transistor PM2 for pull-up is conducted by the second pull-up enable signal SPB2 having a "low potential" to apply the sense amplifier driving voltage VDL to the sense amplifier drive line CSP, The ground voltage VSS is applied to the sense amplifier driving line CSN by the pull-down enMOS transistor NM2.

Then, a predetermined time when the overdriving voltage VDDCLP of the overdriving voltage generation unit 1 becomes the first low-up enable signal SPB1 through the conducting pull-up MOS transistor PM1 becomes "low potential". While driving the sense amplifier section (3).

In the state where the pull-up PMOS transistor PM1 and the pull-down EnMOS transistor NM2 are conducted, the sense amplifier unit 3 senses data carried on the bit line pairs BL0 to BLn and BLB0 to BLBn. .

After that, when the predetermined time passes, the first pull-up enable signal SPB1 becomes "high potential", and at the same time, the second pull-up enable signal SPB2 becomes "high potential" as shown in FIG. Each of the pull-up MOS transistors PM1 and PM2 is turned off to complete the sensing operation.

In this case, a section in which the first pull-up enable signal SPB1 is "low potential" is called an overdriving section, and the overdriving voltage VDDCLP of the section is higher than the sense amplifier driving voltage VDL. Therefore, the sense amplifiers 3a and 3b perform high-speed sensing during the overdrive period.

However, in the conventional technology as described above, when the sense amplifier operates in the overdriving period, the current rapidly increases in the sense amplifier driving line. As the current passes through the transistor, the voltage drops to the overdriving voltage. ), The level of the overdriving voltage is lowered and the sensing speed of the sense amplifier is lowered.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and a simple additional circuit is added to prevent a drop in the overdriving voltage generated in the sense amplifier driving line when the sense amplifier is overdriving. It is an object of the present invention to provide a sense amplifier driving circuit which improves its driving capability by raising the gate voltage of a transistor that generates an overdriving voltage to a predetermined level.

1 is a block diagram showing the configuration of a conventional sense amplifier driving circuit.

Figure 2 is a waveform diagram showing the waveform of each signal in Figure 1;

3 is a waveform diagram showing waveforms of a sense amplifier drive line and a bit line pair when a voltage drop occurs during an overdriving operation;

4 is a block diagram showing the configuration of the sense amplifier driving circuit of the present invention;

FIG. 5 is a circuit diagram of an overdriving control unit in FIG. 4; FIG.

FIG. 6 is a waveform diagram showing the waveform of each signal in FIG. 4; FIG.

Fig. 7 is a waveform diagram showing waveforms of a sense amplifier drive line and a bit line pair after improving the occurrence of voltage drop during an overdriving operation.

*** Description of the symbols for the main parts of the drawings ***

10: overdriving voltage generator 20: sense amplifier driver

30: sense amplifier section 30a, 30b: sense amplifier

40: sense amplifier control unit 50: overdriving control unit

AD: and gate C: capacitor

NM1: NMOS transistor NM2: NMOS transistor for pulldown

PM1, PM2: PMOS transistor for pull-up PM3: PMOS transistor for control

PM4, PM5: PMOS transistor SW: Switch

According to an aspect of the present invention, there is provided a sensing amplifier controller configured to control an overall operation of a sense amplifier by outputting enable signals SPI_CLP, SPB1, SPB2, and SN by a sense amplifier enable signal SAEN; An overdriving controller controlled by a substrate voltage enable signal VPPOK and an overdriving enable signal SPI_CLP that is an output of the sense amplifier controller to adjust a level such that the overdriving control signal VCLPG has a predetermined value; An overdriving voltage generator for conducting control by the overdriving control signal VCLPG and outputting a power supply voltage VDD as an overdriving voltage VDDCLP; And a sense amplifier driver controlled by the outputs SPB1, SPB2, and SN of the sense amplifier controller to apply the overdriving voltage VDDCLP, the driving voltage VDL, and the ground voltage VSS to the respective sense amplifiers. It is characterized by.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a block diagram showing the configuration of the sense amplifier driving circuit of the present invention. As shown in FIG. 4, each signal SP1_CLP, SPB1, SPB2, SN is output by the sense amplifier enable signal SAEN, and the sense amplifier 30a is output. A sense amplifier controller 40 for controlling the overall operation of the controller 30b; An overdriving control unit which is controlled by a substrate voltage enable signal VPPOK and an overdriving enable signal SP1_CLP that is an output of the sense amplifier control unit 40 to adjust a level so that the overdriving control signal VCLPG has a predetermined value. 50; An overdriving voltage generator (10) for conducting control by the overdriving control signal (VCLPG) to output a power supply voltage (VDD) as an overdriving voltage (VDDCLP); It is controlled by the outputs SPB1, SPB2, and SN of the sense amplifier control unit 40 so that the overdriving voltage VDDCLP, the driving voltage VDL, and the sense amplifiers 30a and 30b in the sense amplifier unit 30 are controlled. The sense amplifier driver 20 applies a ground voltage VSS.

As shown in FIG. 5, the overdriving control unit 50 receives the substrate voltage enable signal VPPOK on one input and the overdrive enable signal SPI_CLP on the other input. )Wow; A controlled PMOS transistor (PM3) for receiving a substrate voltage (VPP) from a source and an output of the AND gate (AD) from a gate; A PMOS transistor PM4 having a source and a drain applied to the substrate voltage VPP in common; A switch (SW) having one side connected to a source of the PMOS transistor PM4 and the other side connected to a drain of the PMOS transistor PM4; A PMOS transistor (PM5) having a source and a drain connected in common to the drain of the PMOS transistor (PM4); An overdriving enable signal SPI_CLP is applied to one side and a capacitor C connected to the drain of the PMOS transistor PM5 on the other side. The operation and action of the embodiment according to the present invention configured as described above are attached. It will be described in detail with reference to one drawing.

When the sense amplifier enable signal SAEN is " active " at a high potential, the sense amplifier unit 30 composed of a plurality of sense amplifiers 3a and 3b is configured to convert the bit line pairs BL0 to BLn and BLB0 to BLBn. Data of each cell (not shown) is sensed through this, and the sense amplifier control unit 40 also receives the sense amplifier enable signal SAEN to develop the bit line pairs BL0 to BLn and BLB0 to BLBn. After a predetermined time elapses after the start of operation, the enable signals SPB1, SPB2, and SN are output.

That is, the first pull-up enable signal SPB1 is applied to the pull-up PMOS transistor PM1 at the "low potential" and conducts it, and the pull-down enable signal SN is "high potential" and the pull-down enMOS transistor is pulled down. Is applied to (NM2) to conduct it.

At this time, the pull-up PMOS transistor PM2 is turned on by the second pull-up enable signal SPB2 having a "low potential" to apply the sense amplifier driving voltage VDL to the sense amplifier drive line CSP. The ground voltage VSS is applied to the sense amplifier driving line CSN by the pull-down enMOS transistor NM2.

Then, a predetermined time when the overdriving voltage VDDCLP of the overdriving voltage generator 10 becomes the first low-up enable signal SPB1 through the conducting pull-up MOS transistor PM1 becomes a "low potential". While driving the sense amplifier unit 30.

In addition, the sense amplifier unit 30 senses data carried on the bit line pairs BL0 to BLn and BLB0 to BLBn while the pull-up PMOS transistor PM1 and the pull-down EnMOS transistor NM2 are conducted. .

On the other hand, when the chip is powered up, the NMOS transistor NM1, which is the overdriving voltage generator 10, is electrically controlled by the overdriving control signal VCLPG to overpower the power supply voltage VDD. The sensing amplifier unit 30 performs a high-speed sensing during the overdriving period by the overdriving voltage VDDCLP having a level higher than that of the sense amplifier driving voltage VDL.

In addition, the overdriving voltage generator 10 adjusts the gate voltage of the NMOS transistor NM1 by the overdriving control signal VCLPG output from the overdriving controller 50, thereby controlling the PMOS transistor PM1. The amount of current flowing through the sense amplifier driving line CSP is adjusted, and the overdriving controller 50 determines whether the substrate voltage enable signal VPPOK and the overdriving section are output when the substrate voltage VPP reaches a predetermined level. Controlled by the overdriving enable signal SPI_CLP to indicate the level of the overdriving control signal VCLPG selectively.

Here, referring to the operation of the overdriving controller 50, when the substrate voltage VPP reaches a predetermined level as shown in FIG. 6A, the power generating unit (not shown) as shown in FIG. 6B is illustrated. The substrate voltage enable signal VPPOK is output at " high potential. &Quot;

At this time, since the overdriving enable signal SPI_CLP maintains the "low potential" because it is not an overdriving section, the low potential is output from the AND gate AD so that the controlling PMOS transistor PM3 is turned on and the capacitor C is turned on. ) Is charged to the substrate voltage VPP, so that the overdriving control signal VCLPG becomes the level of the substrate voltage VPP and is applied to the gate of the nMOS transistor NM1 that is the overdriving voltage generator 10. .

Thereafter, when sensing is started by the sense amplifier unit 30, the sense amplifier controller 40 outputs the overdriving enable signal SPI_CLP at high voltage to overdriving as shown in FIG. 6D. do.

Then, the high potential is output from the AND gate AD during the period in which the overdriving enable signal SPI_CLP is “high potential,” so that the controlling PMOS transistor PM3 is turned off and is connected to the substrate voltage VPP. The level of the overdriving control signal VCLPG increases due to the coupling of the capacitor C that has been charged.

At this time, the level of the overdriving control signal VCLPG rises by the voltage Vt induced by each of the PMOS transistors PM4 and PM5 as shown in FIG. 6E, and the overdriving control signal VCLPG When the switch SW is controlled according to the control of the user or the microcomputer to prevent the level of the signal from excessively rising, the level of the overdriving control signal VCLPG becomes VPP + Vt or VPP + 2Vt.

When the overdriving enable signal SPI_CLP becomes "low potential" and the overdriving section ends, the controlling PMOS transistor PM3 is turned on again, and the level of the overdriving control signal VCLPG is reset again. (VPP).

That is, during the overdriving period, the level of the overdriving control signal VCLPG applied to the gate of the NMOS transistor NM1 that is the overdriving voltage generator 10 is raised to increase the level of the NMOS transistor NM1. Improve driving ability

As described above, the present invention adds a simple additional circuit to prevent the overdriving voltage from occurring on the sense amplifier driving line when the sense amplifier is overdriving, and thus, outputs the overdriving voltage. By increasing the voltage to a predetermined level to improve its driving ability, there is an effect of improving the sensing speed of the sense amplifier while reducing the degree of integration in layout design.

Claims (3)

A sense amplifier controller configured to control the overall operation of the sense amplifier by outputting the enable signals SPI_CLP, SPB1, SPB2, and SN according to the sense amplifier enable signal SAEN; An overdriving controller controlled by a substrate voltage enable signal VPPOK and an overdriving enable signal SPI_CLP that is an output of the sense amplifier controller to adjust a level such that the overdriving control signal VCLPG has a predetermined value; An overdriving voltage generator for conducting control by the overdriving control signal VCLPG and outputting a power supply voltage VDD as an overdriving voltage VDDCLP; And a sense amplifier driver controlled by the outputs SPB1, SPB2, and SN of the sense amplifier controller to apply the overdriving voltage VDDCLP, the driving voltage VDL, and the ground voltage VSS to the respective sense amplifiers. A sense amplifier driving circuit, characterized in that. The gate driving circuit of claim 1, wherein the overdriving controller comprises: an AND gate configured to receive a substrate voltage enable signal VPPOK on one input and an overdriving enable signal SPI_CLP on the other input; A control PMOS transistor configured to receive a substrate voltage VPP from a source and an output of the AND gate to a gate; A first PMOS transistor whose source and drain are commonly applied with a substrate voltage VPP; A switch having one side connected to a source of the first PMOS transistor and the other side connected to a drain of the first PMOS transistor; A second PMOS transistor having a source and a drain connected in common to the drain of the first PMOS transistor; And a capacitor connected to a drain of the second PMOS transistor on one side thereof to receive the overdriving enable signal (SPI_CLP). The sense amplifier driving circuit of claim 1, wherein the overdriving control unit is configured to raise the overdriving control signal VCLPG to a predetermined level by using a coupling effect of the capacitor.