JP2635998B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with reduced standby current.

[Conventional technology]

In recent years, for highly integrated memory devices such as dynamic MOSRAMs, reduction in power consumption has been demanded with the progress of high integration. In the dynamic MOSRAM, the ratio of the charge / discharge current of the bit line to the total current consumption is large. Therefore, for example, ISSCC Digest of Technical Papers, pp. 12-13 (February 1987) (DIGEST OF Technical Papers)
Technical Papers, pp. 12-13 (Feb. 1987))
A paper by K. Mashiko et al. [A 90ns 4Mb DR
As disclosed in “AM in a 300 mil DIP”, the maximum potential difference between a pair of bit lines is changed from _Vcc to _Vcc − _Vth (where _Vcc is the power supply potential and _Vth is the threshold voltage of the transistor). And the equalizing voltage of the bit line pair is reduced to ( _Vcc - _Vth ).
The charge / discharge current is reduced by setting it to / 2.

Here, an example of the concept of the memory cell and the sense amplifier circuit of the conventional dynamic type MOSRAM as described above is simplified and shown in FIG.

 In this figure, 1 is an n-channel MIS transistor Q₀
And capacitor C₀A memory cell composed of
MIS transistor Q₁, Q_TwoFirst flip-flop comprising
Type sense amplifier, 3 is a p-channel MIS transistor Q_Three, Q_Four
The second flip-flop type sense amplifier consisting of
n-channel MIS transistor Q_FiveFirst flip consisting of
Flop circuit activation means, 5 is a p-channel MIS transistor
Star Q₆For activating a second flip-flop circuit comprising
Stage, n-channel MOS transistor Q₇Are the bit line pair BL and
A transistor for equalizing the potential of ▲ ▼,
n-channel transistor Q₈, Q₉Are the bit lines BL, ▲
▼ indicates a predetermined potential (for example, (V_cc−V_th) / 2) pre
Transistor for charging, n-channel transistor
Jista Q_Ten, Q₁₁Is the bit line BL, ▲ ▼ is the I / O, ▲
▼ Transistor for connecting to line, n-channel
Transistor Q_B, Q (The gate is connected to power supply voltage V_ccConnected to)
Provided between bit line BL, ▲ ▼ and sense amplifier
The bit line high level to V_cc−V_thTiger for
Is a transistor.

Next, the operation of the circuit shown in FIG. 4 will be described with reference to the timing chart of FIG.

When the signal EQ from the high level at time T ₁ low level decreases, the equalizing transistor Q _7, precharge transistors Q _8, Q ₉ is the bit lines BL and ▲ ▼ floating state so off. When the word line WL to the time T _2, is changed from the low level to the high level, the transistor Q ₀ is turned on. For example, when a high level is stored in the memory cell 1, the level of the bit line BL slightly increases as indicated by a solid line. This level of the node BL 'through the transistor Q _B also increases as well. Therefore a high level S ₀ from the low level at time T _3, ▲ ▼ the changes from the high level to the low level, the transistor Q _5, Q ₆ is the node N ₁ is turned on to 0V,
Node N ₂ becomes the power supply voltage V _cc. As a result, flip-flops 2 and 3 are activated to amplify the aforementioned slight potential difference generated between nodes BL 'and ▲', and
Is changed to the _Vcc level and the node ▲ ▼ 'is changed to 0V. The potential of the bit line BL, when the node BL 'reaches the power supply potential V _cc, transistor Q threshold voltage V _th amount corresponding low V _cc -V _th of _B
Becomes Time T ₄ to the signal Y becomes a low level to the high level, the potential difference generated in the bit line is transmitted to the I / O lines, then amplified high-level output appears at the external output terminal. When a low level is stored in the memory cell 1, the level of the bit line ▼ is _Vcc − _Vth
And the bit line BL becomes 0V. Word line WL is lowered from the high level to the low level at time T _5, equalizing the signal EQ becomes high level again at time T ₆ transistors Q ₇ and the precharge transistors Q _8, Q ₉ is turned on the bit line BL, ▲
▼ is equally connected to ( _Vcc − _Vth ) / 2 level internal power supply _VBL .

In such a circuit, the maximum bit line level amplitude is V
By decreasing from _cc to _Vcc - _Vth , the charge / discharge current of the bit line can be reduced.

In the case the high level of the word line WL is V _cc is a high level to be written to the memory cell 1 when the threshold voltage of the transistor Q ₀ and _V thM V _cc -V thM next, the loss of reading charges for high level . Therefore, lowering the precharge level of the bit line from V _cc / 2 to (V _cc −V _th ) / 2 also has the effect of increasing the read margin for the high level and improving the operation margin.
In this case, it is most effective to set V _th = V _thM .

[Problems to be solved by the invention]

However, since the conventional semiconductor memory device is constructed as described above, when equalizing the bit lines, the bit lines BL, ▲ level difference ▼ is by short circuit is transistor Q ₇ is V _cc -V _th can be easily and _{(V cc -V th) / 2} , the node BL ', ▲ ▼' level difference of only Ruru be short for a V _cc becomes a V _cc / 2, the transistor Q ₈ , through Q ₉ (V _cc −V _th ) / 2
The level of the internal power supply V _BL, forcibly (V _cc -V _th) / 2
Need to level. This internal power supply V _BL generates by resistance division circuits typically for example, a power supply voltage and the ground voltage, as described above, to the level of the node BL 'and ▲ ▼' forced to (V _cc -v _th) / 2 Therefore, it is necessary to increase the driving capability, and therefore, it is not possible to reduce the resistance value of the dividing resistor. Therefore, between the power supply voltage and the ground voltage
There is a problem that the standby current flowing in DC becomes large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a semiconductor memory device capable of reducing a charge / discharge current of a bit line and significantly reducing a standby current. .

[Means for solving the problem]

In the semiconductor memory device according to the present invention, the first and second voltage supply paths for supplying the first and second power supply voltages to the two sets of flip-flop type sense amplifiers in accordance with the first control signal, respectively. Voltage effect means interposed in a first voltage supply path for shifting down to a predetermined voltage of a first power supply voltage (for example, V _cc ), and a first control signal based on a second control signal related to the first control signal. A rapid charging means for rapidly charging the voltage supply path of the first voltage supply path;
And an activation control means including a flip-flop circuit which makes the quick charging means inactive by controlling the control signal.

[Action]

In the present invention, the potential of the first voltage supply path is approximately equal to the value obtained by subtracting the threshold voltage (for example, V _thM ) of the memory cell from the first power supply voltage during the sensing operation (for example, V _cc −V _thM ) at high speed. By providing a rapid charging means, the internal power supply requires almost no driving capability,
It is possible to greatly reduce the standby current of the internal power supply generation circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a memory cell comprising an n-channel MIS transistor Q ₀ and a capacitor C ₀ , and 2 is an n-channel MOS
A first flip-flop type sense amplifier including transistors Q ₁ and Q ₂ , a _second flip-flop type sense amplifier including p-channel MIS transistors Q ₃ and Q ₄ ,
First flip-flop circuit activating means comprising a channel MIS transistor Q _5, the second flip-flop circuit activating means 5 consisting of n-channel MIS transistor Q _C and p-channel transistors Q _6, Q _{A, 6} is n-channel transistor for the transistor Q is applied to the _a ▲ ▼ signal control circuit, n-channel MOS transistor Q ₇ is for equalizing the bit line pair BL and ▲ ▼ potentials,
The n-channel transistors Q ₈ and Q ₉ are connected to the bit lines BL and ▲, respectively.
A transistor for precharging ▼ to a predetermined potential (for example, (V _cc −V _th ) / 2), n-channel transistors Q ₁₀ and Q ₁₁ connect bit lines BL and ▲ to I / O lines and ▲, respectively.
It is a transistor for connecting to the line.

Next, an example of the signal control circuit is shown in FIG. In FIG. 2, reference numeral 7 denotes an RS flip-flop circuit comprising NOR gates G1 and G2, and gate G3 denotes an inverter.

Here, the basic operation of the flip-flop circuit shown in FIG. 2 will be described. As shown in FIG. 3, when the reset pulse S ₀ F ′ becomes “H” level at time T ₀ , the output
▼ falls from “H” level to “L” level. Exceeding the potential V ₁ to the potential of the node N ₂ is are slowly rises, the output ▲
▼ becomes “H” level again. Here, the value of the potential V ₁ was, it is possible to adjust the threshold of the transistor of the NOR gate G2 by arbitrarily controlled.

 The difference between the circuit of FIG. 1 and the circuit of FIG.
Now, the n-channel MOS transistor Q in the circuit of FIG.
_B, Q Does not exist, and the second flip-flop circuit
Activating means 5 is a p-channel MOS transistor Q₆Only
And n-channel transistor Q_C(Power supply to gate V_ccContact
Continued) and p-channel transistor Q_AConnected to
And node N_TwoAnd p-channel transistor Q_AApplied to
▲ ▼ signal control circuit and node N_TwoIs connected
It is a point that has been.

Next, the operation of the circuit shown in FIG. 1 will be described with reference to the timing chart of FIG.

When the signal EQ at time T ₁ is lowered from the high level to the low level, the equalizing transistor Q _7, since precharge transistors Q _8, Q ₉ is turned off, the bit lines BL and ▲ ▼ is floating. When the word line WL to the time T _2, is changed from the low level to the high level, the transistor Q ₀ is turned on. For example, when a high level is stored in the memory cell 1, the level of the bit line BL slightly increases as indicated by a solid line. So the time T _7, for example, signal S one-shot pulse signal S ₀ becomes slightly faster high level from ₀ F '(where signal S ₀ F' signal as indicated by the signal S ₀ and simultaneously or broken line in the figure, S When it slightly be later become the high level from ₀₎ becomes high level, the signal ▲ ▼ goes low, the potential of the node N ₂ begins to be charged toward the power supply voltage V _cc. Here, when setting the potential of the V ₁ to about V _cc -2 V _th, the potential of the node N ₂ becomes the high level at time T _8, as the ▲ ▼ will be described later exceeds V _cc -V _th . Then the high level signal S ₀ from the low level at time T _3,
When the signal ▼ changes from the high level to the low level, the transistors Q ₅ and Q ₆ are turned on, and the node N ₁ starts charging rapidly toward 0 V and the node N ₂ further toward V _cc −V _th . The signal S
₀ F 'the signal ▲ ▼ returns to the low level immediately after becoming a low level. Subsequent while monitoring the potential of the node N ₂ at time T ₄ to control the generation of the signal ▲ ▼ ▲ ▼ signal control circuit, the signal ▲
▼ becomes the high level T ₈ immediately before the potential of the node N ₂ becomes V _cc -V _th. As a result, the flip-flops 2 and 3 are activated, amplify the above-mentioned slight potential difference generated between the bit line BL and ▲, and change the bit line BL to the _Vcc − _Vth level and the bit line ▼ to 0V. Let it. That is, it is possible to close early desired potential V _cc -V _th potential of the node N ₂ for applying a signal ▲ ▼ transistor Q _A. Next time T ₄ the signal Y is from a low level to a high level,
The potential difference generated in the bit line is transmitted to the I / O line, then amplified and a high-level output appears at the external output terminal. When a low level is stored in the memory cell 1, the level of the bit line ▼ is _Vcc − _Vth and the level of the bit line BL is 0V as shown by a broken line. Down from time T ₅ to the word line WL is at a high level to the low level, the time T ₆ the signal EQ when the changes to the high level again equalizer transistor Q ₇ is turned on the bit line BL, ▲ ▼ equally (V _cc -V _th) / 2, and at the same time, the precharge transistors Q ₈ and Q ₉ are turned on to connect the bit line to the (V _cc −V _th ) / 2 level internal power supply V _BL .

In the present embodiment as described above, since so as to activate the direct V _cc -V _th common source N ₂ of the flip-flop 3, equalize during flip-charge transistor Q ₇
(V _cc −V _th ) / 2 level can be realized only with the internal power supply V _BL
Only needs to keep that level, so little drive power is needed. Therefore, it is possible to greatly reduce the standby current in the internal power supply _VBL generation circuit.

In the above embodiment, a semiconductor memory device using a memory cell including an n-channel MOS transistor is shown. However, the semiconductor memory device may include a p-channel MOS transistor. In this case, the waveform of the word line WL is inverted. in phase further flip-flop 2 and 3, swapping the conductivity type of each transistor of the activation means 4 and 5, further signal gate to the power supply V _cc and the drain of the transistor Q ₅ from the ground from the signal S ₀ ▲ ▼
To, the signal S ₀ of the gate from the signal ▲ ▼ drain from the power source V _cc to ground of the transistor Q _6, to ground the gate of the transistor Q _C from the power supply V _cc, to ground the drain of the transistor Q _A from the power supply V _cc The gate may be changed to a waveform S ₀ F complementary to the signal ▲ ▼.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, the means for activating the sense amplifier by setting the first voltage supply path to a value obtained by subtracting the threshold voltage of the memory cell from the first power supply voltage is used. As a result, not only the charging / discharging current of the bit line but also the standby current can be greatly reduced, and the read margin for a high level is increased and the operation margin is improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a memory cell and a sense amplifier of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a signal control circuit thereof, FIG.
FIG. 2 is a waveform diagram illustrating the basic operation of the flip-flop circuit shown in FIG. 2, FIG. 4 is a circuit diagram showing a memory cell and a sense amplifier of a conventional semiconductor memory device, and FIG. FIG. 6 is a diagram showing a timing chart for explaining the operation, and FIG. 6 is a diagram showing a timing chart for explaining the operation of the semiconductor memory device according to the present invention. 1 memory cell, the flip-flop type sense amplifier 2, activation control unit 6, the flip-flop type circuit 7, BL, ▲ ▼ bit lines, Q _A is p-channel MIS transistor, Q _C is the n-channel MIS transistor, S ₀ , ▲
▼, ▲ ▼, S ₀ F ′ are control signals. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] The first power supply voltage and the second power supply voltage are equal to the first power supply voltage.
In a semiconductor memory device of a type in which information of a memory cell is read out by detecting and amplifying a potential difference between a pair of bit lines by sense amplifiers respectively supplied from first and second power supply paths according to the control signal of Voltage drop means interposed in the first voltage supply path for shifting down the first power supply voltage to a predetermined voltage; and the first voltage supply based on a second control signal related to the first control signal. A quick charging means for rapidly charging the path; and a voltage monitoring means for monitoring the voltage of the first voltage supply path and controlling the second control signal in response to a rise in the voltage of the voltage supply path, thereby disabling the quick charging means. And an activation control means including a flip-flop circuit to be activated.