JP2875851B2 - Drive circuit of sense amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A drive circuit for a sense amplifier is intended to reduce the voltage applied to the sense amplifier to a desired voltage value lower than the voltage of a high-potential power supply and to drive at high speed. Driving means for driving a sense amplifier provided between the high-potential-side power supply line and a power supply end of the sense amplifier; detecting a potential of the power supply end of the sense amplifier; And control means for stopping the drive of the sense amplifier by the drive means when the power supply voltage exceeds the threshold value, wherein the control means comprises an inverter and a NAND gate, and the inverter has the sense circuit. The potential of the power supply terminal of the amplifier is supplied, and the output of the inverter and the sense amplifier drive signal are supplied to the NAND gate. The output of the gate supplies the driving means.

[Industrial applications]

The present invention relates to a drive circuit of a sense amplifier, and more specifically, for example, a DR circuit that uses an external power supply voltage internally lowered.
The present invention relates to a drive circuit suitable for use in a sense amplifier such as an AM.

In recent years, for example, with an increase in storage capacity of a computer or the like, an increase in memory capacity, that is, a large number of semiconductor storage devices such as DRAMs with high integration have been provided. Many drive circuits for the sense amplifiers used therein have been developed.

In a semiconductor memory device aiming for high integration, in order to arrange many elements in the same chip area, it is necessary to miniaturize an internal transistor, an internal wiring, and the like. Matching wirings come closer, and as a result, capacitance between wirings increases, and crosstalk increases. That is, while a constant power supply voltage is applied while the distance between the wirings becomes shorter, the electric field generated increases as the distance between the wirings becomes shorter. Since the breakdown of the internal transistor is determined by the electric field, if the electric field becomes too large, the internal transistor is easily broken, and the reliability of the device is reduced. Therefore, it is necessary to reduce the applied power supply voltage as the distance between the wirings becomes shorter. However, since the external supply voltage cannot be freely changed from the standpoint of a user interface, the drive circuit of the sense amplifier in such a semiconductor memory device uses the external supply voltage (for example, 5 V) in the chip for this external supply voltage. It is necessary to generate an internal voltage (for example, 4v) lower than the external supply voltage.

[Conventional technology]

FIG. 7 shows an example of a conventional sense amplifier drive circuit of this type.

In FIG. 7, the drive circuit of the conventional sense amplifier is roughly composed of a sense amplifier group 1 as a sense amplifier and a driving means 2, and the sense amplifier group 1 has 2n bit lines B1, ▲ N CMOS sense amplifier circuits SA1, ..., S corresponding to ▼, ..., Bn, ▲ ▼ respectively
An, and each of the CMOS sense amplifier circuits SA1, ..., S
An is two PMOS transistors P1x, P2x and two N
It is composed of MOS transistors N1x and N2x (1 ≦ x ≦ n).

Driving means 2 is a PMOS transistor Q1, an NMOS transistor
Consists of Q2.

Q3 is an NMOS transistor interposed in series between the PMOS transistor Q1 and the sense amplifier group 1, and is a voltage drop means for generating an internal voltage lower than the external supply voltage (Vcc in this case).

In the figure, SE and ▼ indicate sense amplifier drive signals.

In the above configuration, as shown in FIG. 8, the word line is driven at the timing of time T1, and the sense amplifier group 1 causes the bit lines B1 and ▲ at the timing of time T2.
When the amplification of the potential level of ▼ is started, the bit lines B1,
The voltage of ▼ is amplified, and the waveforms of the bit lines B1 and ▼ are spread over time, as shown by the solid line in FIG. In this case, the bit line ▲ ▼ goes down to the ground level, but the bit line B1 side has a predetermined internal voltage hVcc (eg, 4v) lower than the external supply voltage Vcc (eg, 5v).
It only rises up to that point. That is, the voltage applied to the sense amplifier group 1 is reduced by the NMOS transistor Q3 inserted in series between the external power supply having the external supply voltage Vcc and the sense amplifier group 1, and the sense amplifier group 1
The maximum value of the voltage amplified by the predetermined internal voltage hVcc
This is because it is controlled to be the value of More specifically, assuming that the threshold voltage of the NMOS transistor Q3 is Vth because the gate of the NMOS transistor Q3 is connected to the external power supply and the source is connected to the high potential side of the sense amplifier group 1, the NMOS transistor Q3 The voltage applied to the sense amplifier group 1 via is represented by Vcc-Vth. Since this voltage Vth is about 1 V, the maximum value of the voltage amplified by the sense amplifier group 1 is about 4 V, and the voltage can be easily reduced to a desired voltage value.

As another conventional example, for example, there is one as shown in FIG. 9. In this figure, the same numbers as those in the conventional example shown in FIG. 7 indicate the same or corresponding parts.

In FIG. 9, Q51 and Q52 denote NMOS transistors and R that constitute a current mirror type analog minute signal amplifier circuit.
1 and R2 are resistors, and these NMOS transistors Q51, Q52, P
An analog feedback circuit is configured by the MOS transistors Q53 and Q54 and the resistors R1 and R2.

In such a configuration, when the sense amplifier drive signal SE becomes high level, the NMOS transistor Q6 is turned on, the NMOS transistor Q51 is turned on, and a current flows through the PMOS transistor Q53. When a current flows through the PMOS transistor Q53, the PMOS transistor Q54 conducts accordingly, so that the gate voltage of the NMOS transistor Q55 increases and conducts, and a current flows through the PMOS transistor Q4. Then, due to the action of the current mirror type analog minute signal amplifier circuit, a current I equal to the current flowing through the current path l1 flows through the other current path l2 as a constant current. In this way,
The sense amplifier group 1 starts amplification, and the NMOS transistor Q52
When the gate voltage rises above the reference voltage VR,
NMOS transistor Q52 conducts. NMOS transistor Q52
Becomes conductive, the gate voltage of the NMOS transistor Q55 decreases, the NMOS transistor Q55 turns off, and no current flows through the PMOS transistor Q4. As a result, the PMOS transistor Q5 is turned off, the driving of the sense amplifier group 1 is stopped, and the drain voltage of the PMOS transistor Q5 does not rise to Vcc. Therefore, the voltage for driving the cell array is Vc
lower than c.

[Problems to be solved by the invention]

However, in the conventional sense amplifier drive circuit as shown in FIG. 7, the NMOS transistor Q3
Is connected between the external power supply and the sense amplifier group 1 in series.
If the source potential of Q3 is low, a large bias is applied between the gate and source of NMOS transistor Q3, so that the internal resistance of NMOS transistor Q3 is also low.However, as the source potential of NMOS transistor Q3 rises, Since the gate-source bias decreases, the internal resistance of the NMOS transistor Q3 increases. That is, the output waveform of the bit line voltage shown in FIG. 8 depends on the bias condition of the NMOS transistor Q3, and the actual waveform output from the bit line B1 shows that the internal resistance of the NMOS transistor Q3 increases as the voltage increases. Therefore, as shown by the dashed line in FIG.
There has been a problem that the voltage gradually rises, the amplification operation end time of the sense amplifier group 1 is prolonged, and the voltage cannot be increased to a desired voltage value within a predetermined time.

In the conventional sense amplifier drive circuit as shown in FIG. 9, the drain voltage of the PMOS transistor Q5 is reduced by the action of a current mirror type analog small signal amplifier circuit to obtain a desired voltage value. Resistance R1, R2
When the drain of the PMOS transistor Q5 reaches a predetermined voltage by the comparator operation for comparing the voltage divided by the above with the reference voltage VR, the PMOS transistor Q5 is cut off.
Since an analog small signal amplifier circuit is used for this control,
This circuit may pick up and amplify the noise generated in the chip, causing malfunction.In addition, it is necessary to consider the time constant in the feedback loop and add a phase compensation circuit for stabilization. There was a problem that it was not very practical.

Therefore, an object of the present invention is to reduce the voltage applied to the sense amplifier to a desired voltage value lower than the voltage of the high-potential power supply, and to drive at high speed.

[Means for solving the problem]

In order to achieve the above object, the sense amplifier drive circuit according to the present invention has a sense amplifier provided between a high-potential-side power supply line and a power supply terminal of the sense amplifier group 1 as shown in FIG. Driving means 2 for driving the group 1; detecting the potential of the power supply end of the sense amplifier group 1; and driving the sense amplifier group 1 by the driving means 2 when the detected potential exceeds a predetermined potential. And a control means 3 for stopping the operation, the control means 3 comprises an inverter G2 and a NAND gate G1.
The inverter G2 is supplied with the potential of the power supply terminal of the sense amplifier group 1, the NAND gate G1 is supplied with the output of the inverter G2 and the sense amplifier drive signal, and the output of the NAND gate G1 is supplied. Is supplied to the driving means 2.

[Action]

In the present invention, the control means detects the potential level on the high potential side of the sense amplifier, and when the potential level exceeds a predetermined reference potential, the driving means stops driving the sense amplifier.

Therefore, the voltage applied to the sense amplifier is reduced to a desired voltage value lower than the voltage of the high-potential power supply, and the increase in the voltage value of the sense amplifier is proportional to time. The voltage is increased to the value, and high-speed driving is performed.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

Explanation of principle FIG. 1 is a principle diagram of the present invention, and the same reference numerals as those in the conventional example shown in FIG.

In FIG. 1, the sense amplifier drive circuit of the present embodiment is roughly divided into a sense amplifier group 1, a driving unit 2,
The control means 3 comprises a driving means 2 comprising a PMOS transistor Qs, and the control means 3 comprises a NAND gate G1 and an inverter G2. As shown in FIG. 2, the output characteristic of the inverter G2 is such that the value of the input voltage Vin is inverted at a predetermined threshold voltage Vth and becomes the output voltage Vout. BL and ▲ ▼ are bit lines.

Note that SAP is the high potential side voltage of the sense amplifier group 1, N1 is the output of the NAND gate G1, N2 is the output of the inverter, and SE is the sense amplifier drive signal.

In the above configuration, the operation will be described based on a timing chart for explaining the operation timing in FIG.

Before the start of the sensing operation, the sense amplifier drive signal SE is at "L", whereby the output N1 of the NAND gate G1 always becomes "H".

When the sense amplifier drive signal SE changes to "H" as shown in FIG. 7A, the output N1 of the NAND gate G1 becomes "L" as shown in FIG. Qs conducts, and the sensing operation starts. Thereby, as shown in FIG. 3C, the high-potential-side voltage SAP of the sense amplifier group 1 gradually increases from the bit line reset voltage (for example, 2 V). Since the inverter G2 has the characteristic shown in FIG. 2 with respect to the high-potential-side voltage SAP, when the high-potential-side voltage SAP becomes equal to or higher than the threshold voltage Vth of the inverter G2, it is shown in FIG. So that the output of inverter G2
N2 changes to "L", and as a result, the output N1 of the NAND gate G1 becomes "H" as shown in FIG.
The transistor Qs is cut off regardless of the level of the sense amplifier drive signal SE. That is, as shown in FIG. 3D, the rise of the high-potential-side voltage SAP is stopped by the cut-off of the PMOS transistor Qs.
AP rises only to a predetermined value hVcc (hVcc <Vcc).

Therefore, the voltage applied to sense amplifier group 1 can be reduced to a desired voltage value lower than the voltage of the high-potential power supply, and high-speed driving can be performed.

 Hereinafter, embodiments will be described based on the above basic principle.

4 to 6 are views showing an embodiment of a drive circuit of a sense amplifier according to the present invention. The same reference numerals as those in the conventional example shown in FIG. 7 and the principle diagram shown in FIG. 1 denote the same or corresponding parts. .

In FIG. 4, 3 is a control means, and 4 is a potential maintaining means. The control means 3 comprises a NAND gate G1 and an inverter G2, and the NAND gate G1 is a PMOS transistor.
Q11 and Q12, and NMOS transistors Q13 and Q14, and the inverter G2 includes a PMOS transistor Q15 and an NMOS transistor Q16. The potential maintaining means 4 comprises an NMOS transistor Q17 inserted in series between the voltage power supply and the high potential side of the sense amplifier group 1. Q18,..., Q21 are NMOS transistors, C is a capacitor, and WL is a word line. Rr is a current resistance, and the current feedback resistance Rr is effective in suppressing the peak current. This current feedback resistor Rr may be inserted intentionally, and PM
The OS transistor Qs may be placed near the load, the sense amplifier, and the parasitic resistance generated by the wiring resistance from the power supply to the source of the PMOS transistor Qs may be used.
Even if a large current is about to flow at the beginning of the sensing operation due to Rr, the source voltage of the PMOS transistor Qs is
The voltage drops by the voltage generated at both ends of Rr, and the bias voltage between the gate and source of the PMOS transistor Qs is substantially reduced to suppress the increase in current. That is, the output peak current of the PMOS transistor Qs is suppressed due to the current feedback action by the current feedback resistor Rr.

Note that SAP is a high-potential-side voltage of the sense amplifier group 1, SAN is a low-potential-side voltage of the sense amplifier group 1, RE is a reset clock signal, and SE, ▼, and SE1 are sense amplifier drive signals.

The operation of the above configuration will be described with reference to timing charts for explaining the operation timings in FIGS.

First, the word line WL changes from “L” to “H” and becomes active when the row address strobe signal ▲ ▼ applied to the memory chip from the outside changes from “H” to “L”, and resets accordingly. The clock signal RE changes from “H” to “L”. Then, the sense amplifier drive signal SE becomes “H”.
, And the sensing operation is started. Then, the PMOS transistor Qs conducts, and the high potential side voltage SA of the sense amplifier group 1 is turned on.
P gradually increases from the bit line reset voltage. When the threshold voltage Vth of the PMOS transistor Q15 and the NMOS transistor Q16 constituting the inverter G2 becomes higher than the high potential side voltage SAP, the output N2 of the inverter G2 turns to "L", thereby the PMOS constituting the NAND gate G1. Transistor Q1
1, the PMOS transistor Qs is cut off by the inversion of the PMOS transistor Q12 and the NMOS transistor Q13 among the NMOS transistors Q13 and Q14 regardless of the level of the sense amplifier drive signal SE, and the rise of the high potential side voltage SAP is stopped. You.
Before this cutoff operation, the sense amplifier drive signal SE1 changes from “L” to “H”, and the NMOS transistor Q17 is turned on. As a result, after the PMOS transistor Qs is turned off, the potential of the high potential side voltage SAP of the sense amplifier group 1 is set to “H”.
, And the potential of the high-potential-side voltage SAP is prevented from dropping by turning off the PMOS transistor Qs. The maintained voltage value can be adjusted by the voltage amplitude of the sense amplifier drive signal SE1, but, for example, if the sense amplifier drive signal SE1 is Vcc, the potential of the high potential side voltage SAP is about Vcc−Vth. Is maintained.
Then, the reset clock signal RE changes to “H” again, and when the reset cycle starts, the output N2 of the inverter G2 becomes “H”.
, Whereby the whole system returns to the initial state.

Therefore, in the present embodiment, even if the PMOS transistor Qs is turned off, the NMOS transistor Q17 (gm small transistor)
Is turned on, it is possible to prevent the potential of the high potential side voltage SAP from dropping.

As described above, in this embodiment, the voltage applied to the sense amplifier can be reduced to a desired voltage value lower than the voltage of the high-potential power supply, and high-speed driving can be performed.

Although the above embodiment describes the case where the potential of the high-potential-side voltage SAP is detected by the inverter G2 of the PMOS transistor and the NMOS transistor, the invention is not limited to this, and any device capable of detecting the voltage level may be used. For example,
A voltage comparator circuit for comparing with a reference voltage using a current mirror type differential amplifier may be used. In this case, since the load for detecting the potential of the high potential side voltage SAP is not so large, the differential amplifier may be one with small current consumption, and there is no fear of oscillation of the differential amplifier. Further, even when noise is received, since the potential detection portion operates digitally as a voltage comparator, there is no unstable operation due to a noise signal, which is common in analog feedback circuits.

Further, in the present embodiment, the DRAM in which the memory cell portion is composed of the transistor and the capacitor is described, but the present invention is not limited to this. That is, if the memory cell portion is replaced with a floating gate type memory cell, the same operation as that of the DRAM is performed.
Also applicable to EPROM and the like.

[Effects of the Invention] In the present invention, the voltage applied to the sense amplifier can be reduced to a desired voltage value lower than the voltage of the high-potential power supply, and high-speed driving can be performed.

[Brief description of the drawings]

1 to 3 are diagrams for explaining the principle of the drive circuit of the sense amplifier according to the present invention. FIG. 1 is a diagram showing the principle, FIG. 2 is a diagram showing the output characteristics of the inverter, and FIG. FIGS. 4 to 6 are timing charts for explaining operation timings. FIGS. 4 to 6 are diagrams showing an embodiment of a drive circuit of a sense amplifier according to the present invention. FIG. 4 is a circuit diagram showing the entire configuration. FIG. 6 is a timing chart for explaining the operation timing, FIG. 7 is a circuit diagram showing an entire configuration of a drive circuit of a conventional sense amplifier, and FIG. 8 is an output waveform of a bit line voltage level of a conventional example. FIG. 9 is a circuit diagram showing an overall configuration of a drive circuit of another conventional sense amplifier. 1 sense amplifier group (sense amplifier), 2 drive means, 3 control means, 4 potential maintaining means, G1 NAND gate, G2 inverter.

Claims (2)

(57) [Claims] 1. A drive means for driving a sense amplifier provided between a high-potential-side power supply line and a power supply terminal of a sense amplifier, and a potential detected and detected at a power supply terminal of the sense amplifier. And control means for stopping the drive of the sense amplifier by the drive means when the potential exceeds a predetermined potential.The drive circuit of the sense amplifier, comprising: an inverter and a NAND gate; Is supplied with a potential of a power supply terminal of the sense amplifier, an output of the inverter and a sense amplifier drive signal are supplied to the NAND gate, and an output of the NAND gate is supplied to the drive unit. Drive circuit for the sense amplifier. 2. The sense amplifier according to claim 1, further comprising a potential maintaining means for maintaining a potential at a power supply terminal of said sense amplifier when said driving means stops driving said sense amplifier. Drive circuit.