JP2607559B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage limiter for dropping an external power supply voltage in a semiconductor integrated circuit chip and applying the voltage to a fine transistor in the chip. The present invention relates to a voltage limiter capable of obtaining a stable output voltage with respect to a voltage.

[Conventional technology]

FIG. 11 shows a conventional voltage limiter circuit and an application example thereof. This is the Extruded Abstracts of
The Eighteens Conference on Solid State Devices and Materials, 1986, 3rd
Pages 07 to 310 (Extended Abstracts of the 18th Co
nferencs on Solid State Devices and Materials, 198
6, pp307-310).

Hereinafter, an outline of this operation will be described. In the figure, 1 is a semiconductor chip, VC2 differential is a feedback type voltage limiter circuit using a differential amplifier, L1 and L3 are circuits including fine transistors with low withstand voltage, and L2 is a circuit including large transistors with high withstand voltage and large in size. . Here, L1 and L3 are the limiter reference voltage VL
Voltages VLO ₁ and VLO ₂ lower than the external voltage V _CC by a voltage limiter with reference to 1, VL2 are applied. On the other hand, V _CC is directly applied to L2. φ ₁ , φ ₂ , φ ₃ are L1, L respectively
2, L3 drive signal. Φ ₁ ′ and φ ₃ ′ are signals for controlling the current of the differential amplifier in the voltage limiter VC2.
The transistor Q ₈ on and off. These signals are
_1, the phi ₃ L1, L3 is changed to the Low level (V _SS) from the High level (V _CC) at the time of starting the operation. Thus, the transistor Q ₈ is turned in the VS2, increased current of the differential amplifier will be able to respond quickly to changes in VLO _1, VLO ₂ due to current variations in L1, L3. On the other hand, when the L1, L3 does not operate, to cut-off the Q ₈ to High level. Thus the current flowing through the differential amplifier has a value that can only Q _9. If the While g _m of connexion Q ₈ Oke by the g _m of the large Q ₉ is small, low power consumption voltage Rimitsuta can be realized at high speed.

In this figure, two circuits VC2 are connected to different loads, respectively, in order to prevent the fluctuation of the internal power supply voltage due to the current fluctuation of one load from affecting the other loads. is there.

[Problems to be solved by the invention]

According to the above prior art, the differential amplifier used in the voltage limiter circuit has the P-channel transistors Q ₈ and Q ₉ as the common source load and the N-channel transistors Q _R and Q ₁₃ as active as shown in FIG. Load, P-channel transistor Q ₁₀ ,
The Q ₁₁ as a source-coupled pair, have convex configuration to directly input the reference voltage and Rimitsuta output voltage to its gate. However, in such a configuration, the gate-source voltage V _GS of the source-coupled pair depends on the difference voltage between V _CC and VL or VLO because Q ₈ and Q ₉ perform the same operation as a resistor in the unsaturated region. And V _CC
When the difference between V _CC and VL is small,
As L increases, V _GS decreases, the current decreases, and the response speed decreases. The _{V CC ≦ VL + V T Q} 10, Q 11 in the condition of there has been a problem that not operate as cut-off (amplifier. Where V _T is the absolute value of the threshold voltage of the transistor Q _10, Q _11.

When VL = 3 (V) and V _T = 1 (V) are substituted into the above equation as a simple numerical value, V _CC ≦ 4 (V), and the circuit does not operate at a voltage of V _CC of 4 V or less. In product DRAMs and the like, it is necessary to design the circuit to operate up to about V _CC = 3 V in order to guarantee operation against a drop in power supply voltage due to spike current or the like. On the other hand, the conventional method operates only up to V _CC = 4 V, which is not suitable for practical use.

Further, in the prior art, the current of the differential amplifier is controlled only in two stages, that is, during standby and during operation. In addition, this signal is not generated by directly detecting the load condition.
Since the current is generated by the load drive signal or the clock signals before and after the load drive signal, it is necessary to increase the current of the differential amplifier for a longer time than the operation end time of the load. For this reason, the power consumption has not been sufficiently reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a voltage limiter that operates at high speed and consumes less power even when V _CC is equal to the output voltage of the voltage limiter.

[Means for solving the problem]

The first problem is that a level shift circuit is inserted into the input terminal of the differential amplifier so that a voltage equal to or lower than the input voltage by the threshold voltage of the transistor is applied to the input terminal of the differential amplifier. Is solved.

Also, contrary to the prior art, the problem can be solved by configuring the load of the differential amplifier with a P-channel MOS transistor and the source-coupled pair with an N-channel MOS transistor.

The second problem is that two or more current control transistors of the differential amplifier are provided, and furthermore, a circuit for detecting the amount of decrease in the output voltage of the voltage limiter and thereby controlling the current control transistor is provided. Will be resolved.

[Action]

Insert a level shift circuit into the input terminal of the differential amplifier,
By lowering the voltage applied to the input terminal of the differential amplifier by the voltage of the source-coupled pair to the transistor V _T or lower, the source-coupled pair to the transistor gate-source voltage even when the power supply voltage and the limiter output voltage are equal. V
_GS is ensured more than V _T.

Further, by making the source-coupled pair of transistors of the differential amplifier N Channel transistor, V _GS of the source-coupled pair of transistors is to become as determined with respect to the V _SS, not affected on V _CC. Was but connexion, reference voltage VL becomes possible always operate regardless of the value of V _CC equal to or greater than V _T.

By using the method of two or more, the voltage Rimitsuta, even when the power supply voltage and the output voltage is equal, it is possible to operate since V _GS of the source-coupled pair Shiranjisuta is ensured above V _T.

Further, by providing two or more current control transistors of the differential amplifier, the current value can be more finely controlled, so that useless current can be reduced and power consumption can be reduced. Furthermore, by providing a circuit that detects the amount of decrease in the output voltage of the voltage limiter and automatically generates a current control signal according to this amount, the current can be increased only while the current is actually flowing through the load. Unnecessary current can be eliminated. Further, by combining the two, instantaneous and fine control can be performed with respect to a change in load current, so that power consumption can be further reduced.

〔Example〕

FIG. 2 shows a first embodiment of the present invention. This feature is that the insertion of the level shift circuit consisting of Q _L1, Q _L3 and Q _L2, Q _L4 to the input terminal of the differential amplifier Rimitsuta the conventional example shown in FIG. 11.

Here, Q _L3, L _L4 certain voltage V _G is applied to the gate operates as a constant current source. Therefore, a constant current flows through Q _L1 and Q _L2 regardless of their gate voltages. Q _L1 , Q
_If the gate voltage of _L2 is V _i , its source voltage is V ₀ , and its drain current is _{ID, the} drain conductance is β, Holds, the relationship between the output voltage and the input voltage is Is represented by Since V _T and I _D are constant, V ₀ is greater than V _i It will be low.

Here, as described above, when the operating range of the differential amplifier is obtained, V _i = 3 (V), V _T = 1 (V), I _D = 1 (μA), β = 10
^Since V ₀ = 1.6 (V) as ^-5 (μS / V), V _CC ≦ V ₀ + V
_T = 2.6 (V).

Therefore, according to the present embodiment, it is possible to realize a voltage limiter circuit that can operate sufficiently even when V _CC = 3 (V).

In this method, the signal is delayed by the level shift circuit. Therefore, it is necessary to eliminate this circuit in order to perform higher-speed operation.

FIG. 1 shows an embodiment which solves the above problem. This feature is that the differential amplifier of the conventional limiter shown in FIG. 11 is replaced with an amplifier using the above-mentioned P-channel transistor as a load. Here, the reference voltage VL is input to the gate of the source-coupled pair of transistors Q ₃ of N-channel. Also on the other of the gate of the source-coupled pair of transistors Q ₄ is input Rimitsuta output VLO. Thus, the comparison voltage is N
Since the signal is directly input to the source coupling pair of the channel, the number of elements through which the signal passes can be reduced, and high-speed operation can be performed. Since the source-coupled pair is an N-channel, its gate-source voltage is determined based on V _SS , and the current does not depend on V _CC . For further VL, when the threshold voltage of the source-coupled pair and V _T, Watatsute operation is enabled in a wide range from V _T to V _CC.

Since the current control transistor Q ₅ amps as the N channel, the control signal _{1 'is} phi ₁ of FIG. _2' phase opposition to the.

FIG. 3 shows a third embodiment of the present invention. This feature is that the current control transistor of the differential amplifier is divided into a plurality (three in this embodiment) and driven by signals having different timings.

The operation will be described below. In the figure, VC3 is a voltage limiter circuit, MCA is a DRAM memory cell array, DD is a data line, W
Word lines, Q _M and C _S is the memory cell, Q _S1 to Q _S4 sense amplifier, Q _SP is a driving transistor of the sense amplifier composed of P Channel transistor Q _S1, Q _S2, Q _SN is N Channel transistor a driving transistor of the sense amplifier formed by Q _S3, Q _S4. Φ _P is a precharge signal.

FIG. 4 shows the operation timing of the circuit shown in FIG. In the figure, the data lines D, VL / 2 are precharged. Here, when the word line signal W rises, Q _M
There turned on signal data lines that were gills蓄Wa to C _S, appears at D. Next, when the sense amplifier drive signals φ _SP and φ _SN are input, the sense amplifier operates and the previous signal is amplified. In this case Q _S1, Q _S2 charges the data line capacitance C _D of the High side to the VL, Q _S3, Q _S4 discharges the data line capacitance C _D of the Low side to V _SS. The current waveform _ID when the data line is charged is φ ₁ , φ ₂ , φ ₃
At the same time, the voltage limiter responds quickly to the load fluctuation, so that the voltage limiter rises rapidly as shown by the broken line in FIG. 4 and gradually decreases. Therefore, the peak value increases. This sudden change in the current fluctuates the power supply voltage and causes a malfunction of the device. On the other hand, in the present embodiment, at an appropriate time interval after driving the sense amplifier,
Since φ ₁ , φ ₂ , and φ ₃ are started, the response speed of the amplifier is slow at first, so the driving capability of the voltage limiter is reduced, and the peak immediately after charging is reduced. Becomes

On the other hand, the current consumption of the amplifier itself is also reduced by the amount indicated by the hatched portion in FIG.

As described above, according to this embodiment, there is an effect of reducing the peak current at the time of charging. Further, the power consumption of the voltage limiter itself can be reduced.

Further, if the voltage limiter of the present embodiment is applied to a circuit having a plurality of loads having different sizes, an optimal current consumption can be selected according to each load capacity, so that low power consumption can be achieved. Become.

FIG. 5 shows a fourth embodiment of the present invention. The feature is that a plurality of voltage limiter circuits VC1 of FIG. 1 are connected in parallel, and the current control signals of each circuit are separated by separate signals (φ ₁ ,
φ ₂ , φ ₃ ). Thereby, the same effect as that of the second embodiment can be obtained. Further, since only the same circuits are connected in parallel, only one circuit needs to be laid out, and the number of design steps can be reduced.

FIG. 6 is a circuit for generating a current control signal for the differential amplifier. The feature of the present embodiment is that the amount of change in the output voltage of the limiter is detected, and a current value having a magnitude corresponding thereto can be automatically selected.

In this figure, DA is a differential amplifier as shown in FIG. 8, VF ₁ , VF ₂ ,
VF ₃ is VL> VF ₁ by the reference voltage> VF _2> relationship of VF _3. Further, channel width W ₅₀ of the current control transistor Q _50, Q ₅₁ Q _52,
W ₅₁ and W ₅₂ have a relationship of W ₅₀ ≧ W ₅₁ ≧ W ₅₂ .

The operation of this circuit will be described with reference to FIG. When the drive signal φ is applied to the load L, a current flows through L and VLO decreases. Here, if if VLO is Natsuta below VF _8, VF ₁ from the relation described above, VF ₂ becomes higher than the negative input because from the higher three differential amplifiers all positive inputs VLO phi _A,
Both φ _B and φ _C change from a low state to a high state. Then, Q ₅₀ , Q ₅₁ , and Q ₅₂ are all turned on, the maximum current flows through the differential amplifier VC3, and the limiter has the maximum drive capability. Also, if VLO is VF ₁ and VF ₂
, Only φ _C becomes High and Q ₅₂
Only turn on. Also, if VLO is if reduced to a voltage between the VF ₂ and VF _3, φ _B1, φ _c is turned on becomes High, the Q _51, Q _52.

As described above, according to the present embodiment, it is possible to automatically turn on more current control transistors as the amount of decrease in VLO increases, and conversely, turn on less as the amount decreases. Therefore, there is no need to keep the current control transistor on for a longer time than the actual charging time due to power supply voltage fluctuations and process variations as in the past.
Lower power consumption can be achieved. Further, since it is not necessary to wire a large number of current control signals to the limiter, the layout area can be reduced accordingly. Further, since it is not necessary to know the time change of the current flowing through the load, the circuit design becomes easy.

FIG. 7 shows a complementary MOS (hereinafter abbreviated as CMOS) inverter circuit INV shown in FIG. 9 inserted after the differential amplifier DA of the embodiment shown in FIG. As a result, the phase of the output is reversed, so that the input to DA is reversed from that in FIG.

The feature of this embodiment is that the gain of the control signal generation circuit is increased by the inverter circuit. This VL, VF _1, V
Since the difference between F ₂ and VF ₃ can be reduced, the amount of variation in VLO can be further reduced. The output voltage of the CMOS inverter circuit is V _CC at high level and V _SS at low level.
Therefore, the current control transistors Q ₅₀ , Q ₅₁ , and Q ₅₂ can be completely turned on and off, and the power consumption can be further reduced.

The description of the present invention has been made by taking the MIS type LSI as an example, but this is a bipolar type LSI or a Bi type
-A similar effect can be obtained for a CMOS type LSI.

〔The invention's effect〕

According to the present invention, the differential amplifier of the voltage limiter circuit includes:
Even if the input voltage is equal to the power supply voltage, a large current can flow. Therefore, it is possible to realize a voltage limiter circuit that operates at high speed even when the power supply voltage drops and becomes equal to the output voltage of the voltage limiter.

In addition, since the driving ability can be finely controlled according to the state of the load, power consumption can be reduced.

[Brief description of the drawings]

1, 2, 3, 5, 6, 7, 8, and 9 are diagrams showing an embodiment of the present invention, and FIG. 4 is a diagram of FIG. FIG. 10 is a diagram showing operation waveforms of the embodiment, FIG. 10 is a diagram showing operation waveforms of FIGS. 6 and 7, and FIG. 11 is a diagram showing a conventional example. 1 ...... semiconductor chip, VC1, VC2, VC3 ...... voltage Rimitsuta circuit, L, L1, L2, L3 ...... load circuit, V _CC, V _SS ...... external power supply _{voltage, VL, VL 1, VL 2} ...... Rimitsuta reference _{voltages, φ 1, φ 2, φ} 3, φ
_A , φ _B , φ _C ... load drive signals, φ ₁ ′, ₃ ′,
_{1 ', φ 3,' φ} 1 ", φ 2", φ 3 ", ...... differential amplifier current control _{signal, VLO, VLO 1, VLO 2} ...... Rimitsuta output voltage, MCA ...... memory cell array, D, ...... Data line, W
…… Word line, φ _P …… Precharge signal, φ _SP , φ _SN
…… Sense amplifier drive signal, C _D … Data line capacitance, C _S …
… Memory cell capacity, CSP …… P channel sense amplifier transistor common source line, CSN… N channel sense amplifier transistor common source line, Q ₁ , Q ₂ , Q ₇ , Q _SP , Q _S1 ,
Q _S2 , Q ₈ , Q ₉ , Q ₁₀ , Q ₁₁ ...... P channel MOS transistor,
Q ₃ , Q ₄ , Q ₅ , Q ₆ , Q ₁₂ , Q ₁₃ , Q _SN , Q _S3 , Q _S4 , Q _M , Q _M , Q ₅₀ , Q ₅₁ , Q ₅₂ ……
N-channel MOS transistor, DA ... Differential amplifier, INV ...
... complementary MOS inverter _{circuit, VF 1, VF 2, VF} 3 ...... current control circuit reference voltage.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiyoo Ito 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Masashi Horiguchi 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Inside the Central Research Laboratory of the Works (72) Inventor Yoshinobu Nakagome 1-280 Higashi Koikekubo, Kokubunji, Tokyo, Japan Inside the Central Research Center of Hitachi, Ltd. (72) Inventor Masakazu Aoki 1-280, Higashi Koikebo, Kokubunji, Tokyo, Hitachi, Ltd. In-house (56) References JP-A-62-11990 (JP, A) JP-A-57-172761 (JP, A)

Claims (5)

(57) [Claims] 1. A differential amplifier having a first input and a second input, an output transistor having an output connected to the gate of the differential amplifier, and a source / drain path of the output transistor. And an internal circuit supplied with current through the differential amplifier circuit, wherein a voltage applied to the internal circuit is fed back to the first input of the differential amplifier circuit, and the second input is a reference A semiconductor integrated circuit to which a voltage is input and a current flowing through the differential amplifier circuit is controlled in two or more stages while the internal circuit is activated. A plurality of word lines; a plurality of data lines intersecting the plurality of word lines; and a plurality of word lines provided at desired intersections of the plurality of word lines and the plurality of data lines. And a plurality of sense amplifiers connected to each of the plurality of data lines, wherein a drive current of the sense amplifier is supplied via a source / drain path of the output transistor. The semiconductor integrated circuit according to claim 1, wherein: 3. The voltage applied to the internal circuit is input to one input of a differential amplifier and is compared with a reference voltage input to the other input of the differential amplifier. 2. The method according to claim 1, wherein a current flowing through the differential amplifier circuit is controlled.
A semiconductor integrated circuit according to any one of the above items. 4. A current flowing through the differential amplifier circuit is supplied via source / drain paths of first and second transistors; a gate of the first transistor is connected to a predetermined potential; 4. The semiconductor integrated circuit according to claim 3, wherein an output of said differential amplifier is connected to a gate of said transistor. 5. The first circuit according to claim 1, wherein said internal circuit is a dynamic random access memory.
Item 5. The semiconductor integrated circuit according to any one of Items 1 to 4.