JPS5634184A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS5634184A
JPS5634184A JP10719579A JP10719579A JPS5634184A JP S5634184 A JPS5634184 A JP S5634184A JP 10719579 A JP10719579 A JP 10719579A JP 10719579 A JP10719579 A JP 10719579A JP S5634184 A JPS5634184 A JP S5634184A
Authority
JP
Japan
Prior art keywords
nonselection
memory cell
load
channel
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10719579A
Other languages
Japanese (ja)
Other versions
JPS6235191B2 (en
Inventor
Osamu Minato
Toshiaki Masuhara
Toshio Sasaki
Hideaki Nakamura
Kiyobumi Uchibori
Norimasa Yasui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP10719579A priority Critical patent/JPS5634184A/en
Publication of JPS5634184A publication Critical patent/JPS5634184A/en
Publication of JPS6235191B2 publication Critical patent/JPS6235191B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

PURPOSE:To obtain high operation margin and reliability, by preventing the inversion of information at nonselection memory cell, through the conduction of MOS FET for load at nonselection of data line. CONSTITUTION:The unit is provided with N channel MOSFET70-73 for column selection switch, N channel MOSFET101-104 acting as the load for nonselection memory cell at readout, and N channel MOSFET22, 23 for bias of common data lines 9, 10. Further, when the terminal 7 is at low level and the cell 3 is at nonselection, the terminal 105 is at high level, FET101, 102 are conductive and they are the load to the memory cell. As a result, the potential difference between the data lines 16, 17 and between the stored nodes in the cell are around the same in case with the memory cell to increase the operation margin.
JP10719579A 1979-08-24 1979-08-24 Semiconductor memory Granted JPS5634184A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10719579A JPS5634184A (en) 1979-08-24 1979-08-24 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10719579A JPS5634184A (en) 1979-08-24 1979-08-24 Semiconductor memory

Publications (2)

Publication Number Publication Date
JPS5634184A true JPS5634184A (en) 1981-04-06
JPS6235191B2 JPS6235191B2 (en) 1987-07-31

Family

ID=14452879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10719579A Granted JPS5634184A (en) 1979-08-24 1979-08-24 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS5634184A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121688A (en) * 1982-12-28 1984-07-13 Toshiba Corp Static random access memory
JPS60117490A (en) * 1983-11-29 1985-06-24 Nec Ic Microcomput Syst Ltd Semiconductor memory
JPS61264590A (en) * 1985-05-17 1986-11-22 Matsushita Electric Ind Co Ltd Signal generating circuit
JPS63144488A (en) * 1986-12-06 1988-06-16 Fujitsu Ltd Semiconductor storage device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5116733A (en) * 1974-08-01 1976-02-10 Gewerk Eisenhuette Westfalia
JPS5329037A (en) * 1976-08-30 1978-03-17 Toshiba Corp Mos random access memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5116733A (en) * 1974-08-01 1976-02-10 Gewerk Eisenhuette Westfalia
JPS5329037A (en) * 1976-08-30 1978-03-17 Toshiba Corp Mos random access memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121688A (en) * 1982-12-28 1984-07-13 Toshiba Corp Static random access memory
JPS60117490A (en) * 1983-11-29 1985-06-24 Nec Ic Microcomput Syst Ltd Semiconductor memory
JPS61264590A (en) * 1985-05-17 1986-11-22 Matsushita Electric Ind Co Ltd Signal generating circuit
JPS63144488A (en) * 1986-12-06 1988-06-16 Fujitsu Ltd Semiconductor storage device

Also Published As

Publication number Publication date
JPS6235191B2 (en) 1987-07-31

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