JPS54148339A - Memory device - Google Patents

Memory device

Info

Publication number
JPS54148339A
JPS54148339A JP5676478A JP5676478A JPS54148339A JP S54148339 A JPS54148339 A JP S54148339A JP 5676478 A JP5676478 A JP 5676478A JP 5676478 A JP5676478 A JP 5676478A JP S54148339 A JPS54148339 A JP S54148339A
Authority
JP
Japan
Prior art keywords
terminal
circuit
read
output
inversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5676478A
Other languages
Japanese (ja)
Other versions
JPS6217320B2 (en
Inventor
Jiyouichi Nokubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5676478A priority Critical patent/JPS54148339A/en
Publication of JPS54148339A publication Critical patent/JPS54148339A/en
Publication of JPS6217320B2 publication Critical patent/JPS6217320B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To avoid the inversion of the data input at the early writing time and thus to accelerate the operation of the semiconductor memory device by providing the circuit part which forms the inforamtion transmission line between the read/ write terminal and the input/output common terminal featuring the plural functions. CONSTITUTION:The 1st terminal features a structure in which read/write terminal R/W is connected to the bases of transistor TrQ1 and Q2 connected to the digit line of semiconductor memory device C; and the I/O common terminal featuring the plural functions is connected to the 2nd terminal. Read/write control circuit 50 contains the 1st and 2nd terminals of such constitution. Furthermore, reading circuit 40 containing inversion gate G6 possessing sense amplifier SA plus output O1 and O2 is provided to the collectors of TrQ1 and Q2. Thus, output O2 which is the same phase as data output O1 connected to the 2nd terminal is read out from circuit 40 and then fed back to circuit 50. And gate G3 and G4 of circuit 50 are not put under the writing state even with the writing state of terminal R/W, thus preventing the inversion of the data input.
JP5676478A 1978-05-12 1978-05-12 Memory device Granted JPS54148339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5676478A JPS54148339A (en) 1978-05-12 1978-05-12 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5676478A JPS54148339A (en) 1978-05-12 1978-05-12 Memory device

Publications (2)

Publication Number Publication Date
JPS54148339A true JPS54148339A (en) 1979-11-20
JPS6217320B2 JPS6217320B2 (en) 1987-04-16

Family

ID=13036553

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5676478A Granted JPS54148339A (en) 1978-05-12 1978-05-12 Memory device

Country Status (1)

Country Link
JP (1) JPS54148339A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56119296A (en) * 1980-02-27 1981-09-18 Hitachi Ltd Washing machine
JPS56137582A (en) * 1980-03-31 1981-10-27 Chiyou Lsi Gijutsu Kenkyu Kumiai Write-in input circuit
JPS63119094A (en) * 1987-06-05 1988-05-23 Hitachi Ltd Memory circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56119296A (en) * 1980-02-27 1981-09-18 Hitachi Ltd Washing machine
JPS56137582A (en) * 1980-03-31 1981-10-27 Chiyou Lsi Gijutsu Kenkyu Kumiai Write-in input circuit
JPS63119094A (en) * 1987-06-05 1988-05-23 Hitachi Ltd Memory circuit
JPH035000B2 (en) * 1987-06-05 1991-01-24 Hitachi Ltd

Also Published As

Publication number Publication date
JPS6217320B2 (en) 1987-04-16

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