JPS5562592A - Non-volatile semiconductor memory control circuit - Google Patents

Non-volatile semiconductor memory control circuit

Info

Publication number
JPS5562592A
JPS5562592A JP13478778A JP13478778A JPS5562592A JP S5562592 A JPS5562592 A JP S5562592A JP 13478778 A JP13478778 A JP 13478778A JP 13478778 A JP13478778 A JP 13478778A JP S5562592 A JPS5562592 A JP S5562592A
Authority
JP
Japan
Prior art keywords
time
terminal
circuit
address
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13478778A
Other languages
Japanese (ja)
Other versions
JPS5841600B2 (en
Inventor
Masao Furuta
Yoshihiro Izumi
Junichi Hirase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP53134787A priority Critical patent/JPS5841600B2/en
Publication of JPS5562592A publication Critical patent/JPS5562592A/en
Publication of JPS5841600B2 publication Critical patent/JPS5841600B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To prevent degradation of the storage state of a memory and simplify peripheral circuits by constituting a circuit so that a read signal output may be generated only when an address selection signal is applied to the address input terminal. CONSTITUTION:The address selection signal applied to terminal 4 is applied to AND gate circuits 81-8n and is inputted to address decoder circuit 2 by the address input enable signal applied to terminal 15 at a read time. Then, the output of circuit 2 is applied to one input terminals of AND gate circuits 71-7n, and further, the output of OR gate circuit 9 is applied to the other input terminals of circuits 71-7n. Meanwhile, in case that the logical level at input terminal A of AND gate circuit 10 becomes ''1'' at time t1 by the signal applied to terminal 15, the logical level at input terminal B becomes ''0'' at time t2 after time t1. Therefore, pulse signals are generated at output terminal C of circuit 10 from time t1 to time t2. By using these signals as read signals, read signals can be generated automatically only at an address selection time.
JP53134787A 1978-10-31 1978-10-31 Non-volatile semiconductor memory control circuit Expired JPS5841600B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53134787A JPS5841600B2 (en) 1978-10-31 1978-10-31 Non-volatile semiconductor memory control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53134787A JPS5841600B2 (en) 1978-10-31 1978-10-31 Non-volatile semiconductor memory control circuit

Publications (2)

Publication Number Publication Date
JPS5562592A true JPS5562592A (en) 1980-05-12
JPS5841600B2 JPS5841600B2 (en) 1983-09-13

Family

ID=15136532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53134787A Expired JPS5841600B2 (en) 1978-10-31 1978-10-31 Non-volatile semiconductor memory control circuit

Country Status (1)

Country Link
JP (1) JPS5841600B2 (en)

Also Published As

Publication number Publication date
JPS5841600B2 (en) 1983-09-13

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