JPS55135960A - Micro-computer - Google Patents

Micro-computer

Info

Publication number
JPS55135960A
JPS55135960A JP4381879A JP4381879A JPS55135960A JP S55135960 A JPS55135960 A JP S55135960A JP 4381879 A JP4381879 A JP 4381879A JP 4381879 A JP4381879 A JP 4381879A JP S55135960 A JPS55135960 A JP S55135960A
Authority
JP
Japan
Prior art keywords
rom
terminal
signal
external
ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4381879A
Other languages
Japanese (ja)
Inventor
Takeshi Shiromoto
Norio Takenouchi
Hiroshi Mori
Shinichi Kitano
Kazuo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP4381879A priority Critical patent/JPS55135960A/en
Publication of JPS55135960A publication Critical patent/JPS55135960A/en
Pending legal-status Critical Current

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  • Microcomputers (AREA)

Abstract

PURPOSE: To enhance the function of a micro-computer, by utilizing the terminal which provides a timing signal for accessing the external memory as a general- purpose output terminal in the state that the external memory is not connected, and by efficiently making the most of the terminal of LSI.
CONSTITUTION: In the 1 chip LSI circuit which transfers a signal between the micro-computer and the external memory is provided the output terminal 13 which gives a timing signal for commanding the write operation to the external ROM or the external RAM, or the read operation from the external part. And when a signal of the terminal 13 is in a low level, the instruction stored in ROM is written through the input terminals 3W10 and 12, subsequently the instruction address of a signal which is read out in ROM is provided to ROM through the output terminals 26W37 of LSI, and the instruction is read out by commanding a desired address. And the terminal 13 changes its output level to a high level or a low level by the command from ROM or RAM, and is made a general-purpose output terminal in the state that ROM or RAM is not connected.
COPYRIGHT: (C)1980,JPO&Japio
JP4381879A 1979-04-10 1979-04-10 Micro-computer Pending JPS55135960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4381879A JPS55135960A (en) 1979-04-10 1979-04-10 Micro-computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4381879A JPS55135960A (en) 1979-04-10 1979-04-10 Micro-computer

Publications (1)

Publication Number Publication Date
JPS55135960A true JPS55135960A (en) 1980-10-23

Family

ID=12674316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4381879A Pending JPS55135960A (en) 1979-04-10 1979-04-10 Micro-computer

Country Status (1)

Country Link
JP (1) JPS55135960A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583054A (en) * 1981-06-30 1983-01-08 Nec Corp Single chip microcomputer
JPS6246361A (en) * 1985-08-23 1987-02-28 Hitachi Ltd Data processor
US5497482A (en) * 1985-08-23 1996-03-05 Hitachi, Ltd. Data processor in which external sync signal may be selectively inhibited

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583054A (en) * 1981-06-30 1983-01-08 Nec Corp Single chip microcomputer
JPH03668B2 (en) * 1981-06-30 1991-01-08 Nippon Electric Co
JPS6246361A (en) * 1985-08-23 1987-02-28 Hitachi Ltd Data processor
US5497482A (en) * 1985-08-23 1996-03-05 Hitachi, Ltd. Data processor in which external sync signal may be selectively inhibited

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