JPS5512567A - Memory protection circuit - Google Patents

Memory protection circuit

Info

Publication number
JPS5512567A
JPS5512567A JP8513778A JP8513778A JPS5512567A JP S5512567 A JPS5512567 A JP S5512567A JP 8513778 A JP8513778 A JP 8513778A JP 8513778 A JP8513778 A JP 8513778A JP S5512567 A JPS5512567 A JP S5512567A
Authority
JP
Japan
Prior art keywords
read
memories
computer
state
protection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8513778A
Other languages
Japanese (ja)
Inventor
Fumio Tsujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8513778A priority Critical patent/JPS5512567A/en
Publication of JPS5512567A publication Critical patent/JPS5512567A/en
Pending legal-status Critical Current

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  • Storage Device Security (AREA)

Abstract

PURPOSE: To prevent the malfunction of memory efficiently, by making the memory into read state with the manual switch and the automatic switch which is controlled with the computer.
CONSTITUTION: The circuit provides the manual selection switches 11 to 13 which can compulsively make the memories 2 to 4 into read state without being affected with the state of the read/write signal from the computer 1, and the automatic selection switches 18 to 20 which can compulsively make the memories 2 to 4 into read with the signal from the computer 1. Further, when at least one of the switches 11 to 13 and 18 to 20 is in read state, connection is made so that the memories 2 to 4 are in read state.
COPYRIGHT: (C)1980,JPO&Japio
JP8513778A 1978-07-14 1978-07-14 Memory protection circuit Pending JPS5512567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8513778A JPS5512567A (en) 1978-07-14 1978-07-14 Memory protection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8513778A JPS5512567A (en) 1978-07-14 1978-07-14 Memory protection circuit

Publications (1)

Publication Number Publication Date
JPS5512567A true JPS5512567A (en) 1980-01-29

Family

ID=13850256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8513778A Pending JPS5512567A (en) 1978-07-14 1978-07-14 Memory protection circuit

Country Status (1)

Country Link
JP (1) JPS5512567A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63140495A (en) * 1986-12-03 1988-06-13 Nec Corp Write inhibition circuit
JPH01155545U (en) * 1988-04-19 1989-10-25

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63140495A (en) * 1986-12-03 1988-06-13 Nec Corp Write inhibition circuit
JPH01155545U (en) * 1988-04-19 1989-10-25

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