JPS5668838A - Data control unit - Google Patents

Data control unit

Info

Publication number
JPS5668838A
JPS5668838A JP14622079A JP14622079A JPS5668838A JP S5668838 A JPS5668838 A JP S5668838A JP 14622079 A JP14622079 A JP 14622079A JP 14622079 A JP14622079 A JP 14622079A JP S5668838 A JPS5668838 A JP S5668838A
Authority
JP
Japan
Prior art keywords
executed
circuit
memory
microorder
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14622079A
Other languages
Japanese (ja)
Inventor
Kazutoshi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14622079A priority Critical patent/JPS5668838A/en
Publication of JPS5668838A publication Critical patent/JPS5668838A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To facilitate both the development of program and its storage into the main memory, by performing these actions via the program control memory including the machine word and the microorder.
CONSTITUTION: The machine word 12 is designated by the memory address register MAR16 of the main memory 11 to be stored in the memory data register MDR20 through the AND circuit 18 and then executed to set the FF17. With this action, the circuit 18 and the AND circuit 19 become nonconductive and conductive each. When the MAR 16 designates the next address, the microorder 14 read next is stored in the intermediate register 21 via the circuit 19 and then stored in the storage data register 22 to be executed. After this several microorders are executed through the control memory, and then the final microorder 15 is executed. Thus the circuits 18 and 19 are turned conductive and nonconductive respectively to secure a reset to the original state. As a result, both the development of program and its storage into the main memory can be facilitated.
COPYRIGHT: (C)1981,JPO&Japio
JP14622079A 1979-11-12 1979-11-12 Data control unit Pending JPS5668838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14622079A JPS5668838A (en) 1979-11-12 1979-11-12 Data control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14622079A JPS5668838A (en) 1979-11-12 1979-11-12 Data control unit

Publications (1)

Publication Number Publication Date
JPS5668838A true JPS5668838A (en) 1981-06-09

Family

ID=15402818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14622079A Pending JPS5668838A (en) 1979-11-12 1979-11-12 Data control unit

Country Status (1)

Country Link
JP (1) JPS5668838A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59163640A (en) * 1983-03-09 1984-09-14 Panafacom Ltd Data processing system
JPS61114341A (en) * 1984-10-01 1986-06-02 バロ−ス・コ−ポレ−シヨン Processing system
JPS6453232A (en) * 1984-10-01 1989-03-01 Unisys Corp Processing system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59163640A (en) * 1983-03-09 1984-09-14 Panafacom Ltd Data processing system
JPS61114341A (en) * 1984-10-01 1986-06-02 バロ−ス・コ−ポレ−シヨン Processing system
JPS6453232A (en) * 1984-10-01 1989-03-01 Unisys Corp Processing system

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