JPS5642857A - Address control device - Google Patents

Address control device

Info

Publication number
JPS5642857A
JPS5642857A JP11897779A JP11897779A JPS5642857A JP S5642857 A JPS5642857 A JP S5642857A JP 11897779 A JP11897779 A JP 11897779A JP 11897779 A JP11897779 A JP 11897779A JP S5642857 A JPS5642857 A JP S5642857A
Authority
JP
Japan
Prior art keywords
field
contents
selection
address
microinstruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11897779A
Other languages
Japanese (ja)
Inventor
Hisanobu Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11897779A priority Critical patent/JPS5642857A/en
Publication of JPS5642857A publication Critical patent/JPS5642857A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the increase of the microinstruction length, by securing the working of the selected field of the microinstruction register as both the address part and the register selection part each.
CONSTITUTION: The microinstruction given from the control memory 22 is stored in the microinstruction register 11 containing the operation field OP, the mask field MSR, the selection field A&S and the address field ADR each. Then either one of the higher-rank and lower-rank bits of the mask register 13 is selected through the selection circuit 30 according to the contents of the field A&S. After this, either one of the output of the circuit 30 and the contents of the field A&S is selected by the selection circuit 40 according to the contents of the field MSR. Receiving this selection result, the address selection circuit 12 selects either one of this result and the contents of the field ADR according to the contents of the field OP and then gives it to the control memory circuit 22 in the form of the address. Thus the increase of the order length can be prevented.
COPYRIGHT: (C)1981,JPO&Japio
JP11897779A 1979-09-17 1979-09-17 Address control device Pending JPS5642857A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11897779A JPS5642857A (en) 1979-09-17 1979-09-17 Address control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11897779A JPS5642857A (en) 1979-09-17 1979-09-17 Address control device

Publications (1)

Publication Number Publication Date
JPS5642857A true JPS5642857A (en) 1981-04-21

Family

ID=14749955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11897779A Pending JPS5642857A (en) 1979-09-17 1979-09-17 Address control device

Country Status (1)

Country Link
JP (1) JPS5642857A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60139446A (en) * 1983-12-27 1985-07-24 東海金属株式会社 Delustered evaporated sheet
JPS62109134A (en) * 1985-11-08 1987-05-20 Nec Corp Microprogram controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60139446A (en) * 1983-12-27 1985-07-24 東海金属株式会社 Delustered evaporated sheet
JPS6313830B2 (en) * 1983-12-27 1988-03-28 Tokai Kinzoku Kk
JPS62109134A (en) * 1985-11-08 1987-05-20 Nec Corp Microprogram controller

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