JPS551675A - Memory protect control system - Google Patents

Memory protect control system

Info

Publication number
JPS551675A
JPS551675A JP7520878A JP7520878A JPS551675A JP S551675 A JPS551675 A JP S551675A JP 7520878 A JP7520878 A JP 7520878A JP 7520878 A JP7520878 A JP 7520878A JP S551675 A JPS551675 A JP S551675A
Authority
JP
Japan
Prior art keywords
protect
memory
logical product
register
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7520878A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7520878A priority Critical patent/JPS551675A/en
Publication of JPS551675A publication Critical patent/JPS551675A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the memory protect control and to decrease the protect bit, by taking the logical product between the protect bit selected and the ouput of specified memory usage device, through setting the protect data from the memory usage device to the memory protect register.
CONSTITUTION: First, protect data is set to the protect register 1 from a given processor. Next, when memory is accessed, the address selector 2 selects the protect bit set to the protect register 1. The logical product between the protect bit selected and the output from the processor A or B, is taken at the AND circuit 3 or 4. When the logical product is taken, it is judged as protect error. The protect error is outputted through the OR circuit 5.
COPYRIGHT: (C)1980,JPO&Japio
JP7520878A 1978-06-21 1978-06-21 Memory protect control system Pending JPS551675A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7520878A JPS551675A (en) 1978-06-21 1978-06-21 Memory protect control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7520878A JPS551675A (en) 1978-06-21 1978-06-21 Memory protect control system

Publications (1)

Publication Number Publication Date
JPS551675A true JPS551675A (en) 1980-01-08

Family

ID=13569538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7520878A Pending JPS551675A (en) 1978-06-21 1978-06-21 Memory protect control system

Country Status (1)

Country Link
JP (1) JPS551675A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5992929U (en) * 1982-12-09 1984-06-23 株式会社明電舎 Memory monitoring device for DMA device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5992929U (en) * 1982-12-09 1984-06-23 株式会社明電舎 Memory monitoring device for DMA device

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