JPS5556220A - Data input system - Google Patents

Data input system

Info

Publication number
JPS5556220A
JPS5556220A JP13023378A JP13023378A JPS5556220A JP S5556220 A JPS5556220 A JP S5556220A JP 13023378 A JP13023378 A JP 13023378A JP 13023378 A JP13023378 A JP 13023378A JP S5556220 A JPS5556220 A JP S5556220A
Authority
JP
Japan
Prior art keywords
data
circuit
unit
transfer
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13023378A
Other languages
Japanese (ja)
Inventor
Shigehiko Watabe
Hirotaka Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13023378A priority Critical patent/JPS5556220A/en
Publication of JPS5556220A publication Critical patent/JPS5556220A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make it possible to transfer initial control data with good efficiency by irreducible numbers of memory elements and driver circuits, by connecting a shuft register circuit to a data processor.
CONSTITUTION: Data processor 1 sends a request to transfer initial data to control circuit 16, which outputs an initial address to memory element 4. Next, circuit 16 outputs a transfer control signal to driver circuit 8, which reads data by its constitution units, e.g. four bits from element 4 and then transfers it to unit 1. Unit 1 sets this data to shift register circuit 18 and then shifts it by four bits, for example. Next, unit 1 sends a request to transfer to circuit 16 again to add "1" to address counter 17 and outputs its value to element 4 as a memory address. As a result, it is similarly stored in circuit 18 and then shifted together with the previous data at a time. This operation is repeated four times to store 16-bit initial data in circuit 18 and this data is supplied to unit 1.
COPYRIGHT: (C)1980,JPO&Japio
JP13023378A 1978-10-23 1978-10-23 Data input system Pending JPS5556220A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13023378A JPS5556220A (en) 1978-10-23 1978-10-23 Data input system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13023378A JPS5556220A (en) 1978-10-23 1978-10-23 Data input system

Publications (1)

Publication Number Publication Date
JPS5556220A true JPS5556220A (en) 1980-04-24

Family

ID=15029286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13023378A Pending JPS5556220A (en) 1978-10-23 1978-10-23 Data input system

Country Status (1)

Country Link
JP (1) JPS5556220A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6097439A (en) * 1983-11-02 1985-05-31 Oki Electric Ind Co Ltd Microprocessor circuit
JPS60215260A (en) * 1984-04-10 1985-10-28 Mitsubishi Electric Corp Central processor
JPH01282637A (en) * 1988-05-10 1989-11-14 Hitachi Constr Mach Co Ltd Program loading system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6097439A (en) * 1983-11-02 1985-05-31 Oki Electric Ind Co Ltd Microprocessor circuit
JPS60215260A (en) * 1984-04-10 1985-10-28 Mitsubishi Electric Corp Central processor
JPH01282637A (en) * 1988-05-10 1989-11-14 Hitachi Constr Mach Co Ltd Program loading system

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