JPS5674762A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5674762A
JPS5674762A JP15208679A JP15208679A JPS5674762A JP S5674762 A JPS5674762 A JP S5674762A JP 15208679 A JP15208679 A JP 15208679A JP 15208679 A JP15208679 A JP 15208679A JP S5674762 A JPS5674762 A JP S5674762A
Authority
JP
Japan
Prior art keywords
register
signal
circuit
address
bpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15208679A
Other languages
Japanese (ja)
Other versions
JPS6046461B2 (en
Inventor
Yoshio Kiryu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP54152086A priority Critical patent/JPS6046461B2/en
Priority to US06/210,172 priority patent/US4459688A/en
Publication of JPS5674762A publication Critical patent/JPS5674762A/en
Publication of JPS6046461B2 publication Critical patent/JPS6046461B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Dram (AREA)

Abstract

PURPOSE: To make it possible to increase the speed of the operation of a memory unit having a selecting circuit which selects input from access sources, by receiving access requests from access sources and inputs accompanying them at the same time.
CONSTITUTION: Since selective signal 27 of arithmetic processor BPU shows "1" when access request 10 is made, selecting circuit 8 selects address 18 from processor BPU and sends it to output 20. While request 10 is set in register 4, output 20 of circuit 8 is also set in address register 9 by trigger signal 31. If register 4 is set at this time, output signal 31 of AND circuit 26 is changed into "0" from now on by signal 14, so the update of register 9 is inhibited to hold address 18 in register 9. Thus, the operation speed of the memory circuit can be increased by receiving an access request and address signal from processor BPU at the same time.
COPYRIGHT: (C)1981,JPO&Japio
JP54152086A 1979-11-26 1979-11-26 Access request selection circuit Expired JPS6046461B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP54152086A JPS6046461B2 (en) 1979-11-26 1979-11-26 Access request selection circuit
US06/210,172 US4459688A (en) 1979-11-26 1980-11-25 Access request selecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54152086A JPS6046461B2 (en) 1979-11-26 1979-11-26 Access request selection circuit

Publications (2)

Publication Number Publication Date
JPS5674762A true JPS5674762A (en) 1981-06-20
JPS6046461B2 JPS6046461B2 (en) 1985-10-16

Family

ID=15532733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54152086A Expired JPS6046461B2 (en) 1979-11-26 1979-11-26 Access request selection circuit

Country Status (2)

Country Link
US (1) US4459688A (en)
JP (1) JPS6046461B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8430004D0 (en) * 1984-11-28 1985-01-09 Plessey Co Plc Microprocessor interface device
US5471607A (en) * 1993-04-22 1995-11-28 Analog Devices, Inc. Multi-phase multi-access pipeline memory system
US20030168368A1 (en) * 2002-01-31 2003-09-11 Terrell Michael A. Roll product shipping, storage, and display carton

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3810129A (en) * 1972-10-19 1974-05-07 Ibm Memory system restoration

Also Published As

Publication number Publication date
JPS6046461B2 (en) 1985-10-16
US4459688A (en) 1984-07-10

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