JPS55115122A - Priority control system - Google Patents

Priority control system

Info

Publication number
JPS55115122A
JPS55115122A JP2067479A JP2067479A JPS55115122A JP S55115122 A JPS55115122 A JP S55115122A JP 2067479 A JP2067479 A JP 2067479A JP 2067479 A JP2067479 A JP 2067479A JP S55115122 A JPS55115122 A JP S55115122A
Authority
JP
Japan
Prior art keywords
memory
cpu
usage request
usage
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2067479A
Other languages
Japanese (ja)
Inventor
Masaki Murayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2067479A priority Critical patent/JPS55115122A/en
Publication of JPS55115122A publication Critical patent/JPS55115122A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE: To enable the memory access of CPU in minimum time, by selecting the usage of CPU, when the usage request from CPU is present with the memory usage request for the direct memory unit after the end of memory cycle.
CONSTITUTION: In the electronic computer in which the usage request of memory from the CPU and direct memory access DMA unit is separately and directly made, FF53 receives the memory usage request signal FDREQ1 from DMA unit and FF55 delivers the selection signal FDSEL1 to the main memory. On the other hand, the AND circuit 58 receives the CPU request signal DPREQ and delivers it to the AND circuit 59 via FF57, it is logically multiplied with the DMA request signal and fed to the input terminal of the circuit 58, and the output is logically summed 60 with CPU request signal via FF57. Thus, after the end of memory cycle, if the usage request of memory for DMA unit is uncertain and the memory usage request from CPU is present, the memory access of CPU is made in minimum time.
COPYRIGHT: (C)1980,JPO&Japio
JP2067479A 1979-02-26 1979-02-26 Priority control system Pending JPS55115122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2067479A JPS55115122A (en) 1979-02-26 1979-02-26 Priority control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2067479A JPS55115122A (en) 1979-02-26 1979-02-26 Priority control system

Publications (1)

Publication Number Publication Date
JPS55115122A true JPS55115122A (en) 1980-09-04

Family

ID=12033737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2067479A Pending JPS55115122A (en) 1979-02-26 1979-02-26 Priority control system

Country Status (1)

Country Link
JP (1) JPS55115122A (en)

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