JPS5582330A - Common bus control unit - Google Patents

Abstract

PURPOSE: To make it possible to secure the use of a bus even for a low-priority μCM, by providing the bus request signal of plural microcomputers μCN which are connected to a common bus, in two stages.

CONSTITUTION: Plural μCMs 101W104 are connected to a common bus connected to a memory unit, an I/O, etc., and each μCM is provided with an interface control circuit which controls the use of the common bus. Common bus use request signal RQ for access from a μCM to the memory unit is outputted to priority control circuit 105, and bus use permission signal AC is returned to the μCM for this request. When the common bus is used, output signal FR of the μCM becomes 0. When signal AC is not returned over a fixed time after transmission of signal RQ, is signal TQ is generated by the μCM and is inputted to priority control circuit 106. Then, output EO of circuit 106 becomes 0, input EI of circuit 105 becomes 0, signal TQ is outputted to circuit 106, and the bus use is permitted only for the μCM which receives return signal TA.

COPYRIGHT: (C)1980,JPO&Japio