JPS5672752A - Controller for occupation of common bus line - Google Patents

Controller for occupation of common bus line

Info

Publication number
JPS5672752A
JPS5672752A JP15044579A JP15044579A JPS5672752A JP S5672752 A JPS5672752 A JP S5672752A JP 15044579 A JP15044579 A JP 15044579A JP 15044579 A JP15044579 A JP 15044579A JP S5672752 A JPS5672752 A JP S5672752A
Authority
JP
Japan
Prior art keywords
priority
processors
controller
processor
ram5
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15044579A
Other languages
Japanese (ja)
Inventor
Junichi Komuro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP15044579A priority Critical patent/JPS5672752A/en
Publication of JPS5672752A publication Critical patent/JPS5672752A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Small-Scale Networks (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To prevent the efficiency of utilization of a processor low in priority from lowering by giving the lowest priority to a processor having been given the top priority last time while giving processors prescribed priorities.
CONSTITUTION: Processors 1W3 differing in function are connected to controller 4, which is further connected to common RAM5, so that respective processors 1W3 will be permitted selectively to perform processing. Processors 1W3, when to use RAM5, output request signals RQ1WRQ3 and according to the cyclic priority previously set to controller 4, common address bus AB and data bus DB are released to perform processing. When not less than two out of processors 1W3 send requests at the same time, one processor having been higher in priority is given the lowest priority by controller 4 according to the cyclic priority, thereby enabling the whole system to function smoothly.
COPYRIGHT: (C)1981,JPO&Japio
JP15044579A 1979-11-20 1979-11-20 Controller for occupation of common bus line Pending JPS5672752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15044579A JPS5672752A (en) 1979-11-20 1979-11-20 Controller for occupation of common bus line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15044579A JPS5672752A (en) 1979-11-20 1979-11-20 Controller for occupation of common bus line

Publications (1)

Publication Number Publication Date
JPS5672752A true JPS5672752A (en) 1981-06-17

Family

ID=15497083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15044579A Pending JPS5672752A (en) 1979-11-20 1979-11-20 Controller for occupation of common bus line

Country Status (1)

Country Link
JP (1) JPS5672752A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5875347A (en) * 1981-10-29 1983-05-07 Kokusai Electric Co Ltd Controlling method for end office transmission of conflict system data circuit
JPS6068738A (en) * 1983-09-24 1985-04-19 Oki Electric Ind Co Ltd Method for establishing data link
JPS60246471A (en) * 1984-05-22 1985-12-06 Yokogawa Hokushin Electric Corp Memory control device
JPS62113261A (en) * 1985-10-28 1987-05-25 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Arbitrator for computer system
JPS62263557A (en) * 1986-05-09 1987-11-16 Fujitsu Ltd Bus arbitration control system
JPS63106846A (en) * 1986-10-24 1988-05-11 Ando Electric Co Ltd Sequence designation circuit for extracting plural input signals
JPS63211059A (en) * 1987-02-27 1988-09-01 Meidensha Electric Mfg Co Ltd Precedence control system for computer system
JPH01270161A (en) * 1988-04-22 1989-10-27 Hitachi Ltd Common bus control system
JPH02115962A (en) * 1988-10-26 1990-04-27 K S D:Kk System for connecting computer device to its peripheral device
JPH0782476B2 (en) * 1987-05-01 1995-09-06 ディジタル イクイプメント コーポレーション A system that controls access to the reservation bus by multiple nodes
JP2008302781A (en) * 2007-06-06 2008-12-18 Univ Nagoya Communication method, communication system, and communication device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5875347A (en) * 1981-10-29 1983-05-07 Kokusai Electric Co Ltd Controlling method for end office transmission of conflict system data circuit
JPS6068738A (en) * 1983-09-24 1985-04-19 Oki Electric Ind Co Ltd Method for establishing data link
JPH0220188B2 (en) * 1983-09-24 1990-05-08 Oki Electric Ind Co Ltd
JPS60246471A (en) * 1984-05-22 1985-12-06 Yokogawa Hokushin Electric Corp Memory control device
JPS62113261A (en) * 1985-10-28 1987-05-25 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Arbitrator for computer system
JPS62263557A (en) * 1986-05-09 1987-11-16 Fujitsu Ltd Bus arbitration control system
JPS63106846A (en) * 1986-10-24 1988-05-11 Ando Electric Co Ltd Sequence designation circuit for extracting plural input signals
JPS63211059A (en) * 1987-02-27 1988-09-01 Meidensha Electric Mfg Co Ltd Precedence control system for computer system
JPH0782476B2 (en) * 1987-05-01 1995-09-06 ディジタル イクイプメント コーポレーション A system that controls access to the reservation bus by multiple nodes
JPH01270161A (en) * 1988-04-22 1989-10-27 Hitachi Ltd Common bus control system
JPH02115962A (en) * 1988-10-26 1990-04-27 K S D:Kk System for connecting computer device to its peripheral device
JP2008302781A (en) * 2007-06-06 2008-12-18 Univ Nagoya Communication method, communication system, and communication device

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