JPS6448154A - Bus arbitrating circuit with timeout monitor - Google Patents

Bus arbitrating circuit with timeout monitor

Info

Publication number
JPS6448154A
JPS6448154A JP62205433A JP20543387A JPS6448154A JP S6448154 A JPS6448154 A JP S6448154A JP 62205433 A JP62205433 A JP 62205433A JP 20543387 A JP20543387 A JP 20543387A JP S6448154 A JPS6448154 A JP S6448154A
Authority
JP
Japan
Prior art keywords
bus
time
master
circuit
monopolization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62205433A
Other languages
Japanese (ja)
Inventor
Kazunori Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62205433A priority Critical patent/JPS6448154A/en
Publication of JPS6448154A publication Critical patent/JPS6448154A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Abstract

PURPOSE:To prevent a specific master from monopolizing a bus by providing a time-out monitor circuit which sends a signal, by which the master releases the bus, when the bus monopolization time exceeds a preliminarily set time. CONSTITUTION:A bus arbitrating circuit 5 is provided with not only a bus request control circuit 51 and a priority control circuit 52 but also a time-out monitor circuit 35, and this circuit 35 monitors the bus monopolization time, and the circuits 35 sends the signal, by which the master releases the bus, to the master when this monopolization time exceeds a preliminarily set time. That is, in case of arbitration of bus request and priority in the bus arbitrating circuit 5, the time-out monitor circuit 53 monitors the time when the bus bus is monopolized; and when the monopolization time exceeds the preliminarily set time, the circuit 53 sends the bus releasing signal to the master to give an opportunity of monopolization to another master. Thus, the specific master is prevented from monopolizing the bus to improve the processing efficiency of each master.
JP62205433A 1987-08-19 1987-08-19 Bus arbitrating circuit with timeout monitor Pending JPS6448154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62205433A JPS6448154A (en) 1987-08-19 1987-08-19 Bus arbitrating circuit with timeout monitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62205433A JPS6448154A (en) 1987-08-19 1987-08-19 Bus arbitrating circuit with timeout monitor

Publications (1)

Publication Number Publication Date
JPS6448154A true JPS6448154A (en) 1989-02-22

Family

ID=16506785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62205433A Pending JPS6448154A (en) 1987-08-19 1987-08-19 Bus arbitrating circuit with timeout monitor

Country Status (1)

Country Link
JP (1) JPS6448154A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0449461A (en) * 1990-06-19 1992-02-18 Fujitsu Ltd Bus lock releasing system
JPH0696015A (en) * 1992-04-17 1994-04-08 Internatl Business Mach Corp <Ibm> Computer system and method for bus control synchronization and adjustment
EP0687121A3 (en) * 1994-06-10 1998-07-15 Fujitsu Limited Device and method for indicating timeouts
JP2009102332A (en) * 2001-07-19 2009-05-14 Akira Hayashi Immunotherapy for human

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0449461A (en) * 1990-06-19 1992-02-18 Fujitsu Ltd Bus lock releasing system
JPH0696015A (en) * 1992-04-17 1994-04-08 Internatl Business Mach Corp <Ibm> Computer system and method for bus control synchronization and adjustment
EP0687121A3 (en) * 1994-06-10 1998-07-15 Fujitsu Limited Device and method for indicating timeouts
JP2009102332A (en) * 2001-07-19 2009-05-14 Akira Hayashi Immunotherapy for human

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