JPS6472258A - Inter-processor data transfer system - Google Patents

Inter-processor data transfer system

Info

Publication number
JPS6472258A
JPS6472258A JP62227562A JP22756287A JPS6472258A JP S6472258 A JPS6472258 A JP S6472258A JP 62227562 A JP62227562 A JP 62227562A JP 22756287 A JP22756287 A JP 22756287A JP S6472258 A JPS6472258 A JP S6472258A
Authority
JP
Japan
Prior art keywords
mpu
processors
inter
data transfer
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62227562A
Other languages
Japanese (ja)
Inventor
Yuichi Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62227562A priority Critical patent/JPS6472258A/en
Publication of JPS6472258A publication Critical patent/JPS6472258A/en
Pending legal-status Critical Current

Links

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  • Multi Processors (AREA)

Abstract

PURPOSE:To transfer data between processors at a high speed with use of simple hardware by using a 1-bit hardware flag which is controlled by one of two processors and switching a bus between the processor and a shared memory according to the state of said flag. CONSTITUTION:The transceivers 5 and 6 having three different states are switched by the output of a flip-flop which is controlled by a slave microprocessor (MPU) 2. Then, a shared memory 4 is selectively connected to a master processor MPU 1 or the MPU 2. Thus a proper access is possible to the memory 4 from the MPU 1 or the MPU 2. Then the data can be transferred between both MPUs via the memory 4. As a result, the data are transferred at a high speed between both processors 1 and 2 via a simple circuit.
JP62227562A 1987-09-12 1987-09-12 Inter-processor data transfer system Pending JPS6472258A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62227562A JPS6472258A (en) 1987-09-12 1987-09-12 Inter-processor data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62227562A JPS6472258A (en) 1987-09-12 1987-09-12 Inter-processor data transfer system

Publications (1)

Publication Number Publication Date
JPS6472258A true JPS6472258A (en) 1989-03-17

Family

ID=16862855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62227562A Pending JPS6472258A (en) 1987-09-12 1987-09-12 Inter-processor data transfer system

Country Status (1)

Country Link
JP (1) JPS6472258A (en)

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