JPS6438860A - Inter-microprocessor interface system - Google Patents

Inter-microprocessor interface system

Info

Publication number
JPS6438860A
JPS6438860A JP19440087A JP19440087A JPS6438860A JP S6438860 A JPS6438860 A JP S6438860A JP 19440087 A JP19440087 A JP 19440087A JP 19440087 A JP19440087 A JP 19440087A JP S6438860 A JPS6438860 A JP S6438860A
Authority
JP
Japan
Prior art keywords
processor
microprocessor
int
signal
access right
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19440087A
Other languages
Japanese (ja)
Inventor
Shinya Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19440087A priority Critical patent/JPS6438860A/en
Publication of JPS6438860A publication Critical patent/JPS6438860A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To simplify a hardware scale by sharing a part of the memory area of a master microprocessor and a slave microprocessor, and executing the transfer of an access right into a shared area with an interrupting signal into the microprocessor. CONSTITUTION:As the shared memory of a master microprocessor 1 and a slave microprocessor 4, a shared memory 7 consisting of a RAM is provided, and the memory 7 is connected through a selector 10 with a bus 8 of the processor 1 and a bus 9 of the processor 4. Since the access right of a RAM 7 is arbitrated between the processor 1 and the processor 4, access right requiring interrupting signals INT 1 and INT 2 are prepared. The signal INT 1 is sent from the processor 1 through a signal line 12 to the processor 4, and the signal INT 2 is sent from the processor 4 through a signal line 13 to the processor 1. Thus, the hardware scale is simplified and processing efficiency can be improved.
JP19440087A 1987-08-05 1987-08-05 Inter-microprocessor interface system Pending JPS6438860A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19440087A JPS6438860A (en) 1987-08-05 1987-08-05 Inter-microprocessor interface system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19440087A JPS6438860A (en) 1987-08-05 1987-08-05 Inter-microprocessor interface system

Publications (1)

Publication Number Publication Date
JPS6438860A true JPS6438860A (en) 1989-02-09

Family

ID=16323969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19440087A Pending JPS6438860A (en) 1987-08-05 1987-08-05 Inter-microprocessor interface system

Country Status (1)

Country Link
JP (1) JPS6438860A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6505276B1 (en) 1998-06-26 2003-01-07 Nec Corporation Processing-function-provided packet-type memory system and method for controlling the same
JP2007178312A (en) * 2005-12-28 2007-07-12 Ryusyo Industrial Co Ltd Visual inspection device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61100856A (en) * 1984-10-22 1986-05-19 Fujitsu Ltd Shared memory controlling system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61100856A (en) * 1984-10-22 1986-05-19 Fujitsu Ltd Shared memory controlling system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6505276B1 (en) 1998-06-26 2003-01-07 Nec Corporation Processing-function-provided packet-type memory system and method for controlling the same
JP2007178312A (en) * 2005-12-28 2007-07-12 Ryusyo Industrial Co Ltd Visual inspection device

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